From 7592bbc474f64a644e80c22ab06950c84ebc8cf3 Mon Sep 17 00:00:00 2001
From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com>
Date: Sun, 17 May 2026 15:01:38 +0000
Subject: [PATCH 1/2] Initial plan


From 83dced1af938fad4245504b5b5076ea8c4e6931a Mon Sep 17 00:00:00 2001
From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com>
Date: Sun, 17 May 2026 15:06:26 +0000
Subject: [PATCH 2/2] fix assembler rmask handling for vector ops

Agent-Logs-Url: https://github.com/AICrossSim/PLENA_Compiler/sessions/99e4dcc6-281d-408c-b1ff-f0a4b8407743

Co-authored-by: gaoziqian123 <184267376+gaoziqian123@users.noreply.github.com>
---
 assembler/assembly_to_binary.py               |  6 +++-
 assembler/parser.py                           |  9 ++++++
 assembler/tests/test_vector_rmask_handling.py | 28 +++++++++++++++++++
 3 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 assembler/tests/test_vector_rmask_handling.py

diff --git a/assembler/assembly_to_binary.py b/assembler/assembly_to_binary.py
index bb3c578..10b5c28 100644
--- a/assembler/assembly_to_binary.py
+++ b/assembler/assembly_to_binary.py
@@ -40,6 +40,11 @@ def _convert_to_binary(self, instruction):
         binary_instruction = 0
         ow = self.operands_width
         opw = self.opcode_width
+        vector_ops_with_rmask = {"V_ADD_VV", "V_ADD_VF", "V_MUL_VV", "V_SUB_VV", "V_MUL_VF", "V_EXP_V", "V_RECI_V", "V_RED_SUM", "V_RED_MAX"}
+
+        if instruction.opcode in vector_ops_with_rmask and rmask is None:
+            # Treat omitted rmask deterministically as "mask disabled" instead of crashing on None << ...
+            rmask = 0
 
         if instruction.opcode in [
             "S_ADDI_INT",
@@ -140,4 +145,3 @@ def generate_binary(self, asm_file: str, output_file: str):
         self.write_binary_to_file(binary_instructions, output_file)
         return binary_instructions
 
-
diff --git a/assembler/parser.py b/assembler/parser.py
index 12306b2..69aeae4 100644
--- a/assembler/parser.py
+++ b/assembler/parser.py
@@ -109,6 +109,9 @@ def parse_asm_file(file_path: str) -> list[Instruction]:
     """
     instructions = []
 
+    vector_masked_unary_or_reduction_ops = {"V_EXP_V", "V_RECI_V", "V_RED_SUM", "V_RED_MAX"}
+    vector_masked_binary_ops = {"V_ADD_VV", "V_ADD_VF", "V_MUL_VV", "V_SUB_VV", "V_MUL_VF"}
+
     with open(file_path) as file:
         for line in file:
             # Remove comments and strip whitespace
@@ -190,6 +193,12 @@ def parse_reg_or_int(operand):
                         imm = int(operand_2)
                     except ValueError:
                         pass
+                if opcode in vector_masked_unary_or_reduction_ops:
+                    # Keep rmask/rstride aligned for 3-operand masked unary/reduction forms.
+                    rstride = imm
+                elif opcode in vector_masked_binary_ops:
+                    # Allow 3-operand vector ALU forms by defaulting omitted rmask to 0.
+                    rstride = 0
             elif len(operands) == 4:
                 operand_0, operand_1, operand_2, operand_3 = operands
                 rd = parse_reg_or_int(operand_0)
diff --git a/assembler/tests/test_vector_rmask_handling.py b/assembler/tests/test_vector_rmask_handling.py
new file mode 100644
index 0000000..b479884
--- /dev/null
+++ b/assembler/tests/test_vector_rmask_handling.py
@@ -0,0 +1,28 @@
+import unittest
+
+from assembler.assembly_to_binary import AssemblyToBinary
+from assembler.parser import Instruction, parse_asm_file
+
+
+class TestVectorRmaskHandling(unittest.TestCase):
+    def setUp(self):
+        self.asm = AssemblyToBinary("doc/operation.svh", "doc/configuration.svh")
+
+    def test_parser_sets_default_rmask_for_three_operand_vector_binary(self):
+        asm_path = "/tmp/plena_test_vector_binary_missing_rmask.asm"
+        with open(asm_path, "w") as f:
+            f.write("V_ADD_VV gp1, gp2, gp3\n")
+
+        parsed = parse_asm_file(asm_path)
+        self.assertEqual(len(parsed), 1)
+        self.assertEqual(parsed[0].rmask, 0)
+
+    def test_encoder_defaults_missing_rmask_to_zero(self):
+        explicit_mask = Instruction("V_ADD_VV", 1, 2, 3, 0, None, None, None)
+        missing_mask = Instruction("V_ADD_VV", 1, 2, 3, None, None, None, None)
+
+        self.assertEqual(self.asm._convert_to_binary(missing_mask), self.asm._convert_to_binary(explicit_mask))
+
+
+if __name__ == "__main__":
+    unittest.main()