feat: add profiling tracepoints to CPU runtime function implementations (Part 8)

Instrument key CPU runtime functions entry points in src/runtime/NEON/functions/* with
tracepoints to enable lightweight runtime profiling. These tracepoints
leverage the ACL_PROFILE macros and form the basis for collecting
execution timing and behavior metrics. This is the first step in
integrating end-to-end profiling support.

Partially Resolves: COMPMID-8330
Signed-off-by: Walid Ben Romdhane <Walid.BenRomdhane@arm.com>
Change-Id: I6701dff91eae53bcc96d0666b449c1a5844f4028
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/14780
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Andreas Flöjt <andreas.floejt@arm.com>

Author: walidbr

src/runtime/NEON/functions/NELSTMLayerQuantized.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, 2024 Arm Limited.
+ * Copyright (c) 2019-2021, 2024-2025 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -28,6 +28,7 @@
 #include "arm_compute/core/Validate.h"
 
 #include "src/common/utils/Log.h"
+#include "src/common/utils/profile/acl_profile.h"
 #include "src/core/helpers/AutoConfiguration.h"
 
 #include <cmath>
@@ -127,6 +128,7 @@ void NELSTMLayerQuantized::configure(const ITensor *input,
                                      ITensor       *cell_state_out,
                                      ITensor       *output_state_out)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELSTMLayerQuantized::configure");
     ARM_COMPUTE_ERROR_ON_NULLPTR(input, input_to_input_weights, input_to_forget_weights, input_to_cell_weights,
                                  input_to_output_weights, recurrent_to_input_weights, recurrent_to_forget_weights,
                                  recurrent_to_cell_weights, recurrent_to_output_weights, input_gate_bias,
@@ -363,6 +365,7 @@ Status NELSTMLayerQuantized::validate(const ITensorInfo *input,
                                       const ITensorInfo *cell_state_out,
                                       const ITensorInfo *output_state_out)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELSTMLayerQuantized::validate");
     ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(
         input, input_to_input_weights, input_to_forget_weights, input_to_cell_weights, input_to_output_weights,
         recurrent_to_input_weights, recurrent_to_forget_weights, recurrent_to_cell_weights, recurrent_to_output_weights,
@@ -629,6 +632,7 @@ Status NELSTMLayerQuantized::validate(const ITensorInfo *input,
 
 void NELSTMLayerQuantized::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELSTMLayerQuantized::run");
     prepare();
 
     // Acquire all the temporaries

src/runtime/NEON/functions/NELogical.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, 2024 Arm Limited.
+ * Copyright (c) 2020-2021, 2024-2025 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -27,6 +27,7 @@
 #include "arm_compute/runtime/Tensor.h"
 
 #include "src/common/utils/Log.h"
+#include "src/common/utils/profile/acl_profile.h"
 #include "src/core/NEON/kernels/NELogicalKernel.h"
 
 namespace arm_compute
@@ -47,6 +48,7 @@ NELogicalAnd::~NELogicalAnd() = default;
 
 void NELogicalAnd::configure(const ITensor *input1, const ITensor *input2, ITensor *output)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELogicalAnd::configure");
     ARM_COMPUTE_ERROR_ON_NULLPTR(input1, input2, output);
     ARM_COMPUTE_LOG_PARAMS(input1, input2, output);
 
@@ -61,12 +63,14 @@ void NELogicalAnd::configure(const ITensor *input1, const ITensor *input2, ITens
 
 Status NELogicalAnd::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELogicalAnd::validate");
     ARM_COMPUTE_RETURN_ERROR_ON_DYNAMIC_SHAPE(input1, input2, output);
     return kernels::NELogicalKernel::validate(input1, input2, output, LogicalOperation::And);
 }
 
 void NELogicalAnd::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELogicalAnd::run");
     NEScheduler::get().schedule_op(_impl->kernel.get(), Window::DimY, _impl->kernel->window(), _impl->pack);
 }
 
@@ -80,6 +84,7 @@ NELogicalOr::~NELogicalOr() = default;
 
 void NELogicalOr::configure(const ITensor *input1, const ITensor *input2, ITensor *output)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELogicalOr::configure");
     ARM_COMPUTE_ERROR_ON_NULLPTR(input1, input2, output);
     ARM_COMPUTE_LOG_PARAMS(input1, input2, output);
 
@@ -94,12 +99,14 @@ void NELogicalOr::configure(const ITensor *input1, const ITensor *input2, ITenso
 
 Status NELogicalOr::validate(const ITensorInfo *input1, const ITensorInfo *input2, const ITensorInfo *output)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELogicalOr::validate");
     ARM_COMPUTE_RETURN_ERROR_ON_DYNAMIC_SHAPE(input1, input2, output);
     return kernels::NELogicalKernel::validate(input1, input2, output, LogicalOperation::Or);
 }
 
 void NELogicalOr::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELogicalOr::run");
     NEScheduler::get().schedule_op(_impl->kernel.get(), Window::DimY, _impl->kernel->window(), _impl->pack);
 }
 
@@ -113,6 +120,7 @@ NELogicalNot::~NELogicalNot() = default;
 
 void NELogicalNot::configure(const ITensor *input, ITensor *output)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELogicalNot::configure");
     ARM_COMPUTE_ERROR_ON_NULLPTR(input, output);
     ARM_COMPUTE_LOG_PARAMS(input, output);
 
@@ -126,12 +134,14 @@ void NELogicalNot::configure(const ITensor *input, ITensor *output)
 
 Status NELogicalNot::validate(const ITensorInfo *input, const ITensorInfo *output)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELogicalNot::validate");
     ARM_COMPUTE_RETURN_ERROR_ON_DYNAMIC_SHAPE(input, output);
     return kernels::NELogicalKernel::validate(input, nullptr, output, LogicalOperation::Not);
 }
 
 void NELogicalNot::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NELogicalNot::run");
     NEScheduler::get().schedule_op(_impl->kernel.get(), Window::DimY, _impl->kernel->window(), _impl->pack);
 }
 } // namespace arm_compute

src/runtime/NEON/functions/NEMatMul.cpp

@@ -27,6 +27,7 @@
 #include "arm_compute/runtime/MemoryGroup.h"
 #include "arm_compute/runtime/Tensor.h"
 
+#include "src/common/utils/profile/acl_profile.h"
 #include "src/core/helpers/MemoryHelpers.h"
 #include "src/cpu/operators/CpuMatMul.h"
 
@@ -56,6 +57,7 @@ void NEMatMul::configure(ITensor                   *lhs,
                          const CpuMatMulSettings   &settings,
                          const ActivationLayerInfo &act_info)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEMatMul::configure");
     _impl->lhs    = lhs;
     _impl->rhs    = rhs;
     _impl->output = output;
@@ -74,12 +76,14 @@ Status NEMatMul::validate(const ITensorInfo         *lhs,
                           const CpuMatMulSettings   &settings,
                           const ActivationLayerInfo &act_info)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEMatMul::validate");
     ARM_COMPUTE_RETURN_ERROR_ON_DYNAMIC_SHAPE(lhs, rhs, output);
     return cpu::CpuMatMul::validate(lhs, rhs, output, info, settings, act_info);
 }
 
 void NEMatMul::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEMatMul::run");
     MemoryGroupResourceScope scope_mg(_impl->memory_group);
     _impl->op->run(_impl->run_pack);
 }

src/runtime/NEON/functions/NEMaxUnpoolingLayer.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, 2024 Arm Limited.
+ * Copyright (c) 2020-2022, 2024-2025 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -29,6 +29,7 @@
 #include "arm_compute/runtime/NEON/NEScheduler.h"
 
 #include "src/common/utils/Log.h"
+#include "src/common/utils/profile/acl_profile.h"
 #include "src/cpu/kernels/CpuMaxUnpoolingLayerKernel.h"
 #include "src/cpu/operators/CpuMaxUnpooling.h"
 
@@ -53,6 +54,7 @@ void NEMaxUnpoolingLayer::configure(ITensor                *input,
                                     ITensor                *output,
                                     const PoolingLayerInfo &pool_info)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEMaxUnpoolingLayer::configure");
     ARM_COMPUTE_LOG_PARAMS(input, indices, output, pool_info);
 
     const PixelValue zero_value(0.f);
@@ -72,6 +74,7 @@ Status NEMaxUnpoolingLayer::validate(const ITensorInfo      *input,
                                      const ITensorInfo      *output,
                                      const PoolingLayerInfo &pool_info)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEMaxUnpoolingLayer::validate");
     ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input, output, indices);
     ARM_COMPUTE_RETURN_ERROR_ON_DYNAMIC_SHAPE(input, indices, output);
     ARM_COMPUTE_RETURN_ON_ERROR(cpu::CpuMaxUnpooling::validate(input, indices, output, pool_info));
@@ -80,6 +83,7 @@ Status NEMaxUnpoolingLayer::validate(const ITensorInfo      *input,
 
 void NEMaxUnpoolingLayer::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEMaxUnpoolingLayer::run");
     ITensorPack pack;
     pack.add_tensor(TensorType::ACL_SRC_0, _impl->src);
     pack.add_tensor(TensorType::ACL_SRC_1, _impl->indices);

src/runtime/NEON/functions/NEMeanStdDevNormalizationLayer.cpp

@@ -26,6 +26,7 @@
 #include "arm_compute/core/Validate.h"
 
 #include "src/common/utils/Log.h"
+#include "src/common/utils/profile/acl_profile.h"
 #include "src/cpu/operators/CpuMeanStdDevNormalization.h"
 
 namespace arm_compute
@@ -45,6 +46,8 @@ NEMeanStdDevNormalizationLayer::~NEMeanStdDevNormalizationLayer() = default;
 
 void NEMeanStdDevNormalizationLayer::configure(ITensor *input, ITensor *output, float epsilon)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU,
+                            "NEMeanStdDevNormalizationLayer::configure");
     _impl->input  = input;
     _impl->output = (output == nullptr) ? input : output;
     _impl->op     = std::make_unique<cpu::CpuMeanStdDevNormalization>();
@@ -53,11 +56,14 @@ void NEMeanStdDevNormalizationLayer::configure(ITensor *input, ITensor *output,
 
 Status NEMeanStdDevNormalizationLayer::validate(const ITensorInfo *input, const ITensorInfo *output, float epsilon)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU,
+                            "NEMeanStdDevNormalizationLayer::validate");
     return cpu::CpuMeanStdDevNormalization::validate(input, output, epsilon);
 }
 
 void NEMeanStdDevNormalizationLayer::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEMeanStdDevNormalizationLayer::run");
     ITensorPack pack;
     pack.add_tensor(TensorType::ACL_SRC, _impl->input);
     pack.add_tensor(TensorType::ACL_DST, _impl->output);

src/runtime/NEON/functions/NENormalizationLayer.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, 2024 Arm Limited.
+ * Copyright (c) 2017-2021, 2024-2025 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -31,6 +31,7 @@
 #include "arm_compute/runtime/NEON/NEScheduler.h"
 
 #include "src/common/utils/Log.h"
+#include "src/common/utils/profile/acl_profile.h"
 #include "src/core/NEON/kernels/NENormalizationLayerKernel.h"
 
 namespace arm_compute
@@ -44,6 +45,7 @@ NENormalizationLayer::NENormalizationLayer(std::shared_ptr<IMemoryManager> memor
 
 void NENormalizationLayer::configure(const ITensor *input, ITensor *output, const NormalizationLayerInfo &norm_info)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NENormalizationLayer::configure");
     ARM_COMPUTE_ERROR_ON_NULLPTR(input, output);
     ARM_COMPUTE_LOG_PARAMS(input, output, norm_info);
 
@@ -66,6 +68,7 @@ Status NENormalizationLayer::validate(const ITensorInfo            *input,
                                       const ITensorInfo            *output,
                                       const NormalizationLayerInfo &norm_info)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NENormalizationLayer::validate");
     // Perform validation step
     ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input, output);
     ARM_COMPUTE_RETURN_ERROR_ON_DYNAMIC_SHAPE(input, output);
@@ -79,6 +82,7 @@ Status NENormalizationLayer::validate(const ITensorInfo            *input,
 
 void NENormalizationLayer::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NENormalizationLayer::run");
     MemoryGroupResourceScope scope_mg(_memory_group);
     _multiply_f.run();
     NEScheduler::get().schedule(_norm_kernel.get(), Window::DimY);

src/runtime/NEON/functions/NEPReluLayer.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, 2024 Arm Limited.
+ * Copyright (c) 2019-2021, 2024-2025 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -26,6 +26,7 @@
 #include "arm_compute/core/ITensor.h"
 #include "arm_compute/core/Validate.h"
 
+#include "src/common/utils/profile/acl_profile.h"
 #include "src/cpu/operators/CpuPRelu.h"
 
 namespace arm_compute
@@ -49,6 +50,7 @@ NEPReluLayer::~NEPReluLayer()                          = default;
 
 void NEPReluLayer::configure(const ITensor *input, const ITensor *alpha, ITensor *output)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEPReluLayer::configure");
     _impl->src_0 = input;
     _impl->src_1 = alpha;
     _impl->dst   = output;
@@ -58,6 +60,7 @@ void NEPReluLayer::configure(const ITensor *input, const ITensor *alpha, ITensor
 
 void NEPReluLayer::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEPReluLayer::run");
     ITensorPack pack;
     pack.add_tensor(TensorType::ACL_SRC_0, _impl->src_0);
     pack.add_tensor(TensorType::ACL_SRC_1, _impl->src_1);
@@ -67,6 +70,7 @@ void NEPReluLayer::run()
 
 Status NEPReluLayer::validate(const ITensorInfo *input, const ITensorInfo *alpha, const ITensorInfo *output)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEPReluLayer::validate");
     ARM_COMPUTE_RETURN_ERROR_ON_DYNAMIC_SHAPE(input, alpha, output);
     return OperatorType::validate(input, alpha, output);
 }

src/runtime/NEON/functions/NEPadLayer.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2021, 2024 Arm Limited.
+ * Copyright (c) 2018-2021, 2024-2025 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -28,6 +28,7 @@
 #include "arm_compute/runtime/NEON/NEScheduler.h"
 
 #include "src/common/utils/Log.h"
+#include "src/common/utils/profile/acl_profile.h"
 #include "src/core/helpers/AutoConfiguration.h"
 #include "src/core/NEON/kernels/NEPadLayerKernel.h"
 
@@ -189,6 +190,7 @@ void NEPadLayer::configure(ITensor           *input,
                            const PixelValue   constant_value,
                            const PaddingMode  mode)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEPadLayer::configure");
     ARM_COMPUTE_ERROR_THROW_ON(validate(input->info(), output->info(), padding, constant_value, mode));
     ARM_COMPUTE_LOG_PARAMS(input, output, padding, constant_value, mode);
 
@@ -234,6 +236,7 @@ Status NEPadLayer::validate(const ITensorInfo *input,
                             const PixelValue   constant_value,
                             const PaddingMode  mode)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEPadLayer::validate");
     ARM_COMPUTE_UNUSED(constant_value);
     ARM_COMPUTE_RETURN_ERROR_ON_DYNAMIC_SHAPE(input, output);
 
@@ -279,6 +282,7 @@ Status NEPadLayer::validate(const ITensorInfo *input,
 
 void NEPadLayer::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEPadLayer::run");
     if (_num_dimensions > 0)
     {
         switch (_mode)

src/runtime/NEON/functions/NEPermute.cpp

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2021, 2024 Arm Limited.
+ * Copyright (c) 2017-2021, 2024-2025 Arm Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -25,6 +25,7 @@
 
 #include "arm_compute/core/Validate.h"
 
+#include "src/common/utils/profile/acl_profile.h"
 #include "src/cpu/operators/CpuPermute.h"
 
 namespace arm_compute
@@ -44,6 +45,7 @@ NEPermute::~NEPermute() = default;
 
 void NEPermute::configure(const ITensor *input, ITensor *output, const PermutationVector &perm)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEPermute::configure");
     ARM_COMPUTE_ERROR_ON_NULLPTR(input, output);
 
     _impl->src = input;
@@ -54,6 +56,7 @@ void NEPermute::configure(const ITensor *input, ITensor *output, const Permutati
 
 Status NEPermute::validate(const ITensorInfo *input, const ITensorInfo *output, const PermutationVector &perm)
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEPermute::validate");
     ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(input, output);
     ARM_COMPUTE_RETURN_ERROR_ON_DYNAMIC_SHAPE(input, output);
     ARM_COMPUTE_RETURN_ON_ERROR(cpu::CpuPermute::validate(input, output, perm));
@@ -63,6 +66,7 @@ Status NEPermute::validate(const ITensorInfo *input, const ITensorInfo *output,
 
 void NEPermute::run()
 {
+    ARM_COMPUTE_TRACE_EVENT(ARM_COMPUTE_PROF_CAT_CPU, ARM_COMPUTE_PROF_LVL_CPU, "NEPermute::run");
     ITensorPack pack;
     pack.add_tensor(TensorType::ACL_SRC, _impl->src);
     pack.add_tensor(TensorType::ACL_DST, _impl->dst);