Merge pull request #1 from AntidoteDB/map-based

Map based

Author: bieniusa

.travis.yml

@@ -1,13 +1,12 @@
 language: erlang
 otp_release:
-  - 19.3
-  - 20.3
-  - 21.0
+  - 21.2
 install:
   - make
 script:
   - make test
   - make dialyzer
   - make lint
+  - rebar3 as test coveralls send
 sudo: required
 dist: trusty

Makefile

@@ -8,7 +8,7 @@ compile:
 clean:
 	$(REBAR) clean
 
-distclean: clean relclean
+distclean: clean
 	$(REBAR) clean --all
 
 cleantests:
@@ -18,7 +18,7 @@ cleantests:
 test:
 	mkdir -p logs
 	${REBAR} eunit
-	${REBAR} cover
+	${REBAR} cover --verbose
 
 docs:
 	${REBAR} doc

README.md

@@ -1,5 +1,7 @@
 vectorclock
-=====
+===========
+
 [![Build Status](https://travis-ci.org/AntidoteDB/vectorclock.svg?branch=master)](https://travis-ci.org/AntidoteDB/vectorclock)
+[![Coverage Status](https://coveralls.io/repos/github/AntidoteDB/vectorclock/badge.svg?branch=master)](https://coveralls.io/github/AntidoteDB/vectorclock?branch=master)
 
 A vectorclock library for Erlang.

rebar.config

@@ -5,10 +5,17 @@
 {profiles,[
   {lint, [
     {plugins, [{rebar3_lint, {git, "https://github.com/project-fifo/rebar3_lint.git", {tag, "0.1.2"}}}]}
-  ]}
+  ]},
+  {test, [
+    {erl_opts, [warnings_as_errors, debug_info, no_inline_list_funcs]},
+    {plugins, [{coveralls, {git, "https://github.com/markusn/coveralls-erl", {branch, "master"}}}]}]}
 ]}.
 
 {cover_enabled, true}.
+{plugins, [coveralls]}.
+{cover_export_enabled, true}.
+{coveralls_coverdata, "_build/test/cover/eunit.coverdata"}.
+{coveralls_service_name, "travis-ci"}.
 
 % configuration of style rules
 {elvis,
@@ -34,12 +41,11 @@
         #{regex => "^[a-z]([a-z0-9]*_?)*(_SUITE)?$",
           ignore => []}
       },
-      % Can be added back if antidote_crdt_counter_b:localPermissions is renamed
-      %{
-      %  elvis_style,
-      %  function_naming_convention,
-      %  #{regex => "^([a-z][a-z0-9]*_?)*$"}
-      %},
+      {
+        elvis_style,
+        function_naming_convention,
+        #{regex => "^([a-z][a-z0-9]*_?)*$"}
+      },
       {elvis_style, state_record_and_type},
       {elvis_style, no_spec_with_records}
     ]

rebar.config.script

@@ -0,0 +1,6 @@
+case os:getenv("TRAVIS") of
+    "true" ->
+        lists:keystore(coveralls_service_job_id, 1, CONFIG, {coveralls_service_job_id, os:getenv("TRAVIS_JOB_ID")});
+    _ ->
+        CONFIG
+end.

src/vectorclock.app.src

@@ -1,6 +1,6 @@
 {application, vectorclock,
- [{description, "An vectorclock library for Erlang"},
-  {vsn, "0.1.0"},
+ [{description, "A vectorclock library for Erlang"},
+  {vsn, "0.0.2"},
   {registered, []},
   {applications,
    [kernel,

src/vectorclock.erl

@@ -39,34 +39,43 @@
          min/1,
          conc/2]).
 
-
 -type actor() :: any().
--type vectorclock() :: dict:dict(actor(), non_neg_integer()).
+-type vectorclock() :: #{actor() => non_neg_integer()}.
 -export_type([vectorclock/0]).
 
 -spec new() -> vectorclock().
 new() ->
-    dict:new().
+    maps:new().
 
 -spec get_clock_of_dc(any(), vectorclock()) -> non_neg_integer().
 get_clock_of_dc(Key, VectorClock) ->
-  case dict:find(Key, VectorClock) of
-    {ok, Value} -> Value;
-    error -> 0
-  end.
+  maps:get(Key, VectorClock, 0).
 
 -spec set_clock_of_dc(any(), non_neg_integer(), vectorclock()) -> vectorclock().
 set_clock_of_dc(Key, Value, VectorClock) ->
-  dict:store(Key, Value, VectorClock).
+  VectorClock#{Key => Value}.
 
 -spec from_list([{any(), non_neg_integer()}]) -> vectorclock().
 from_list(List) ->
-    dict:from_list(List).
+  maps:from_list(List).
 
 -spec max([vectorclock()]) -> vectorclock().
 max([]) -> new();
 max([V]) -> V;
-max([V1, V2|T]) -> max([merge(fun erlang:max/2, V1, V2)|T]).
+max([V1, V2|T]) -> max([max2(V1, V2)|T]).
+
+%% component-wise maximum of two clocks
+-spec max2(vectorclock(), vectorclock()) -> vectorclock().
+max2(V1, V2) ->
+  FoldFun =
+    fun(DC, A, Acc) ->
+      B = get_clock_of_dc(DC, Acc),
+      case A > B of
+        true -> Acc#{DC => A};
+        false -> Acc
+      end
+    end,
+  maps:fold(FoldFun, V2, V1).
 
 -spec min([vectorclock()]) -> vectorclock().
 min([]) -> new();
@@ -75,7 +84,7 @@ min([V1, V2|T]) -> min([merge(fun erlang:min/2, V1, V2)|T]).
 
 -spec merge(fun((non_neg_integer(), non_neg_integer()) -> non_neg_integer()), vectorclock(), vectorclock()) -> vectorclock().
 merge(F, V1, V2) ->
-  AllDCs = dict:fetch_keys(V1) ++ dict:fetch_keys(V2),
+  AllDCs = maps:keys(maps:merge(V1, V2)),
   Func = fun(DC) ->
     A = get_clock_of_dc(DC, V1),
     B = get_clock_of_dc(DC, V2),
@@ -85,8 +94,7 @@ merge(F, V1, V2) ->
 
 -spec for_all_keys(fun((non_neg_integer(), non_neg_integer()) -> boolean()), vectorclock(), vectorclock()) -> boolean().
 for_all_keys(F, V1, V2) ->
-  %% We could but do not care about duplicate DC keys - finding duplicates is not worth the effort
-  AllDCs = dict:fetch_keys(V1) ++ dict:fetch_keys(V2),
+  AllDCs = maps:keys(maps:merge(V1, V2)),
   Func = fun(DC) ->
     A = get_clock_of_dc(DC, V1),
     B = get_clock_of_dc(DC, V2),
@@ -95,13 +103,23 @@ for_all_keys(F, V1, V2) ->
   lists:all(Func, AllDCs).
 
 -spec eq(vectorclock(), vectorclock()) -> boolean().
-eq(V1, V2) -> for_all_keys(fun(A, B) -> A == B end, V1, V2).
+eq(V1, V2) -> le(V1, V2) andalso le(V2, V1).
 
 -spec le(vectorclock(), vectorclock()) -> boolean().
-le(V1, V2) -> for_all_keys(fun(A, B) -> A =< B end, V1, V2).
+le(V1, V2) ->
+  try
+    maps:fold(fun (DC, V, true) ->
+                case V =< get_clock_of_dc(DC, V2) of
+                  true -> true;
+                  false -> throw(false)
+                end
+              end, true, V1)
+  catch
+    false -> false
+  end .
 
 -spec ge(vectorclock(), vectorclock()) -> boolean().
-ge(V1, V2) -> for_all_keys(fun(A, B) -> A >= B end, V1, V2).
+ge(V1, V2) -> le(V2, V1).
 
 -spec all_dots_smaller(vectorclock(), vectorclock()) -> boolean().
 all_dots_smaller(V1, V2) -> for_all_keys(fun(A, B) -> A < B end, V1, V2).
@@ -110,16 +128,41 @@ all_dots_smaller(V1, V2) -> for_all_keys(fun(A, B) -> A < B end, V1, V2).
 all_dots_greater(V1, V2) -> for_all_keys(fun(A, B) -> A > B end, V1, V2).
 
 -spec gt(vectorclock(), vectorclock()) -> boolean().
-gt(V1, V2) -> ge(V1, V2) and (not eq(V1, V2)).
+gt(V1, V2) -> lt(V2, V1).
 
 -spec lt(vectorclock(), vectorclock()) -> boolean().
-lt(V1, V2) -> le(V1, V2) and (not eq(V1, V2)).
+lt(V1, V2) ->
+  try
+    maps:fold(fun (DC, V, Acc) ->
+                X = get_clock_of_dc(DC, V2),
+                case V =< X of
+                  true -> Acc orelse V < X;
+                  false -> throw(false)
+                end
+              end, false, V1)
+    orelse
+    maps:fold(fun (DC, V, _) ->
+                X = get_clock_of_dc(DC, V1),
+                case V > X of
+                  true -> throw(true);
+                  false -> false
+                end
+              end, false, V2)
+  catch
+    R -> R
+  end .
 
 -spec conc(vectorclock(), vectorclock()) -> boolean().
 conc(V1, V2) -> (not ge(V1, V2)) andalso (not le(V1, V2)).
 
 -ifdef(TEST).
 
+vectorclock_empty_test() ->
+    V1 = vectorclock:new(),
+    V2 = vectorclock:from_list([]),
+    ?assertEqual(V1, V2),
+    ?assertEqual(eq(vectorclock:min([]), vectorclock:max([])), true).
+
 vectorclock_test() ->
     V1 = vectorclock:from_list([{1, 5}, {2, 4}, {3, 5}, {4, 6}]),
     V2 = vectorclock:from_list([{1, 4}, {2, 3}, {3, 4}, {4, 5}]),
@@ -136,6 +179,11 @@ vectorclock_test() ->
     ?assertEqual(eq(V1, V4), false),
     ?assertEqual(ge(V1, V5), false).
 
+vectorclock_lt_test() ->
+  ?assertEqual(lt(from_list([{a, 1}]), from_list([{a, 1}, {b, 1}])), true),
+  ?assertEqual(lt(from_list([{a, 1}]), from_list([{a, 1}])), false),
+  ?assertEqual(lt(from_list([{a, 2}]), from_list([{a, 1}])), false).
+
 vectorclock_max_test() ->
   V1 = vectorclock:from_list([{1, 5}, {2, 4}]),
   V2 = vectorclock:from_list([{1, 6}, {2, 3}]),
@@ -153,7 +201,6 @@ vectorclock_max_test() ->
   ?assertEqual(eq(max([V1, V2, V3]), Expected123), true),
   ?assertEqual(eq(max([V1, V2, V3]), Unexpected123), false).
 
-
 vectorclock_min_test() ->
   V1 = vectorclock:from_list([{1, 5}, {2, 4}]),
   V2 = vectorclock:from_list([{1, 6}, {2, 3}]),
@@ -169,7 +216,8 @@ vectorclock_min_test() ->
   ?assertEqual(eq(min([V2, V3]), Expected23), true),
   ?assertEqual(eq(min([V1, V3]), Expected13), true),
   ?assertEqual(eq(min([V1, V2, V3]), Expected123), true),
-  ?assertEqual(eq(min([V1, V2, V3]), Unexpected123), false).
+  ?assertEqual(eq(min([V1, V2, V3]), Unexpected123), false),
+  ?assertEqual(eq(vectorclock:min([V1]), vectorclock:max([V1])), true).
 
 vectorclock_conc_test() ->
   V1 = vectorclock:from_list([{1, 5}, {2, 4}]),
@@ -182,4 +230,13 @@ vectorclock_conc_test() ->
   ?assertEqual(conc(V2, V3), true),
   ?assertEqual(conc(V3, V4), false),
   ?assertEqual(conc(V5, V4), false).
+
+vectorclock_set_test() ->
+  V1 = vectorclock:from_list([{1, 1}, {2, 2}]),
+  V2 = vectorclock:from_list([{1, 1}, {2, 2}, {3, 3}]),
+  V3 = vectorclock:from_list([{1, 1}, {2, 4}]),
+
+  ?assertEqual(eq(V2, vectorclock:set_clock_of_dc(3, 3, V1)), true),
+  ?assertEqual(eq(V3, vectorclock:set_clock_of_dc(2, 4, V1)), true).
+
 -endif.