ArmDeveloperEcosystem
diff --git a/‎acpi.py‎ ‎src/acpi.py‎acpi.py renamed to src/acpi.py b/‎acpi.py‎ ‎src/acpi.py‎acpi.py renamed to src/acpi.py
diff --git a/‎chi_spec.py‎ ‎src/chi_spec.py‎chi_spec.py renamed to src/chi_spec.py b/‎chi_spec.py‎ ‎src/chi_spec.py‎chi_spec.py renamed to src/chi_spec.py
diff --git a/‎cmn_base.py‎ ‎src/cmn_base.py‎cmn_base.py renamed to src/cmn_base.py
Lines changed: 3 additions & 0 deletions b/‎cmn_base.py‎ ‎src/cmn_base.py‎cmn_base.py renamed to src/cmn_base.py
Lines changed: 3 additions & 0 deletions
diff --git a/‎cmn_cpu.py‎ ‎src/cmn_cpu.py‎cmn_cpu.py renamed to src/cmn_cpu.py b/‎cmn_cpu.py‎ ‎src/cmn_cpu.py‎cmn_cpu.py renamed to src/cmn_cpu.py
diff --git a/‎cmn_detect_cpu.py‎ ‎src/cmn_detect_cpu.py‎cmn_detect_cpu.py renamed to src/cmn_detect_cpu.py b/‎cmn_detect_cpu.py‎ ‎src/cmn_detect_cpu.py‎cmn_detect_cpu.py renamed to src/cmn_detect_cpu.py
diff --git a/‎cmn_devmem.py‎ ‎src/cmn_devmem.py‎cmn_devmem.py renamed to src/cmn_devmem.py b/‎cmn_devmem.py‎ ‎src/cmn_devmem.py‎cmn_devmem.py renamed to src/cmn_devmem.py
diff --git a/‎cmn_devmem_find.py‎ ‎src/cmn_devmem_find.py‎cmn_devmem_find.py renamed to src/cmn_devmem_find.py b/‎cmn_devmem_find.py‎ ‎src/cmn_devmem_find.py‎cmn_devmem_find.py renamed to src/cmn_devmem_find.py
diff --git a/‎cmn_diagram.py‎ ‎src/cmn_diagram.py‎cmn_diagram.py renamed to src/cmn_diagram.py b/‎cmn_diagram.py‎ ‎src/cmn_diagram.py‎cmn_diagram.py renamed to src/cmn_diagram.py
diff --git a/‎cmn_discover.py‎ ‎src/cmn_discover.py‎cmn_discover.py renamed to src/cmn_discover.py b/‎cmn_discover.py‎ ‎src/cmn_discover.py‎cmn_discover.py renamed to src/cmn_discover.py
diff --git a/‎cmn_enum.py‎ ‎src/cmn_enum.py‎cmn_enum.py renamed to src/cmn_enum.py b/‎cmn_enum.py‎ ‎src/cmn_enum.py‎cmn_enum.py renamed to src/cmn_enum.py
@@ -305,6 +305,9 @@ def cpus(self):
             if cpu.CMN() == self:
                 yield cpu
 
+    def has_cpu_mappings(self):
+        return self.owner.has_cpu_mappings()
+
     def port_at_id(self, base_id):
         # Get the CMNPort object with a given base id.
         for p in self.ports():