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fix uart
1 parent d6b5f57 commit 0db98b4

1 file changed

Lines changed: 4 additions & 3 deletions

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02.inputs/uart.py

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,10 @@
44
uart = UART(2) # UART(2) RX16 TX17
55
uart.init(57600, bits=8, parity=None, stop=1)
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7+
time.sleep(1)
8+
uart.write("hello\n")
9+
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while True:
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recvlen = uart.any()
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if recvlen > 0:
10-
uart.write(uart.read(1))
11-
# uart.write("hello\n")
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# time.sleep(1)
13+
uart.write(uart.read(recvlen))

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