Merge branch 'master' of https://github.com/CSRG-Group/dcs-notes.github.io

Author: EdmundGoodman

_CS126/digraphs.md

@@ -13,7 +13,7 @@ title: "Directed Graphs"
 
 ### Properties
 
-If a **simple** directed graph has $$m$$ edges and $n$ vertices, then $$m \leq n \cdot (n-1)$$, since every vertex can connect to every other vertex bar itself
+If a **simple** directed graph has $$m$$ edges and $$n$$ vertices, then $$m \leq n \cdot (n-1)$$, since every vertex can connect to every other vertex bar itself
 
 There is more terminology specifically about digraphs:
 

_CS132/index.md

@@ -7,15 +7,6 @@ title: CS132
 
 ## Topics and content
 
-There are five broad topics in the module, which are as follows:
-
-1. Data representation
-2. Digital logic
-3. Assembler
-4. Memory systems
-5. I/O mechanisms
-6. Processor architecture
-
 In the words of Matt, **all of the above topics are examinable**. However, there
 are varying degrees of usefulness for each of the topics - if something is not
 deemed overly useful, it will typically be omitted in the notes. For example,
@@ -24,19 +15,7 @@ omitted (for example, specific operations of the circuit).
 
 ## Complete notes
 
-Detailed handwritten notes for CS132 by **Josh Fitzmaurice** which cover the
-entire module can be found [here](./CS132_full.pdf).
-
-Detailed typed notes for CS132 by **Yijun Hu** can be found [here](https://www.yijun.hu/blog-cs/cs132/index.html).
-
-1. [x] [Data representation](https://www.yijun.hu/blog-cs/cs132/index.html#)
-2. [x] [Digital logic](https://www.yijun.hu/blog-cs/cs132/index.html#)
-3. [x] [Assembler](https://www.yijun.hu/blog-cs/cs132/index.html#)
-4. [x] [Memory systems](https://www.yijun.hu/blog-cs/cs132/index.html#)
-5. [x] [I/O mechanisms](https://www.yijun.hu/blog-cs/cs132/index.html#)
-6. [x] [Processor architecture](https://www.yijun.hu/blog-cs/cs132/index.html#)
-
-Another source of type notes (from **Akram Ahmad** and **Justin Tan**’s notes) can be found below in parts or
+Detailed typed notes for CS132 by **Akram Ahmad** and **Justin Tan**’s can be found below in parts or
 here for [CS132 One Page Notes](opnotes):
 
 1. [x] [Data representation](part1)
@@ -46,7 +25,17 @@ here for [CS132 One Page Notes](opnotes):
 5. [x] [I/O mechanisms](part5)
 6. [x] [Processor architecture](part6)
 
+Another source of type notes by **Yijun Hu** can be found [here](https://www.yijun.hu/blog-cs/cs132/index.html).
 
+1. [x] [Data representation](https://www.yijun.hu/blog-cs/cs132/index.html#)
+2. [x] [Digital logic](https://www.yijun.hu/blog-cs/cs132/index.html#)
+3. [x] [Assembler](https://www.yijun.hu/blog-cs/cs132/index.html#)
+4. [x] [Memory systems](https://www.yijun.hu/blog-cs/cs132/index.html#)
+5. [x] [I/O mechanisms](https://www.yijun.hu/blog-cs/cs132/index.html#)
+6. [x] [Processor architecture](https://www.yijun.hu/blog-cs/cs132/index.html#)
+
+Detailed handwritten notes for CS132 by **Josh Fitzmaurice** which cover the
+entire module can be found [here](./CS132_full.pdf).
 
 ## Unofficial worksheet solutions
 
@@ -69,4 +58,4 @@ A document containing all of the typed solutions linked above concatenated toget
 
 Here are a set of flashcards for the module by **Leon Chipchase** (they still need to be refined), and please message me if there is something incorrect on there.
 
-[Flash Cards](https://quizlet.com/_9pgkq4?x=1jqt&i=18al03)
+[Flash Cards](https://quizlet.com/_9pgkq4?x=1jqt&i=18al03)

_CS132/part6.md

@@ -85,7 +85,8 @@ The dominant technique, since roughly 1980s, for implementing control units in R
 | ------------------------------------------------------- | ------------------------------------------------------------ |
 | **Sequencer** – takes clock input of our microprocessor | Regulates/aligns the operation of the combinatorial logic circuit in the CU with the control steps/rounds we have for each macro instruction. These regulated signals should ideally match the clock frequency. |
 | **Instruction Decoder**                                 | Depending on the opcode, send a signal to a certain path that corresponds to a particular macro instruction. |
-| **Fetch/Execute flip-flop**                             | Works together with the sequencer to regulate control rounds. It asserts when a control round starts and ends, essentially ensuring that the sequencer is in sync. |
+| **Fetch/Execute flip-flop**                             | Depending on the `START_FETCH` and `START_EXECUTE` signals, the flip-flop ensures that the CPU is only ever **fetching** or carrying out an opcode instruction (XOR relationship). |
+| `START_FETCH` & `START_EXECUTE`                         | When high, these two signals reset the sequencer so that it is in sync with the fetch/execute flip-flop’s signals (either the Enable signal to the opcode decoder or the fetch signal). |
 
 > **Advantages.** Fast (operates as fast as logic gates).
 >

_CS141/index.md

@@ -9,11 +9,11 @@ Given the large number of topics, it makes sense to break these down into broade
 
 1. [x] [General Functional Programming](part1)
 2. [x] [Lazy Evaluation & Recursion](part2)
-3. [ ] Higher-Order Functions
+3. [ ] Higher-Order Functions 
 4. [x] [Data types](datatypes)
 5. [x] [Equational reasoning](equationalReasoning)
 6. [x] [Functors, Applicatives, Monads](FAM)
-7. [ ] Type-level programming
+7. [x] [Type-level programming](type-level-programming)
 
 ## Crib Sheets
 

_CS141/type-level-programming.md

@@ -1,3 +1,9 @@
+---
+layout: CS141
+part: true
+title: Type Level Programming
+---
+
 ## Kinds
 
 > Just like how expressions have **types**, types have **kinds**.