added stuff

ryancramuh · ryancramuh · commit 5e5f5f2a37ab · 2026-01-29T09:05:48.000-08:00
diff --git a/.gitignore b/.gitignore
@@ -176,3 +176,5 @@ cython_debug/
 .pypirc
 
 /_site/
+
+/just/
diff --git a/source/_static/pdf/meeting-slides/intro_to_formal.pdf b/source/_static/pdf/meeting-slides/intro_to_formal.pdf
diff --git a/source/docs/formal_verif.rst b/source/docs/formal_verif.rst
@@ -0,0 +1,8 @@
+Intro to ASIC Formal Verification
+=====================================
+
+View the `Riley Peter's Intro to ASIC Formal Verification Presentation (PDF) <../_static/pdf/meeting-slides/intro-to-formal.pdf>`_
+
+.. raw:: html
+
+   <iframe src="../_static/pdf/meeting-slides/intro-to-formal.pdf" width="100%" height="600px" style="border:none;"></iframe>
diff --git a/source/docs/presentations/index.rst b/source/docs/presentations/index.rst
@@ -21,3 +21,4 @@ Presenter Slides
   ../intro-to-asic
   ../intro-fifo
   ../bist
+  ../intro-to-formal
diff --git a/source/index.rst b/source/index.rst
@@ -169,7 +169,7 @@ Meetings
 :doc:`meetings/verilog-meetup`
 
 
-.. important:: The 14th meeting will be 11/19/2025 @ 6:00 PM in Bldg. 20, Room 100
+.. important:: The 14th meeting will be 1/31/2026 @ 12:00 PM in Bldg. 20, Room 100
 
 .. raw:: html
 

-Original file line number
+Diff line change
 .pypirc
 /_site/
++
 +/just/