added new stuff to site

Author: ryancramuh

source/meetings/meeting-67.rst

@@ -6,34 +6,34 @@ CARP Meeting 6 and 7
 
 .. note::
 
-   These meetings marks the transition from **design to verification and integration**.  
+   These meetings marks the transition from **design to verification and integration**.
    With the multiplier and divider complete, the focus shifts to **test coverage**, **pipeline verification**, and **layout validation** for physical design readiness.
 
 Where Are We At?
 ----------------
 
-- **Core:** CARP baseline operational; branch hazards pending integration.  
-- **Multiplier:** Fully functional and verified at the unit level.  
-- **Divider:** Completed and passing initial directed tests.  
+- **Core:** CARP baseline operational; branch hazards pending integration.
+- **Multiplier:** Fully functional and verified at the unit level.
+- **Divider:** Completed and passing initial directed tests.
 - **Next Milestone:** Verify and integrate **RV32M extension** within the pipelined core.
 
 Immediate Priorities
 --------------------
 
 1. **Verification Continuation**
-   - Extend regression suite to include both multiplier and divider.  
-   - Begin **core-level integration testing** (M-extension through writeback).  
-   - Document verification coverage metrics and corner-case behaviors.  
+   - Extend regression suite to include both multiplier and divider.
+   - Begin **core-level integration testing** (M-extension through writeback).
+   - Document verification coverage metrics and corner-case behaviors.
    - Validate hazard/stall/flush control under M-extension operations.
 
 2. **Layout Progression**
-   - Continue SKY130 design rule familiarization and layout environment setup.  
-   - Review cell libraries, DRC/LVS conventions, and macro integration strategies.  
+   - Continue SKY130 design rule familiarization and layout environment setup.
+   - Review cell libraries, DRC/LVS conventions, and macro integration strategies.
    - Start placing initial **floorplan prototypes** with realistic module sizing.
 
 3. **Documentation & Coordination**
-   - Consolidate multiplier/divider design documentation.  
-   - Update CARP Docs with verification flow instructions (Verilator/Icarus/Cocotb).  
+   - Consolidate multiplier/divider design documentation.
+   - Update CARP Docs with verification flow instructions (Verilator/Icarus/Cocotb).
    - Record latency tables, signed/unsigned behavior, and testbench summaries.
 
 Frontend Team (RTL Design)
@@ -43,14 +43,14 @@ Frontend Team (RTL Design)
 
 - **Responsibilities**
 
-  * Maintain stable RTL for multiplier and divider modules.  
-  * Support verification with annotated waveforms and timing notes.  
-  * Assist in pipeline-level integration (forwarding, stall logic).  
+  * Maintain stable RTL for multiplier and divider modules.
+  * Support verification with annotated waveforms and timing notes.
+  * Assist in pipeline-level integration (forwarding, stall logic).
 
 - **Active Tasks (by today)**
 
-  * Finalize integration of M-extension into `DE` and `EM` stages.  
-  * Validate stall propagation with new `hazard_unit`.  
+  * Finalize integration of M-extension into `DE` and `EM` stages.
+  * Validate stall propagation with new `hazard_unit`.
   * Prepare short technical brief for divider latency and throughput.
 
 Backend Team (Verification)
@@ -60,14 +60,14 @@ Backend Team (Verification)
 
 - **Responsibilities**
 
-  * Perform end-to-end verification for multiplier/divider.  
-  * Expand testbench coverage to random and edge-case operands.  
-  * Begin regression for combined pipeline execution (M-extension ops).  
+  * Perform end-to-end verification for multiplier/divider.
+  * Expand testbench coverage to random and edge-case operands.
+  * Begin regression for combined pipeline execution (M-extension ops).
 
 - **Active Tasks (by today)**
 
-  * Run full regression on multiplier/divider units.  
-  * Integrate both into core simulation and compare against Spike reference.  
+  * Run full regression on multiplier/divider units.
+  * Integrate both into core simulation and compare against Spike reference.
   * Draft preliminary **coverage summary** and test methodology document.
 
 Layout Team (Physical / Floorplan)
@@ -77,26 +77,26 @@ Layout Team (Physical / Floorplan)
 
 - **Responsibilities**
 
-  * Advance SKY130 layout literacy: DRC/LVS, parasitics, and standard-cell usage.  
-  * Prepare layout sandbox for integration of arithmetic units.  
+  * Advance SKY130 layout literacy: DRC/LVS, parasitics, and standard-cell usage.
+  * Prepare layout sandbox for integration of arithmetic units.
   * Identify memory macro boundaries and prepare DEF/LEF templates.
 
 - **Active Tasks (by today)**
 
-  * Review SKY130 documentation for SRAM/ROM macro compatibility.  
-  * Produce report on multiplier/divider area estimates.  
+  * Review SKY130 documentation for SRAM/ROM macro compatibility.
+  * Produce report on multiplier/divider area estimates.
   * Begin schematic/layout correlation for critical datapath cells.
 
 Next Steps
 ----------
 
 - **By end of today:**
-  * All teams: submit M-extension verification updates.  
-  * Frontend: integration of divider into the main datapath.  
-  * Backend: preliminary regression report uploaded to repo.  
+  * All teams: submit M-extension verification updates.
+  * Frontend: integration of divider into the main datapath.
+  * Backend: preliminary regression report uploaded to repo.
   * Layout: internal notes on macro placement and process layers.
 
 - **By next week:**
-  * Full M-extension verification suite passing.  
-  * Core pipeline validated with stalls, flushes, and forwarding.  
+  * Full M-extension verification suite passing.
+  * Core pipeline validated with stalls, flushes, and forwarding.
   * Layout team to present first complete **floorplan snapshot** (with M-unit blocks).

source/meetings/meeting-8.rst

@@ -6,14 +6,14 @@ CARP Meeting 8
 
 .. note::
 
-   These sessions mark our transition from **arithmetic verification** into **control flow and prediction**.  
+   These sessions mark our transition from **arithmetic verification** into **control flow and prediction**.
    With the multiplier and divider modules stabilized, we’re now expanding toward **branch hazards**, **control transfer**, and **prediction logic**—but with a lighter cadence during midterms.
 
 Current Focus
 --------------
 
-- **Core:** Pipelined baseline operational; branch logic pending refinement.  
-- **Multiplier / Divider:** Verified at the unit level and integrated through the M-extension.  
+- **Core:** Pipelined baseline operational; branch logic pending refinement.
+- **Multiplier / Divider:** Verified at the unit level and integrated through the M-extension.
 - **Next Phase:** Control transfer validation (JAL, JALR, BRANCH) and branch prediction design.
 
 Control Transfer Overview
@@ -23,21 +23,21 @@ Control Transfer Overview
 
 Branches and jumps bring *decision-making* to the CPU—without them, the processor is just a deterministic calculator.
 
-- **Branches** 
+- **Branches**
 
-  - Enable `if/else`, `for`, `while`, and `do-while` constructs.  
+  - Enable `if/else`, `for`, `while`, and `do-while` constructs.
   - Use the **B-type** immediate format with RS1/RS2 comparison.
 
-- **Jumps** 
+- **Jumps**
 
-  - Enable *function calls* and *returns*.  
-  - `JAL` uses **PC + J-type** immediate.  
+  - Enable *function calls* and *returns*.
+  - `JAL` uses **PC + J-type** immediate.
   - `JALR` uses **PC + (RS1 + I-type)** and requires forwarding RS1 if not yet written back.
 
 **Control Transfer Opcodes**
 
-- ``JAL``  Jump and Link  
-- ``JALR``  Jump and Link Register  
+- ``JAL``  Jump and Link
+- ``JALR``  Jump and Link Register
 - ``BRANCH``  Conditional control transfer (BEQ, BNE, etc.)
 
 Hazards and Forwarding
@@ -46,12 +46,12 @@ Hazards and Forwarding
 When branching or jumping, hazards may arise from unresolved or in-flight instructions:
 
 - **JAL / JALR**
-  - Unresolved branch or jump ahead.  
-  - RS1 dependency in multiply/divide.  
+  - Unresolved branch or jump ahead.
+  - RS1 dependency in multiply/divide.
   - Divider or load-use stalls.
 
 - **Branch**
-  - RS1 and RS2 may need forwarding.  
+  - RS1 and RS2 may need forwarding.
   - Pending jump/branch in pipeline.
 
 Ensure the **hazard unit** handles:
@@ -64,49 +64,49 @@ Branch Prediction
 We’re officially entering **branch prediction**—the earliest form of machine learning!
 
 **Why Prediction?**
-- Improves instruction throughput by guessing branch outcomes before resolution.  
+- Improves instruction throughput by guessing branch outcomes before resolution.
 - Reduces pipeline stalls due to control hazards.
 
 **Branch Prediction Logic**
-- Predictor can mark branches as *strongly taken*, *weakly taken*, or *not taken*.  
+- Predictor can mark branches as *strongly taken*, *weakly taken*, or *not taken*.
 - Fetch and decode stages can speculatively forward instructions based on prediction state.
 
 **FETCH Stage (with Prediction)**
-- Forward RS1/RS2 if available.  
+- Forward RS1/RS2 if available.
 - If predictor says **strongly taken**, preemptively adjust PC.
 
 **DECODE Stage (with Prediction)**
-- Continue to forward RS1/RS2 as needed.  
+- Continue to forward RS1/RS2 as needed.
 - Use branch prediction result to decide speculative execution path.
 
 Verification Priorities
 -----------------------
 
 1. **Branch and Jump Integration**
-   - Validate JAL/JALR instruction sequencing.  
+   - Validate JAL/JALR instruction sequencing.
    - Confirm correct return address storage and PC computation.
 
 2. **Hazard and Stall Handling**
-   - Test control stalls alongside load-use and M-extension interactions.  
+   - Test control stalls alongside load-use and M-extension interactions.
    - Ensure pipeline flushes on mispredicted branches.
 
 3. **Prediction Validation**
-   - Implement basic static predictor (always taken / backward taken).  
+   - Implement basic static predictor (always taken / backward taken).
    - Begin simulation runs with branch-heavy benchmarks.
 
 Next Steps
 -----------
 
 **By next week (lighter schedule):**
-- RTL: Integrate basic branch functionality into EEL.  
+- RTL: Integrate basic branch functionality into EEL.
 - Verification: Add control-transfer test cases
 
 **After midterms:**
-- Expand predictor sophistication (2-bit saturating counter).  
+- Expand predictor sophistication (2-bit saturating counter).
 - Begin full end-to-end pipeline regression with hazards, M-extension, and branch logic active.
 
 ---
 
-*Relaxed focus for midterms:*  
-The next two weeks are for stabilization, documentation, and conceptual understanding.  
+*Relaxed focus for midterms:*
+The next two weeks are for stabilization, documentation, and conceptual understanding.
 No major synthesis or layout pushes until post-midterm.

source/meetings/roberts-comp-arch-presentation.md

@@ -1,6 +1,5 @@
 # Intro to Computer Architecture Slides
 
-
 View the [Robert's Intro to Computer Architecture Presentation (PDF)](../_static/pdf/meeting-slides/intro-to-comp-arch.pdf)
 
 ```{raw} html