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source/docs/intro-to-asic.rst

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.. raw:: html
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<iframe src="../_static/pdf/verilog-meetups-stuff/10_25%20Pres.pdf" width="100%" height="600px" style="border:none;"></iframe>
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source/docs/intro-to-formal.rst

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Intro to ASIC Formal Verification Slides
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=====================================
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View the `Riley Peter's Intro to ASIC Formal Verification Presentation (PDF) <../_static/pdf/meeting-slides/intro-to-formal.pdf>`_
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.. raw:: html
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<iframe src="../_static/pdf/meeting-slides/intro-to-formal.pdf" width="100%" height="600px" style="border:none;"></iframe>

source/docs/presentations/index.rst

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:doc:`../bist`
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:doc:`../intro-to-formal`
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.. toctree::
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../intro-to-asic
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../intro-fifo
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../bist
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../intro-to-formal

source/docs/video-guides/video-guides.rst

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`Layout Team - Flow Demo <https://www.youtube.com/watch?v=x48YaTp-b7Q>`_
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`Verilog Meetup Event Videos - <https://www.youtube.com/watch?v=PZAxtHzPFCM&list=PLeuUczGoUbdrEi9uJ-WoV_ze26XoNv759>`_
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`Verilog Meetup Event Videos <https://www.youtube.com/watch?v=PZAxtHzPFCM&list=PLeuUczGoUbdrEi9uJ-WoV_ze26XoNv759>`_
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`CARP Guest Talk - ASIC Design and TinyTapeout with Matt Venn <https://www.youtube.com/watch?v=koR7RC7Wuik>`_
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`Intro to ASIC Formal Verification - Riley Peters <https://www.youtube.com/watch?v=Bvp3MHgNWHY>`_

source/index.rst

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docs/asic-class/asic-class
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docs/timing-guides/index
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docs/FreeRTOS/index
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docs/risc-v/index
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.. docs/memory/index
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