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[GD32F103] Omit DISABLE_REMAP macro for those pins that dont need it
1 parent 9f1c9f1 commit c6c5e46

130 files changed

Lines changed: 2437 additions & 2563 deletions

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‎variants/GD32F103C4_GENERIC/PeripheralPins.c‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -125,55 +125,55 @@ const PinMap PinMap_DAC[] = {
125125

126126
/* I2C_SDA PinMap */
127127
const PinMap PinMap_I2C_SDA[] = {
128-
{PORTB_7, I2C0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_I2C0_REMAP)}, /* I2C0_SDA */
128+
{PORTB_7, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SDA */
129129
{PORTB_9, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SDA */
130130
{NC, NC, 0}
131131
};
132132

133133
/* I2C_SCL PinMap */
134134
const PinMap PinMap_I2C_SCL[] = {
135-
{PORTB_6, I2C0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_I2C0_REMAP)}, /* I2C0_SCL */
135+
{PORTB_6, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SCL */
136136
{PORTB_8, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SCL */
137137
{NC, NC, 0}
138138
};
139139

140140
/* PWM PinMap */
141141
const PinMap PinMap_PWM[] = {
142-
{PORTA_0, TIMER1, GD_PIN_FUNC_PWM(0, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH0 */
142+
{PORTA_0, TIMER1, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER1_CH0 */
143143
{PORTA_0_ALT1, TIMER1, GD_PIN_FUNC_PWM(0, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH0 */
144144
{PORTA_0_ALT2, TIMER4, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER4_CH0 */
145-
{PORTA_1, TIMER1, GD_PIN_FUNC_PWM(1, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH1 */
145+
{PORTA_1, TIMER1, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER1_CH1 */
146146
{PORTA_1_ALT1, TIMER1, GD_PIN_FUNC_PWM(1, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH1 */
147-
{PORTA_2, TIMER1, GD_PIN_FUNC_PWM(2, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH2 */
147+
{PORTA_2, TIMER1, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER1_CH2 */
148148
{PORTA_2_ALT1, TIMER1, GD_PIN_FUNC_PWM(2, TIMER1_PARTIAL_REMAP0)}, /* TIMER1_CH2 */
149-
{PORTA_3, TIMER1, GD_PIN_FUNC_PWM(3, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH3 */
149+
{PORTA_3, TIMER1, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER1_CH3 */
150150
{PORTA_3_ALT1, TIMER1, GD_PIN_FUNC_PWM(3, TIMER1_PARTIAL_REMAP0)}, /* TIMER1_CH3 */
151-
{PORTA_6, TIMER2, GD_PIN_FUNC_PWM(0, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH0 */
151+
{PORTA_6, TIMER2, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER2_CH0 */
152152
{PORTA_7, TIMER0, GD_PIN_FUNC_PWM(0, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH0_ON */
153-
{PORTA_7_ALT1, TIMER2, GD_PIN_FUNC_PWM(1, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH1 */
154-
{PORTA_8, TIMER0, GD_PIN_FUNC_PWM(0, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH0 */
153+
{PORTA_7_ALT1, TIMER2, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER2_CH1 */
154+
{PORTA_8, TIMER0, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER0_CH0 */
155155
{PORTA_8_ALT1, TIMER0, GD_PIN_FUNC_PWM(0, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH0 */
156-
{PORTA_9, TIMER0, GD_PIN_FUNC_PWM(1, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH1 */
156+
{PORTA_9, TIMER0, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER0_CH1 */
157157
{PORTA_9_ALT1, TIMER0, GD_PIN_FUNC_PWM(1, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH1 */
158-
{PORTA_10, TIMER0, GD_PIN_FUNC_PWM(2, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH2 */
158+
{PORTA_10, TIMER0, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER0_CH2 */
159159
{PORTA_10_ALT1, TIMER0, GD_PIN_FUNC_PWM(2, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH2 */
160-
{PORTA_11, TIMER0, GD_PIN_FUNC_PWM(3, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH3 */
160+
{PORTA_11, TIMER0, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER0_CH3 */
161161
{PORTA_11_ALT1, TIMER0, GD_PIN_FUNC_PWM(3, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH3 */
162162
{PORTA_15, TIMER1, GD_PIN_FUNC_PWM(0, TIMER1_PARTIAL_REMAP0)}, /* TIMER1_CH0 */
163163
{PORTA_15_ALT1, TIMER1, GD_PIN_FUNC_PWM(0, TIMER1_FULL_REMAP)}, /* TIMER1_CH0 */
164164
{PORTB_0, TIMER0, GD_PIN_FUNC_PWM(1, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH1_ON */
165-
{PORTB_0_ALT1, TIMER2, GD_PIN_FUNC_PWM(2, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH2 */
165+
{PORTB_0_ALT1, TIMER2, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER2_CH2 */
166166
{PORTB_0_ALT2, TIMER2, GD_PIN_FUNC_PWM(2, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH2 */
167167
{PORTB_1, TIMER0, GD_PIN_FUNC_PWM(2, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH2_ON */
168-
{PORTB_1_ALT1, TIMER2, GD_PIN_FUNC_PWM(3, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH3 */
168+
{PORTB_1_ALT1, TIMER2, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER2_CH3 */
169169
{PORTB_1_ALT2, TIMER2, GD_PIN_FUNC_PWM(3, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH3 */
170170
{PORTB_4, TIMER2, GD_PIN_FUNC_PWM(0, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH0 */
171171
{PORTB_5, TIMER2, GD_PIN_FUNC_PWM(1, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH1 */
172172
{PORTB_10, TIMER1, GD_PIN_FUNC_PWM(2, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH2 */
173173
{PORTB_10_ALT1, TIMER1, GD_PIN_FUNC_PWM(2, TIMER1_FULL_REMAP)}, /* TIMER1_CH2 */
174174
{PORTB_11, TIMER1, GD_PIN_FUNC_PWM(3, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH3 */
175175
{PORTB_11_ALT1, TIMER1, GD_PIN_FUNC_PWM(3, TIMER1_FULL_REMAP)}, /* TIMER1_CH3 */
176-
{PORTB_13, TIMER0, GD_PIN_FUNC_PWM(0, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH0_ON */
176+
{PORTB_13, TIMER0, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER0_CH0_ON */
177177
{PORTB_14, TIMER0, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER0_CH1_ON */
178178
{PORTB_15, TIMER0, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER0_CH2_ON */
179179
{NC, NC, 0}
@@ -182,15 +182,15 @@ const PinMap PinMap_PWM[] = {
182182
/* UART_TX PinMap */
183183
const PinMap PinMap_UART_TX[] = {
184184
{PORTA_2, USART1, PIN_MODE_AF_PP}, /* USART1_TX */
185-
{PORTA_9, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_USART0_REMAP)}, /* USART0_TX */
185+
{PORTA_9, USART0, PIN_MODE_AF_PP}, /* USART0_TX */
186186
{PORTB_6, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, USART0_REMAP)}, /* USART0_TX */
187187
{NC, NC, 0}
188188
};
189189

190190
/* UART_RX PinMap */
191191
const PinMap PinMap_UART_RX[] = {
192192
{PORTA_3, USART1, GPIO_MODE_IN_FLOATING}, /* USART1_RX */
193-
{PORTA_10, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_USART0_REMAP)}, /* USART0_RX */
193+
{PORTA_10, USART0, GPIO_MODE_IN_FLOATING}, /* USART0_RX */
194194
{PORTB_7, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, USART0_REMAP)}, /* USART0_RX */
195195
{NC, NC, 0}
196196
};
@@ -211,27 +211,27 @@ const PinMap PinMap_UART_CTS[] = {
211211

212212
/* SPI_MOSI PinMap */
213213
const PinMap PinMap_SPI_MOSI[] = {
214-
{PORTA_7, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_MOSI */
214+
{PORTA_7, SPI0, GPIO_MODE_AF_PP}, /* SPI0_MOSI */
215215
{PORTB_5, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, SPI0_REMAP)}, /* SPI0_MOSI */
216216
{NC, NC, 0}
217217
};
218218

219219
/* SPI_MISO PinMap */
220220
const PinMap PinMap_SPI_MISO[] = {
221-
{PORTA_6, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_MISO */
221+
{PORTA_6, SPI0, GPIO_MODE_AF_PP}, /* SPI0_MISO */
222222
{PORTB_4, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, SPI0_REMAP)}, /* SPI0_MISO */
223223
{NC, NC, 0}
224224
};
225225

226226
/* SPI_SCLK PinMap */
227227
const PinMap PinMap_SPI_SCLK[] = {
228-
{PORTA_5, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_SCK */
228+
{PORTA_5, SPI0, GPIO_MODE_AF_PP}, /* SPI0_SCK */
229229
{NC, NC, 0}
230230
};
231231

232232
/* SPI_SSEL PinMap */
233233
const PinMap PinMap_SPI_SSEL[] = {
234-
{PORTA_4, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_NSS */
234+
{PORTA_4, SPI0, GPIO_MODE_AF_PP}, /* SPI0_NSS */
235235
{PORTA_15, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, SPI0_REMAP)}, /* SPI0_NSS */
236236
{NC, NC, 0}
237237
};

‎variants/GD32F103C4_GENERIC/variant.cpp‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -57,30 +57,30 @@ const PinName digital_pins[] = {
5757
PORTB_7,
5858
PORTB_8,
5959
PORTB_9,
60-
PORTA_4,
61-
PORTA_6,
62-
PORTB_1,
6360
PORTA_2,
64-
PORTA_7,
65-
PORTB_0,
66-
PORTA_0,
6761
PORTA_1,
62+
PORTA_5,
63+
PORTB_1,
6864
PORTA_3,
69-
PORTA_5
65+
PORTA_6,
66+
PORTB_0,
67+
PORTA_7,
68+
PORTA_4,
69+
PORTA_0
7070
};
7171

7272
/* analog pins for pinmap list */
7373
const uint32_t analog_pins[] = {
74-
PA4, //A0
75-
PA6, //A1
76-
PB1, //A2
77-
PA2, //A3
78-
PA7, //A4
79-
PB0, //A5
80-
PA0, //A6
81-
PA1, //A7
82-
PA3, //A8
83-
PA5 //A9
74+
PA2, //A0
75+
PA1, //A1
76+
PA5, //A2
77+
PB1, //A3
78+
PA3, //A4
79+
PA6, //A5
80+
PB0, //A6
81+
PA7, //A7
82+
PA4, //A8
83+
PA0 //A9
8484
};
8585

8686
#ifdef __cplusplus

‎variants/GD32F103C4_GENERIC/variant.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -58,22 +58,22 @@ extern "C" {
5858
#define PB8 22
5959
#define PB9 23
6060
/* analog pins */
61-
#define PA4 24
62-
#define PA6 25
63-
#define PB1 26
64-
#define PA2 27
65-
#define PA7 28
66-
#define PB0 29
67-
#define PA0 30
68-
#define PA1 31
69-
#define PA3 32
70-
#define PA5 33
61+
#define PA2 24
62+
#define PA1 25
63+
#define PA5 26
64+
#define PB1 27
65+
#define PA3 28
66+
#define PA6 29
67+
#define PB0 30
68+
#define PA7 31
69+
#define PA4 32
70+
#define PA0 33
7171

7272
/* digital pins and analog pins number definitions */
7373
#define DIGITAL_PINS_NUM 34
7474
#define ANALOG_PINS_NUM 10
75-
#define ANALOG_PINS_START PA4
76-
#define ANALOG_PINS_LAST PA5
75+
#define ANALOG_PINS_START PA2
76+
#define ANALOG_PINS_LAST PA0
7777

7878
/* alternative pin remappings */
7979
#define PA0_ALT1 (PA0 | ALT1)

‎variants/GD32F103C6_GENERIC/PeripheralPins.c‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -125,55 +125,55 @@ const PinMap PinMap_DAC[] = {
125125

126126
/* I2C_SDA PinMap */
127127
const PinMap PinMap_I2C_SDA[] = {
128-
{PORTB_7, I2C0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_I2C0_REMAP)}, /* I2C0_SDA */
128+
{PORTB_7, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SDA */
129129
{PORTB_9, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SDA */
130130
{NC, NC, 0}
131131
};
132132

133133
/* I2C_SCL PinMap */
134134
const PinMap PinMap_I2C_SCL[] = {
135-
{PORTB_6, I2C0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_I2C0_REMAP)}, /* I2C0_SCL */
135+
{PORTB_6, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SCL */
136136
{PORTB_8, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SCL */
137137
{NC, NC, 0}
138138
};
139139

140140
/* PWM PinMap */
141141
const PinMap PinMap_PWM[] = {
142-
{PORTA_0, TIMER1, GD_PIN_FUNC_PWM(0, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH0 */
142+
{PORTA_0, TIMER1, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER1_CH0 */
143143
{PORTA_0_ALT1, TIMER1, GD_PIN_FUNC_PWM(0, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH0 */
144144
{PORTA_0_ALT2, TIMER4, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER4_CH0 */
145-
{PORTA_1, TIMER1, GD_PIN_FUNC_PWM(1, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH1 */
145+
{PORTA_1, TIMER1, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER1_CH1 */
146146
{PORTA_1_ALT1, TIMER1, GD_PIN_FUNC_PWM(1, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH1 */
147-
{PORTA_2, TIMER1, GD_PIN_FUNC_PWM(2, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH2 */
147+
{PORTA_2, TIMER1, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER1_CH2 */
148148
{PORTA_2_ALT1, TIMER1, GD_PIN_FUNC_PWM(2, TIMER1_PARTIAL_REMAP0)}, /* TIMER1_CH2 */
149-
{PORTA_3, TIMER1, GD_PIN_FUNC_PWM(3, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH3 */
149+
{PORTA_3, TIMER1, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER1_CH3 */
150150
{PORTA_3_ALT1, TIMER1, GD_PIN_FUNC_PWM(3, TIMER1_PARTIAL_REMAP0)}, /* TIMER1_CH3 */
151-
{PORTA_6, TIMER2, GD_PIN_FUNC_PWM(0, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH0 */
151+
{PORTA_6, TIMER2, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER2_CH0 */
152152
{PORTA_7, TIMER0, GD_PIN_FUNC_PWM(0, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH0_ON */
153-
{PORTA_7_ALT1, TIMER2, GD_PIN_FUNC_PWM(1, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH1 */
154-
{PORTA_8, TIMER0, GD_PIN_FUNC_PWM(0, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH0 */
153+
{PORTA_7_ALT1, TIMER2, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER2_CH1 */
154+
{PORTA_8, TIMER0, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER0_CH0 */
155155
{PORTA_8_ALT1, TIMER0, GD_PIN_FUNC_PWM(0, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH0 */
156-
{PORTA_9, TIMER0, GD_PIN_FUNC_PWM(1, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH1 */
156+
{PORTA_9, TIMER0, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER0_CH1 */
157157
{PORTA_9_ALT1, TIMER0, GD_PIN_FUNC_PWM(1, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH1 */
158-
{PORTA_10, TIMER0, GD_PIN_FUNC_PWM(2, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH2 */
158+
{PORTA_10, TIMER0, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER0_CH2 */
159159
{PORTA_10_ALT1, TIMER0, GD_PIN_FUNC_PWM(2, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH2 */
160-
{PORTA_11, TIMER0, GD_PIN_FUNC_PWM(3, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH3 */
160+
{PORTA_11, TIMER0, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER0_CH3 */
161161
{PORTA_11_ALT1, TIMER0, GD_PIN_FUNC_PWM(3, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH3 */
162162
{PORTA_15, TIMER1, GD_PIN_FUNC_PWM(0, TIMER1_PARTIAL_REMAP0)}, /* TIMER1_CH0 */
163163
{PORTA_15_ALT1, TIMER1, GD_PIN_FUNC_PWM(0, TIMER1_FULL_REMAP)}, /* TIMER1_CH0 */
164164
{PORTB_0, TIMER0, GD_PIN_FUNC_PWM(1, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH1_ON */
165-
{PORTB_0_ALT1, TIMER2, GD_PIN_FUNC_PWM(2, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH2 */
165+
{PORTB_0_ALT1, TIMER2, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER2_CH2 */
166166
{PORTB_0_ALT2, TIMER2, GD_PIN_FUNC_PWM(2, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH2 */
167167
{PORTB_1, TIMER0, GD_PIN_FUNC_PWM(2, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH2_ON */
168-
{PORTB_1_ALT1, TIMER2, GD_PIN_FUNC_PWM(3, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH3 */
168+
{PORTB_1_ALT1, TIMER2, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER2_CH3 */
169169
{PORTB_1_ALT2, TIMER2, GD_PIN_FUNC_PWM(3, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH3 */
170170
{PORTB_4, TIMER2, GD_PIN_FUNC_PWM(0, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH0 */
171171
{PORTB_5, TIMER2, GD_PIN_FUNC_PWM(1, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH1 */
172172
{PORTB_10, TIMER1, GD_PIN_FUNC_PWM(2, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH2 */
173173
{PORTB_10_ALT1, TIMER1, GD_PIN_FUNC_PWM(2, TIMER1_FULL_REMAP)}, /* TIMER1_CH2 */
174174
{PORTB_11, TIMER1, GD_PIN_FUNC_PWM(3, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH3 */
175175
{PORTB_11_ALT1, TIMER1, GD_PIN_FUNC_PWM(3, TIMER1_FULL_REMAP)}, /* TIMER1_CH3 */
176-
{PORTB_13, TIMER0, GD_PIN_FUNC_PWM(0, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH0_ON */
176+
{PORTB_13, TIMER0, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER0_CH0_ON */
177177
{PORTB_14, TIMER0, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER0_CH1_ON */
178178
{PORTB_15, TIMER0, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER0_CH2_ON */
179179
{NC, NC, 0}
@@ -182,15 +182,15 @@ const PinMap PinMap_PWM[] = {
182182
/* UART_TX PinMap */
183183
const PinMap PinMap_UART_TX[] = {
184184
{PORTA_2, USART1, PIN_MODE_AF_PP}, /* USART1_TX */
185-
{PORTA_9, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_USART0_REMAP)}, /* USART0_TX */
185+
{PORTA_9, USART0, PIN_MODE_AF_PP}, /* USART0_TX */
186186
{PORTB_6, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, USART0_REMAP)}, /* USART0_TX */
187187
{NC, NC, 0}
188188
};
189189

190190
/* UART_RX PinMap */
191191
const PinMap PinMap_UART_RX[] = {
192192
{PORTA_3, USART1, GPIO_MODE_IN_FLOATING}, /* USART1_RX */
193-
{PORTA_10, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_USART0_REMAP)}, /* USART0_RX */
193+
{PORTA_10, USART0, GPIO_MODE_IN_FLOATING}, /* USART0_RX */
194194
{PORTB_7, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, USART0_REMAP)}, /* USART0_RX */
195195
{NC, NC, 0}
196196
};
@@ -211,27 +211,27 @@ const PinMap PinMap_UART_CTS[] = {
211211

212212
/* SPI_MOSI PinMap */
213213
const PinMap PinMap_SPI_MOSI[] = {
214-
{PORTA_7, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_MOSI */
214+
{PORTA_7, SPI0, GPIO_MODE_AF_PP}, /* SPI0_MOSI */
215215
{PORTB_5, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, SPI0_REMAP)}, /* SPI0_MOSI */
216216
{NC, NC, 0}
217217
};
218218

219219
/* SPI_MISO PinMap */
220220
const PinMap PinMap_SPI_MISO[] = {
221-
{PORTA_6, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_MISO */
221+
{PORTA_6, SPI0, GPIO_MODE_AF_PP}, /* SPI0_MISO */
222222
{PORTB_4, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, SPI0_REMAP)}, /* SPI0_MISO */
223223
{NC, NC, 0}
224224
};
225225

226226
/* SPI_SCLK PinMap */
227227
const PinMap PinMap_SPI_SCLK[] = {
228-
{PORTA_5, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_SCK */
228+
{PORTA_5, SPI0, GPIO_MODE_AF_PP}, /* SPI0_SCK */
229229
{NC, NC, 0}
230230
};
231231

232232
/* SPI_SSEL PinMap */
233233
const PinMap PinMap_SPI_SSEL[] = {
234-
{PORTA_4, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_NSS */
234+
{PORTA_4, SPI0, GPIO_MODE_AF_PP}, /* SPI0_NSS */
235235
{PORTA_15, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, SPI0_REMAP)}, /* SPI0_NSS */
236236
{NC, NC, 0}
237237
};

‎variants/GD32F103C6_GENERIC/variant.cpp‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -57,30 +57,30 @@ const PinName digital_pins[] = {
5757
PORTB_7,
5858
PORTB_8,
5959
PORTB_9,
60-
PORTA_4,
61-
PORTA_6,
62-
PORTB_1,
6360
PORTA_2,
64-
PORTA_7,
65-
PORTB_0,
66-
PORTA_0,
6761
PORTA_1,
62+
PORTA_5,
63+
PORTB_1,
6864
PORTA_3,
69-
PORTA_5
65+
PORTA_6,
66+
PORTB_0,
67+
PORTA_7,
68+
PORTA_4,
69+
PORTA_0
7070
};
7171

7272
/* analog pins for pinmap list */
7373
const uint32_t analog_pins[] = {
74-
PA4, //A0
75-
PA6, //A1
76-
PB1, //A2
77-
PA2, //A3
78-
PA7, //A4
79-
PB0, //A5
80-
PA0, //A6
81-
PA1, //A7
82-
PA3, //A8
83-
PA5 //A9
74+
PA2, //A0
75+
PA1, //A1
76+
PA5, //A2
77+
PB1, //A3
78+
PA3, //A4
79+
PA6, //A5
80+
PB0, //A6
81+
PA7, //A7
82+
PA4, //A8
83+
PA0 //A9
8484
};
8585

8686
#ifdef __cplusplus

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