From b80c1f6227c564d46df9012fcce983a52d6acd9a Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Mon, 13 Apr 2026 16:19:13 +0000 Subject: [PATCH 1/3] Update scalafmt-core to 3.11.0 --- .scalafmt.conf | 2 +- docs/getting-started/hello-world/scala-project/.scalafmt.conf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.scalafmt.conf b/.scalafmt.conf index 88fe92390..21b34a20d 100755 --- a/.scalafmt.conf +++ b/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 3.10.7 +version = 3.11.0 runner.dialect = scala3 maxColumn = 100 diff --git a/docs/getting-started/hello-world/scala-project/.scalafmt.conf b/docs/getting-started/hello-world/scala-project/.scalafmt.conf index 75af615b0..99eb5862b 100644 --- a/docs/getting-started/hello-world/scala-project/.scalafmt.conf +++ b/docs/getting-started/hello-world/scala-project/.scalafmt.conf @@ -1,4 +1,4 @@ -version = 3.10.7 +version = 3.11.0 runner.dialect = scala3 maxColumn = 100 From b96c4d23ce2ab8c80bd5d83129a90fe93ebe2a3f Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Mon, 13 Apr 2026 16:19:38 +0000 Subject: [PATCH 2/3] Reformat with scalafmt 3.11.0 Executed command: scalafmt --non-interactive --- .../compiler/analysis/DomainAnalysis.scala | 21 ++-- .../src/main/scala/dfhdl/compiler/ir/DB.scala | 13 +- .../main/scala/dfhdl/compiler/ir/DFType.scala | 5 +- .../compiler/printing/DFDataPrinter.scala | 20 +-- .../dfhdl/compiler/stages/AddClkRst.scala | 3 +- .../compiler/stages/DropStructsVecs.scala | 15 ++- .../stages/GlobalizePortVectorParams.scala | 6 +- .../stages/vhdl/VHDLDataPrinter.scala | 13 +- .../compiler/stages/vhdl/VHDLValPrinter.scala | 9 +- .../StagesSpec/ExplicitNamedVarsSpec.scala | 2 +- .../StagesSpec/PrintCodeStringSpec.scala | 3 +- .../src/main/scala/dfhdl/core/DFDecimal.scala | 36 ++++-- core/src/main/scala/dfhdl/core/DFEnum.scala | 6 +- core/src/main/scala/dfhdl/core/DFVal.scala | 12 +- .../test/scala/CoreSpec/DFDecimalSpec.scala | 116 +++++++++--------- .../src/test/scala/CoreSpec/DFMatchSpec.scala | 6 +- .../main/scala/dfhdl/internals/Checked.scala | 4 +- .../main/scala/dfhdl/internals/Exact.scala | 23 +++- lib/src/test/scala/AES/defs.scala | 3 +- .../scala/plugin/FlattenInlinedPhase.scala | 4 +- project/DFHDLCommands.scala | 2 +- 21 files changed, 180 insertions(+), 142 deletions(-) diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DomainAnalysis.scala b/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DomainAnalysis.scala index 15c7e3fa4..769564325 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DomainAnalysis.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/analysis/DomainAnalysis.scala @@ -21,21 +21,24 @@ final class DomainAnalysis(designDB: DB): if clkCfg != None || rstCfg != None => collectedDesignDomains.get(key) match case Some(clkRstOpt) => - (clkCfg != None && clkRstOpt.clkOpt.isEmpty) || (rstCfg != None && clkRstOpt.rstOpt.isEmpty) + (clkCfg != None && clkRstOpt.clkOpt.isEmpty) || + (rstCfg != None && clkRstOpt.rstOpt.isEmpty) case None => true case _ => setEmpty(key) // TODO: probably ugly to do this here false private def addClk(key: DFDomainOwner, clk: DFVal.Dcl): Unit = - collectedDesignDomains += key -> collectedDesignDomains - .get(key) - .map(_.addClk(clk)) - .getOrElse(ClkRstOpt(Some(clk), None)) + collectedDesignDomains += key -> + collectedDesignDomains + .get(key) + .map(_.addClk(clk)) + .getOrElse(ClkRstOpt(Some(clk), None)) private def addRst(key: DFDomainOwner, rst: DFVal.Dcl): Unit = - collectedDesignDomains += key -> collectedDesignDomains - .get(key) - .map(_.addRst(rst)) - .getOrElse(ClkRstOpt(None, Some(rst))) + collectedDesignDomains += key -> + collectedDesignDomains + .get(key) + .map(_.addRst(rst)) + .getOrElse(ClkRstOpt(None, Some(rst))) private def setEmpty(key: DFDomainOwner): Unit = collectedDesignDomains += key -> ClkRstOpt(None, None) end extension diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala index b6b57c036..d4880d2c0 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala @@ -308,14 +308,16 @@ final case class DB( } // 2. Build port copies (reusing origToDupMap from step 1) val pbnsTypes = pbnsByDesign.getOrElse(dupDesign, Map.empty) - portEntries += dupDesign -> ListMap.from(origPortMap.getOrElse(origDesign, ListMap.empty).view.map { (name, dcl) => - val dfType = pbnsTypes.getOrElse(name, dcl.dfType) - val dupOwnerDomain = origToDupMap(dcl.getOwnerDomain) - name -> dcl.copy(ownerRef = DFRef.DuplicationRef(dupOwnerDomain), dfType = dfType) - }) + portEntries += dupDesign -> + ListMap.from(origPortMap.getOrElse(origDesign, ListMap.empty).view.map { (name, dcl) => + val dfType = pbnsTypes.getOrElse(name, dcl.dfType) + val dupOwnerDomain = origToDupMap(dcl.getOwnerDomain) + name -> dcl.copy(ownerRef = DFRef.DuplicationRef(dupOwnerDomain), dfType = dfType) + }) } // dupEntries only fills in missing entries (designs without real port members) (domainBlockMap.toMap, portEntries.toMap ++ origPortMap) + end val lazy val dupDomainOwnerPublicMemberList: List[(DFDomainOwner, List[DFMember])] = def publicMemberFilter(member: DFMember): Boolean = @@ -348,6 +350,7 @@ final case class DB( (dupOwner -> dupMembers) :: origMembers.collect { case db: DomainBlock => dupEntriesFor(db, dupDesign) }.flatten + end dupEntriesFor domainOwnerMemberList.flatMap { case (owner, members) => owner match case dupDesign: DFDesignBlock if dupDesign.isDuplicate => diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala index 5eb4bdc52..db0e0410e 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/ir/DFType.scala @@ -439,8 +439,9 @@ final case class DFStruct( def getNameForced: String = name def width(using MemberGetSet): Int = fieldMap.values.map(_.width).sum def createBubbleData(using MemberGetSet): Data = fieldMap.values.map(_.createBubbleData).toList - def isDataBubble(data: Data): Boolean = - (fieldMap.values lazyZip data).exists((ft, fd) => ft.isDataBubble(fd.asInstanceOf[ft.Data])) + def isDataBubble(data: Data): Boolean = (fieldMap.values lazyZip data).exists((ft, fd) => + ft.isDataBubble(fd.asInstanceOf[ft.Data]) + ) def dataToBitsData(data: Data)(using MemberGetSet): (BitVector, BitVector) = (fieldMap.values lazyZip data) .map((ft, fd) => ft.dataToBitsData(fd.asInstanceOf[ft.Data])) diff --git a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala index 767bcbdf3..e74751047 100644 --- a/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala +++ b/compiler/ir/src/main/scala/dfhdl/compiler/printing/DFDataPrinter.scala @@ -205,16 +205,16 @@ protected trait DFDataPrinter extends AbstractDataPrinter: def csDFOpaqueData(dfType: DFOpaque, data: Any): String = s"${csConstData(dfType.actualType, data).applyBrackets()}.as(${dfType.name})" def csDFStructData(dfType: DFStruct, data: List[Any]): String = - dfType.name + dfType.fieldMap - .lazyZip(data) - .map { case ((n, t), d) => - s"$n = ${csConstData(t, d)}" - } - .mkStringBrackets - def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String = - (dfTypes lazyZip data) - .map((t, d) => csConstData(t, d)) - .mkStringBrackets + dfType.name + + dfType.fieldMap + .lazyZip(data) + .map { case ((n, t), d) => + s"$n = ${csConstData(t, d)}" + } + .mkStringBrackets + def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String = (dfTypes lazyZip data) + .map((t, d) => csConstData(t, d)) + .mkStringBrackets def csDFUnitData(dfType: DFUnit, data: Unit): String = "()" def csDFDoubleData(dfType: DFDouble, data: Option[Double]): String = data match diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/AddClkRst.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/AddClkRst.scala index 0b71f096e..1093432d4 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/AddClkRst.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/AddClkRst.scala @@ -168,8 +168,7 @@ case object AddClkRst extends Stage: val updatedDFVal = dfVal match // existing clocks also get the constraints from the domain owner case clk: DFVal.Dcl if clk.isClkDcl => - val updatedAnnotations = - (ownerClkConstraints ++ clk.meta.annotations).distinct + val updatedAnnotations = (ownerClkConstraints ++ clk.meta.annotations).distinct clk.copy( dfType = opaqueReplaceMap(dfType), meta = clk.meta.copy(annotations = updatedAnnotations) diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropStructsVecs.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropStructsVecs.scala index e062a8dd9..e22d9ee69 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropStructsVecs.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/DropStructsVecs.scala @@ -167,15 +167,17 @@ case object DropStructsVecs extends Stage: case _ => elemIdxVal.asValAny.asInstanceOf[IntParam[Int]] val elemWidth = elemSel.asValAny.widthIntParam val relValWidth = relVal.asValAny.widthIntParam - idxLow = (relValWidth - elemWidth * (elemIdx + 1)) + idxLow - .asInstanceOf[IntParam[Int]] + idxLow = (relValWidth - elemWidth * (elemIdx + 1)) + + idxLow + .asInstanceOf[IntParam[Int]] case rangeSel: DFVal.Alias.ApplyRange => val elemWidth = replacementMap(relVal).dfType.asInstanceOf[DFVector] .cellType.asFE[DFTypeAny].widthIntParam val relValWidth = relVal.asValAny.widthIntParam - idxLow = (relValWidth - elemWidth * (rangeSel.idxHighRef.get + 1)) + idxLow - .asInstanceOf[IntParam[Int]] + idxLow = (relValWidth - elemWidth * (rangeSel.idxHighRef.get + 1)) + + idxLow + .asInstanceOf[IntParam[Int]] case fieldSel: DFVal.Alias.SelectField => var relBitLow: IntParam[Int] = idxLow val dfType = replacementMap(relVal).dfType.asInstanceOf[DFStruct] @@ -205,8 +207,9 @@ case object DropStructsVecs extends Stage: case _: DFStruct => false case _ => true val bitsMeta = if (requireCast) partial.meta.anonymize else partial.meta - val idxHigh: IntParam[Int] = - (partial.asValAny.widthIntParam + idxLow - 1).asInstanceOf[IntParam[Int]] + val idxHigh: IntParam[ + Int + ] = (partial.asValAny.widthIntParam + idxLow - 1).asInstanceOf[IntParam[Int]] val bitsVal = dfhdl.core.DFVal.Alias.ApplyRange( relVal.asValOf[Bits[Int]], diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/GlobalizePortVectorParams.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/GlobalizePortVectorParams.scala index efd3faa98..1e5a2dd74 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/GlobalizePortVectorParams.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/GlobalizePortVectorParams.scala @@ -45,8 +45,9 @@ case object GlobalizePortVectorParams extends Stage: val dupMember0 = origMember.copyWithNewRefs // Tag nested design blocks as duplicates val dupMember = dupMember0 match - case dsn: DFDesignBlock => dsn.setTags(_.tag(DuplicateTag)).asInstanceOf[dupMember0.type] - case _ => dupMember0 + case dsn: DFDesignBlock => + dsn.setTags(_.tag(DuplicateTag)).asInstanceOf[dupMember0.type] + case _ => dupMember0 origToDupMemberMap += origMember -> dupMember dupRefTable += dupMember.ownerRef -> getReplacement(origMember.getOwner) origMember.getRefs.lazyZip(dupMember.getRefs).foreach { (origRef, dupRef) => @@ -62,6 +63,7 @@ case object GlobalizePortVectorParams extends Stage: duplicateDesignMembers(origNested, dupNested) case _ => } + end duplicateDesignMembers designDB.dupDesignToOrigMap.groupBy(_._2).foreach { (orig, dupMap) => dupMap.keys.foreach { dup => duplicateDesignMembers(orig, dup) } } diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLDataPrinter.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLDataPrinter.scala index a1b94176a..7e0358a69 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLDataPrinter.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLDataPrinter.scala @@ -81,12 +81,13 @@ protected trait VHDLDataPrinter extends AbstractDataPrinter: def csDFOpaqueData(dfType: DFOpaque, data: Any): String = csConstData(dfType.actualType, data) def csDFStructData(dfType: DFStruct, data: List[Any]): String = - printer.csDFStructTypeName(dfType) + dfType.fieldMap - .lazyZip(data) - .map { case ((n, t), d) => - s"$n = ${csConstData(t, d)}" - } - .mkStringBrackets + printer.csDFStructTypeName(dfType) + + dfType.fieldMap + .lazyZip(data) + .map { case ((n, t), d) => + s"$n = ${csConstData(t, d)}" + } + .mkStringBrackets def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String = printer.unsupported def csDFUnitData(dfType: DFUnit, data: Unit): String = printer.unsupported def csDFDoubleData(dfType: DFDouble, data: Option[Double]): String = diff --git a/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLValPrinter.scala b/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLValPrinter.scala index 2fac06be3..976a8b64c 100644 --- a/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLValPrinter.scala +++ b/compiler/stages/src/main/scala/dfhdl/compiler/stages/vhdl/VHDLValPrinter.scala @@ -117,10 +117,11 @@ protected trait VHDLValPrinter extends AbstractValPrinter: case DFString => args.map(_.refCodeString).mkString(" & ") case dfType @ DFStruct(_, _) => - printer.csDFStructTypeName(dfType) + dfType.fieldMap - .lazyZip(args.map(_.refCodeString)) - .map { case ((n, _), d) => s"$n = $d" } - .mkStringBrackets + printer.csDFStructTypeName(dfType) + + dfType.fieldMap + .lazyZip(args.map(_.refCodeString)) + .map { case ((n, _), d) => s"$n = $d" } + .mkStringBrackets // all args are the same ==> repeat function case _ if args.view.map(_.get).allElementsAreEqual => diff --git a/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala b/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala index c35aaafc5..3cdae9269 100644 --- a/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala +++ b/compiler/stages/src/test/scala/StagesSpec/ExplicitNamedVarsSpec.scala @@ -278,7 +278,7 @@ class ExplicitNamedVarsSpec extends StageSpec: // shifted ^ o // else shifted // o <> anon.as(AESByte) - // end xtime + // end xtime // val top = (new xtime).explicitNamedVars // assertCodeString( diff --git a/compiler/stages/src/test/scala/StagesSpec/PrintCodeStringSpec.scala b/compiler/stages/src/test/scala/StagesSpec/PrintCodeStringSpec.scala index a6fe13b4e..125aaccf4 100644 --- a/compiler/stages/src/test/scala/StagesSpec/PrintCodeStringSpec.scala +++ b/compiler/stages/src/test/scala/StagesSpec/PrintCodeStringSpec.scala @@ -1836,7 +1836,8 @@ class PrintCodeStringSpec extends StageSpec: class LongChain extends DFDesign: val a = UInt(8) <> IN val o = UInt(8) <> OUT - o <> (a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a) + o <> + (a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a + a) end LongChain val top = (new LongChain).getCodeString assertNoDiff( diff --git a/core/src/main/scala/dfhdl/core/DFDecimal.scala b/core/src/main/scala/dfhdl/core/DFDecimal.scala index cf8a281bb..a9b95f3ed 100644 --- a/core/src/main/scala/dfhdl/core/DFDecimal.scala +++ b/core/src/main/scala/dfhdl/core/DFDecimal.scala @@ -108,19 +108,17 @@ object DFDecimal: Boolean, Boolean, [BaS <: Boolean, WcS <: Boolean] =>> BaS || ![WcS], - [BaS <: Boolean, WcS <: Boolean] =>> - "Cannot apply a signed wildcard `Int` value to " + - ITE[BaS, "a signed", "an unsigned"] + - " bit-accurate value.\nUse an explicit conversion or `sd\"\"` interpolation." + [BaS <: Boolean, WcS <: Boolean] =>> "Cannot apply a signed wildcard `Int` value to " + + ITE[BaS, "a signed", "an unsigned"] + + " bit-accurate value.\nUse an explicit conversion or `sd\"\"` interpolation." ] object `BaW >= WcW` extends Check2[ Int, Int, [BaW <: Int, WcW <: Int] =>> BaW >= WcW, - [BaW <: Int, WcW <: Int] =>> - "The wildcard `Int` value width (" + WcW + - ") is larger than the bit-accurate value width (" + BaW + ")." + [BaW <: Int, WcW <: Int] =>> "The wildcard `Int` value width (" + WcW + + ") is larger than the bit-accurate value width (" + BaW + ")." ] type SignStr[S <: Boolean] = ITE[S, "a signed", "an unsigned"] object `LS == RS` @@ -994,6 +992,7 @@ object DFXInt: verilogSemanticsWarnMsg ) ) + end if val cw: IntParam[Int] = func.op.runtimeChecked match case FuncOp.+ | FuncOp.- => funcWidth + 1 case FuncOp.* => funcWidth + funcWidth @@ -1008,7 +1007,9 @@ object DFXInt: case Int32 => lhsCarryPromo.toInt.asIR case BitAccurate => - DFVal.Alias.AsIs(dfType, lhsCarryPromo)(using dfc.tag(ir.ImplicitlyFromIntTag)).asIR + DFVal.Alias.AsIs(dfType, lhsCarryPromo)(using + dfc.tag(ir.ImplicitlyFromIntTag) + ).asIR else if ( !dfType.asIR.widthParamRef.isSimilarTo( lhsCarryPromo.dfType.asIR.widthParamRef @@ -1204,8 +1205,12 @@ object DFXInt: // (Int32 NativeType), adapt to the bit-accurate value's sign and width. // When both are wildcards, use LS || RS and Max (both-wildcard = DFInt32-like). resultSign: Id[ITE[LN && ![RN], RS, ITE[RN && ![LN], LS, ITE[LN && RN, LS, LS || RS]]]], - resultWidth: Id[ITE[LN && ![RN], RW, ITE[RN && ![LN], LW, - ITE[LN && RN, LW, + resultWidth: Id[ITE[LN && ![RN], RW, ITE[ + RN && ![LN], + LW, + ITE[ + LN && RN, + LW, IntP.Max[ ITE[![LS] && RS, LW + 1, LW], ITE[![RS] && LS, RW + 1, RW] @@ -1223,9 +1228,11 @@ object DFXInt: ], checkWW: `BaW >= WcW`.Check[ ITE[RN && ![LN], ubLW.Out, ITE[LN && ![RN], ubRW.Out, ubLW.Out]], - ITE[RN && ![LN], + ITE[ + RN && ![LN], ITE[LS && ![RS], ubRW.Out + 1, ubRW.Out], - ITE[LN && ![RN], + ITE[ + LN && ![RN], ITE[RS && ![LS], ubLW.Out + 1, ubLW.Out], ubLW.Out ] @@ -1287,6 +1294,8 @@ object DFXInt: else arithOp(rhsVal.dfType, op.value, rhsVal, lhsVal) .asInstanceOf[Out] + end if + end if }(using dfc, CTName(op.value.toString)) end evOpCommutativeArithDFXInt @@ -1324,7 +1333,8 @@ object DFXInt: ], checkWW: `BaW >= WcW`.Check[ ITE[LN && ![RN], ubRW.Out, ubLW.Out], - ITE[LN && ![RN], + ITE[ + LN && ![RN], ITE[RS && ![LS], ubLW.Out + 1, ubLW.Out], ubLW.Out ] diff --git a/core/src/main/scala/dfhdl/core/DFEnum.scala b/core/src/main/scala/dfhdl/core/DFEnum.scala index 468d8dc1a..65102d386 100644 --- a/core/src/main/scala/dfhdl/core/DFEnum.scala +++ b/core/src/main/scala/dfhdl/core/DFEnum.scala @@ -19,13 +19,11 @@ object DFEncoding: abstract class Default extends StartAt(0) abstract class Gray extends Auto: - final def calcWidth(entryCount: Int): Int = - (entryCount - 1).bitsWidth(false) + final def calcWidth(entryCount: Int): Int = (entryCount - 1).bitsWidth(false) final def encode(idx: Int): BigInt = BigInt(idx ^ (idx >>> 1)) abstract class StartAt[V <: Int & Singleton](value: V) extends Auto: - final def calcWidth(entryCount: Int): Int = - (entryCount - 1 + value).bitsWidth(false) + final def calcWidth(entryCount: Int): Int = (entryCount - 1 + value).bitsWidth(false) final def encode(idx: Int): BigInt = BigInt(idx + value) abstract class OneHot extends Auto: diff --git a/core/src/main/scala/dfhdl/core/DFVal.scala b/core/src/main/scala/dfhdl/core/DFVal.scala index c9cf18468..7b2103b7a 100644 --- a/core/src/main/scala/dfhdl/core/DFVal.scala +++ b/core/src/main/scala/dfhdl/core/DFVal.scala @@ -809,9 +809,9 @@ object DFVal extends DFValLP: args.flatMap { case prevFunc: ir.DFVal.Func if prevFunc.op == op - && prevFunc.isAnonymous - && argCounts(prevFunc) == 1 - && canMergeFunc(dfType, op, prevFunc) => + && prevFunc.isAnonymous + && argCounts(prevFunc) == 1 + && canMergeFunc(dfType, op, prevFunc) => // Track the earliest start position from absorbed Funcs val prevPos = prevFunc.meta.position mergedPositionStart = Some( @@ -855,13 +855,15 @@ object DFVal extends DFValLP: // +, -, * are excluded because carry promotion assumes binary (2-arg) Funcs. // ++ is only merged for flat bits concatenation, not struct/vector/string. private def canMergeFunc( - resultType: ir.DFType, op: FuncOp, prevFunc: ir.DFVal.Func + resultType: ir.DFType, + op: FuncOp, + prevFunc: ir.DFVal.Func )(using ir.MemberGetSet): Boolean = op match case FuncOp.++ => resultType.isInstanceOf[ir.DFBits] && prevFunc.dfType.isInstanceOf[ir.DFBits] case FuncOp.+ | FuncOp.- | FuncOp.`*` => false - case _ => true // &, |, ^, max, min — no carry concept + case _ => true // &, |, ^, max, min — no carry concept end Func object Alias: diff --git a/core/src/test/scala/CoreSpec/DFDecimalSpec.scala b/core/src/test/scala/CoreSpec/DFDecimalSpec.scala index 0b01c7ad4..b4c180c45 100644 --- a/core/src/test/scala/CoreSpec/DFDecimalSpec.scala +++ b/core/src/test/scala/CoreSpec/DFDecimalSpec.scala @@ -556,42 +556,42 @@ class DFDecimalSpec extends DFSpec: val i42: Int = 42 // === Commutative + with Scala Int literals === - val t1 = u8 + 5; t1.verifyValOf[UInt[8]] - val t2 = 5 + u8; t2.verifyValOf[UInt[8]] - val t3 = s8 + 5; t3.verifyValOf[SInt[8]] - val t4 = 5 + s8; t4.verifyValOf[SInt[8]] - val t5 = (-5) + s8; t5.verifyValOf[SInt[8]] - val t6 = s8 + (-5); t6.verifyValOf[SInt[8]] + val t1 = u8 + 5; t1.verifyValOf[UInt[8]] + val t2 = 5 + u8; t2.verifyValOf[UInt[8]] + val t3 = s8 + 5; t3.verifyValOf[SInt[8]] + val t4 = 5 + s8; t4.verifyValOf[SInt[8]] + val t5 = (-5) + s8; t5.verifyValOf[SInt[8]] + val t6 = s8 + (-5); t6.verifyValOf[SInt[8]] // === Commutative * with Scala Int literals === - val t7 = u8 * 3; t7.verifyValOf[UInt[8]] - val t8 = 3 * u8; t8.verifyValOf[UInt[8]] - val t9 = s8 * 3; t9.verifyValOf[SInt[8]] - val t10 = 3 * s8; t10.verifyValOf[SInt[8]] + val t7 = u8 * 3; t7.verifyValOf[UInt[8]] + val t8 = 3 * u8; t8.verifyValOf[UInt[8]] + val t9 = s8 * 3; t9.verifyValOf[SInt[8]] + val t10 = 3 * s8; t10.verifyValOf[SInt[8]] // === Commutative + with Scala non-literal Int === - val t11 = u8 + i42; t11.verifyValOf[UInt[8]] - val t12 = i42 + u8; t12.verifyValOf[UInt[8]] - val t13 = s8 + i42; t13.verifyValOf[SInt[8]] - val t14 = i42 + s8; t14.verifyValOf[SInt[8]] + val t11 = u8 + i42; t11.verifyValOf[UInt[8]] + val t12 = i42 + u8; t12.verifyValOf[UInt[8]] + val t13 = s8 + i42; t13.verifyValOf[SInt[8]] + val t14 = i42 + s8; t14.verifyValOf[SInt[8]] // === Commutative * with Scala non-literal Int === - val t15 = u8 * i42; t15.verifyValOf[UInt[8]] - val t16 = i42 * u8; t16.verifyValOf[UInt[8]] - val t17 = s8 * i42; t17.verifyValOf[SInt[8]] - val t18 = i42 * s8; t18.verifyValOf[SInt[8]] + val t15 = u8 * i42; t15.verifyValOf[UInt[8]] + val t16 = i42 * u8; t16.verifyValOf[UInt[8]] + val t17 = s8 * i42; t17.verifyValOf[SInt[8]] + val t18 = i42 * s8; t18.verifyValOf[SInt[8]] // === Commutative + with DFHDL Int param === - val t19 = u8 + param; t19.verifyValOf[UInt[8]] - val t20 = param + u8; t20.verifyValOf[UInt[8]] - val t21 = s8 + param; t21.verifyValOf[SInt[8]] - val t22 = param + s8; t22.verifyValOf[SInt[8]] + val t19 = u8 + param; t19.verifyValOf[UInt[8]] + val t20 = param + u8; t20.verifyValOf[UInt[8]] + val t21 = s8 + param; t21.verifyValOf[SInt[8]] + val t22 = param + s8; t22.verifyValOf[SInt[8]] // === Commutative * with DFHDL Int param === - val t23 = u8 * param; t23.verifyValOf[UInt[8]] - val t24 = param * u8; t24.verifyValOf[UInt[8]] - val t25 = s8 * param; t25.verifyValOf[SInt[8]] - val t26 = param * s8; t26.verifyValOf[SInt[8]] + val t23 = u8 * param; t23.verifyValOf[UInt[8]] + val t24 = param * u8; t24.verifyValOf[UInt[8]] + val t25 = s8 * param; t25.verifyValOf[SInt[8]] + val t26 = param * s8; t26.verifyValOf[SInt[8]] // === Bits (implicit UInt) with wildcards === val t27 = b8 + 5 @@ -600,46 +600,46 @@ class DFDecimalSpec extends DFSpec: val t30 = param + b8 // === Commutative max/min with wildcards === - val t27b = u8 max 5; t27b.verifyValOf[UInt[8]] - val t27c = 5 max u8; t27c.verifyValOf[UInt[8]] - val t27d = s8 max (-5); t27d.verifyValOf[SInt[8]] - val t27e = (-5) max s8; t27e.verifyValOf[SInt[8]] - val t27f = u8 min i42; t27f.verifyValOf[UInt[8]] - val t27g = i42 min u8; t27g.verifyValOf[UInt[8]] - val t27h = s8 min i42; t27h.verifyValOf[SInt[8]] - val t27i = i42 min s8; t27i.verifyValOf[SInt[8]] - val t27j = u8 max param; t27j.verifyValOf[UInt[8]] - val t27k = param max u8; t27k.verifyValOf[UInt[8]] - val t27l = s8 min param; t27l.verifyValOf[SInt[8]] - val t27m = param min s8; t27m.verifyValOf[SInt[8]] + val t27b = u8 max 5; t27b.verifyValOf[UInt[8]] + val t27c = 5 max u8; t27c.verifyValOf[UInt[8]] + val t27d = s8 max (-5); t27d.verifyValOf[SInt[8]] + val t27e = (-5) max s8; t27e.verifyValOf[SInt[8]] + val t27f = u8 min i42; t27f.verifyValOf[UInt[8]] + val t27g = i42 min u8; t27g.verifyValOf[UInt[8]] + val t27h = s8 min i42; t27h.verifyValOf[SInt[8]] + val t27i = i42 min s8; t27i.verifyValOf[SInt[8]] + val t27j = u8 max param; t27j.verifyValOf[UInt[8]] + val t27k = param max u8; t27k.verifyValOf[UInt[8]] + val t27l = s8 min param; t27l.verifyValOf[SInt[8]] + val t27m = param min s8; t27m.verifyValOf[SInt[8]] // === Param + Param: stays Int (DFInt32) === val param2: Int <> CONST = 20 - val t31 = param + param2; t31.verifyValOf[DFInt32] - val t32 = param * param2; t32.verifyValOf[DFInt32] + val t31 = param + param2; t31.verifyValOf[DFInt32] + val t32 = param * param2; t32.verifyValOf[DFInt32] val t33b = param max param2; t33b.verifyValOf[DFInt32] val t33c = param min param2; t33c.verifyValOf[DFInt32] // === Non-commutative ops: wildcard adapts to LHS === - val t33 = u8 - 3; t33.verifyValOf[UInt[8]] - val t34 = u8 - i42; t34.verifyValOf[UInt[8]] - val t35 = u8 - param; t35.verifyValOf[UInt[8]] - val t36 = u8 / 3; t36.verifyValOf[UInt[8]] - val t37 = u8 / i42; t37.verifyValOf[UInt[8]] - val t38 = u8 / param; t38.verifyValOf[UInt[8]] - val t39 = s8 - 3; t39.verifyValOf[SInt[8]] - val t40 = s8 - i42; t40.verifyValOf[SInt[8]] - val t41 = s8 - param; t41.verifyValOf[SInt[8]] - val t42 = s8 % 3; t42.verifyValOf[SInt[8]] - val t43 = s8 % i42; t43.verifyValOf[SInt[8]] - val t44 = s8 % param; t44.verifyValOf[SInt[8]] + val t33 = u8 - 3; t33.verifyValOf[UInt[8]] + val t34 = u8 - i42; t34.verifyValOf[UInt[8]] + val t35 = u8 - param; t35.verifyValOf[UInt[8]] + val t36 = u8 / 3; t36.verifyValOf[UInt[8]] + val t37 = u8 / i42; t37.verifyValOf[UInt[8]] + val t38 = u8 / param; t38.verifyValOf[UInt[8]] + val t39 = s8 - 3; t39.verifyValOf[SInt[8]] + val t40 = s8 - i42; t40.verifyValOf[SInt[8]] + val t41 = s8 - param; t41.verifyValOf[SInt[8]] + val t42 = s8 % 3; t42.verifyValOf[SInt[8]] + val t43 = s8 % i42; t43.verifyValOf[SInt[8]] + val t44 = s8 % param; t44.verifyValOf[SInt[8]] // === Non-commutative with wildcard LHS === // Wildcard always adapts, even in non-commutative ops - val t45 = 200 - u8; t45.verifyValOf[UInt[8]] - val t46 = i42 - u8; t46.verifyValOf[UInt[8]] - val t47 = param - u8; t47.verifyValOf[UInt[8]] - val t48 = param / u8; t48.verifyValOf[UInt[8]] + val t45 = 200 - u8; t45.verifyValOf[UInt[8]] + val t46 = i42 - u8; t46.verifyValOf[UInt[8]] + val t47 = param - u8; t47.verifyValOf[UInt[8]] + val t48 = param / u8; t48.verifyValOf[UInt[8]] // === Constant propagation === // All-constant expressions produce CONST results @@ -652,8 +652,8 @@ class DFDecimalSpec extends DFSpec: val c6: UInt[8] <> CONST = d"8'5" + param val c7: SInt[8] <> CONST = sd"8'5" + param // Param + VAR is NOT const (verified by type — no CONST annotation) - val nc1 = u8 + param // result is not CONST - val nc2 = param + u8 // result is not CONST + val nc1 = u8 + param // result is not CONST + val nc2 = param + u8 // result is not CONST // === Comparisons: wildcard adapts === val cmp1 = u8 == 200 diff --git a/core/src/test/scala/CoreSpec/DFMatchSpec.scala b/core/src/test/scala/CoreSpec/DFMatchSpec.scala index 34e5f3f0d..7b27c904a 100644 --- a/core/src/test/scala/CoreSpec/DFMatchSpec.scala +++ b/core/src/test/scala/CoreSpec/DFMatchSpec.scala @@ -178,10 +178,10 @@ class DFMatchSpec extends DFSpec: test("Trivial tuple match skip") { import dfhdl.hw.flag.scalaRanges assertCodeString("") { - val (ret, _) = - (0 until 8).foldLeft[(Byte <> VAL, Byte <> VAL)]((all(0), all(0))) { case ((p, a), _) => + val (ret, _) = (0 until 8).foldLeft[(Byte <> VAL, Byte <> VAL)]((all(0), all(0))) { + case ((p, a), _) => (p, a) - } + } } } diff --git a/internals/src/main/scala/dfhdl/internals/Checked.scala b/internals/src/main/scala/dfhdl/internals/Checked.scala index f9ea808d4..f8342654d 100644 --- a/internals/src/main/scala/dfhdl/internals/Checked.scala +++ b/internals/src/main/scala/dfhdl/internals/Checked.scala @@ -57,9 +57,9 @@ private class MacroClass[Q <: Quotes](using val quotes: Q)( case "S" => '{ ${ arg0.asExprOf[Int] } + 1 } case "!" => - '{ !${ arg0.asExprOf[Boolean] } } + '{ ! ${ arg0.asExprOf[Boolean] } } case "Negate" => - '{ -${ arg0.asExprOf[Int] } } + '{ - ${ arg0.asExprOf[Int] } } case "ITE" => // if-then-else '{ if (${ arg0.asExprOf[Boolean] }) ${ arg1.asExpr } else ${ arg2.asExpr } diff --git a/internals/src/main/scala/dfhdl/internals/Exact.scala b/internals/src/main/scala/dfhdl/internals/Exact.scala index a55222d34..3b606bdca 100644 --- a/internals/src/main/scala/dfhdl/internals/Exact.scala +++ b/internals/src/main/scala/dfhdl/internals/Exact.scala @@ -288,7 +288,9 @@ private def ascribeWidenedType(using Quotes)(term: quotes.reflect.Term): quotes. import quotes.reflect.* Typed(term, TypeTree.of(using term.tpe.dealias.asType)) -private def flattenInlined(using Quotes)(term: quotes.reflect.Term): (List[quotes.reflect.Definition], quotes.reflect.Term) = +private def flattenInlined(using + Quotes +)(term: quotes.reflect.Term): (List[quotes.reflect.Definition], quotes.reflect.Term) = import quotes.reflect.* term match case Inlined(_, bindings, inner) => @@ -315,7 +317,7 @@ private def exactOp1Macro[Op, Ctx, OutUB](lhs: Expr[Any])(ctx: Expr[Ctx])(using else val innerTerm = appTerm match case Inlined(_, Nil, inner) => inner - case t => t + case t => t Block(lhsBindings, innerTerm).asExprOf[OutUB] case None => ControlledMacroError.report("Unsupported argument type for this operation.") @@ -380,13 +382,24 @@ private def exactOp2Macro[Op, Ctx, OutUB]( val (lhsBindings, lhsInner) = flattenInlined(lhsTerm) val (rhsBindings, rhsInner) = flattenInlined(rhsTerm) val allBindings = lhsBindings ++ rhsBindings - val appTerm = ascribeWidenedType('{ ${ expr.asInstanceOf[Expr[ExactOp2[Op, Ctx, OutUB, lhsExactInfo.Underlying, rhsExactInfo.Underlying]]] }(${ lhsInner.asExpr }, ${ rhsInner.asExpr })(using $ctx) }.asTerm) + val appTerm = ascribeWidenedType('{ + ${ + expr.asInstanceOf[Expr[ExactOp2[ + Op, + Ctx, + OutUB, + lhsExactInfo.Underlying, + rhsExactInfo.Underlying + ]]] + }(${ lhsInner.asExpr }, ${ rhsInner.asExpr })(using $ctx) + }.asTerm) if allBindings.isEmpty then appTerm.asExprOf[OutUB] else val innerTerm = appTerm match case Inlined(_, Nil, inner) => inner - case t => t + case t => t Block(allBindings, innerTerm).asExprOf[OutUB] + end buildFlattened exactOp2ExprOrError match case Right(expr) => buildFlattened(lhsExactInfo.exactExpr.asTerm, rhsExactInfo.exactExpr.asTerm, expr) @@ -460,7 +473,7 @@ private def exactOp3Macro[Op, Ctx, OutUB]( else val innerTerm = appTerm match case Inlined(_, Nil, inner) => inner - case t => t + case t => t Block(allBindings, innerTerm).asExprOf[OutUB] case None => ControlledMacroError.report("Unsupported argument types for this operation.") diff --git a/lib/src/test/scala/AES/defs.scala b/lib/src/test/scala/AES/defs.scala index 961e571a2..8578d5f15 100644 --- a/lib/src/test/scala/AES/defs.scala +++ b/lib/src/test/scala/AES/defs.scala @@ -36,8 +36,7 @@ extension (lhs: AESByte <> VAL) // corresponding powers in the polynomials for the two elements. The addition is performed with // the XOR operation. @targetName("addByte") - @inline def +(rhs: AESByte <> VAL): AESByte <> DFRET = - (lhs.actual ^ rhs.actual).as(AESByte) + @inline def +(rhs: AESByte <> VAL): AESByte <> DFRET = (lhs.actual ^ rhs.actual).as(AESByte) private def xtime: AESByte <> DFRET = lhs.mapActual: lhs => val shifted = lhs << 1 diff --git a/plugin/src/main/scala/plugin/FlattenInlinedPhase.scala b/plugin/src/main/scala/plugin/FlattenInlinedPhase.scala index 37c9f82e8..5431abcd7 100644 --- a/plugin/src/main/scala/plugin/FlattenInlinedPhase.scala +++ b/plugin/src/main/scala/plugin/FlattenInlinedPhase.scala @@ -39,7 +39,9 @@ class FlattenInlinedPhase(setting: Setting) extends PluginPhase: val topLevelCls = callSym.topLevelClass if !topLevelCls.exists then call else if callSym.is(Macro) then - ref(topLevelCls.owner).select(topLevelCls.name)(using ctx.withOwner(topLevelCls.owner)).withSpan(call.span) + ref(topLevelCls.owner).select(topLevelCls.name)(using + ctx.withOwner(topLevelCls.owner) + ).withSpan(call.span) else Ident(topLevelCls.typeRef).withSpan(call.span) diff --git a/project/DFHDLCommands.scala b/project/DFHDLCommands.scala index e6434b0df..3339c3c48 100644 --- a/project/DFHDLCommands.scala +++ b/project/DFHDLCommands.scala @@ -19,7 +19,7 @@ object DFHDLCommands { (LocalProject("lib") / Test / sources) := Nil ), state) newState - } + } val libPlayground = Command.command("libPlayground") { state => val extracted = Project.extract(state) val newState = extracted.appendWithSession(Seq( From 83b7205b9288e31f4aa8abc5edc06199854be992 Mon Sep 17 00:00:00 2001 From: Scala Steward Date: Mon, 13 Apr 2026 16:19:38 +0000 Subject: [PATCH 3/3] Add 'Reformat with scalafmt 3.11.0' to .git-blame-ignore-revs --- .git-blame-ignore-revs | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 .git-blame-ignore-revs diff --git a/.git-blame-ignore-revs b/.git-blame-ignore-revs new file mode 100644 index 000000000..e694beea3 --- /dev/null +++ b/.git-blame-ignore-revs @@ -0,0 +1,2 @@ +# Scala Steward: Reformat with scalafmt 3.11.0 +b96c4d23ce2ab8c80bd5d83129a90fe93ebe2a3f