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UNIWA

UNIVERSITY OF WEST ATTICA
SCHOOL OF ENGINEERING
DEPARTMENT OF COMPUTER ENGINEERING AND INFORMATICS

University of West Attica · Department of Computer Engineering and Informatics

Digital Circuit Design

Register Files

Vasileios Evangelos Athanasiou
Student ID: 19390005

GitHub · LinkedIn

Supervision

Supervisor: Ioannis Vogiatzis, Professor

UNIWA Profile · LinkedIn

Supervisor: Panagiotis Karkazis, Associate Professor

UNIWA Profile · LinkedIn

Co-supervisor: Athanasios Milidonis, Postdoctoral Researcher

Scholar · LinkedIn

Athens, May 2023

INSTALL

Register Files

This repository contains VHDL implementations of fundamental digital logic circuits along with testbenches for functional verification using ModelSim Altera Starter Edition.
The project is intended for digital circuit design education and laboratory exercises.

1. Prerequisites

1.1 Operating System

Supported platforms:

  • Windows (recommended – best ModelSim support)
  • Linux
  • macOS (may require legacy or alternative simulators)

2. VHDL Simulation Software

2.1 ModelSim Altera Starter Edition (Recommended)

This project was developed and verified using:

  • ModelSim Altera Starter Edition
  • Provided by Intel FPGA (formerly Altera)

Capabilities used:

  • VHDL-2008 compatible simulation
  • Waveform visualization
  • Testbench execution

Note: Newer systems may use ModelSim Intel FPGA Edition or Questa Intel FPGA Starter as replacements.

3. Text Editor / IDE (Optional but Recommended)

For editing and reviewing VHDL files:

  • Visual Studio Code + VHDL extension
  • Notepad++
  • Vim / Emacs
  • ModelSim built-in editor

4. Knowledge Prerequisites

To understand and modify the project, basic knowledge of:

  • Digital logic design
  • VHDL syntax and semantics
  • Dataflow architecture
  • Testbench-driven verification
  • Combinational circuits (adders, multiplexers, decoders)

is recommended.

5. Installation / Setup

5.1 Clone the Repository

Using Git:

git clone https://github.com/Digital-Circuit-Design/Register-Files.git

5.2 Alternative (Without Git)

  • Open the repository URL in your browser
  • Click Code → Download ZIP
  • Extract the ZIP file to a local directory

5.3 Install ModelSim

  1. Download ModelSim Altera Starter Edition (or Intel FPGA equivalent)
  2. Complete installation following vendor instructions
  3. Verify installation by launching ModelSim successfully

6. Project Setup in ModelSim

6.1 Create a New Project

  1. Open ModelSim
  2. Select File → New → Project
  3. Set:
    • Project Name (e.g. VHDL_Lab)
    • Project Location (your cloned repository path)
  4. Choose Create Project

6.2 Add VHDL Source Files

  1. In the Add Items to Project window:
    • Select Add Existing File
  2. Navigate to the src/ directory
  3. Add:
    • All *.vhd files (designs and testbenches)
  4. Finish project creation

6.3 Compile the Project

  1. In the Project tab:
    • Select Compile → Compile All
  2. Ensure:
    • No syntax errors
    • Successful compilation messages in the transcript

7. Simulation & Verification

7.1 View Waveforms

  1. In the simulation window:
    • Add signals to the waveform
  2. Run simulation:
run -all
  1. Verify:
    • Correct logical behavior
    • Expected outputs for each test case

8. Open the Documentation

  1. Navigate to the docs/ directory
  2. Open the report corresponding to your preferred language:
    • English: Register-Files.pdf
    • Greek: Αρχεία-Καταχώρησης.pdf