diff --git a/fossee/asynchronous_fifo/async ckt.png b/fossee/asynchronous_fifo/async ckt.png
new file mode 100644
index 000000000..7ae9f4ba7
Binary files /dev/null and b/fossee/asynchronous_fifo/async ckt.png differ
diff --git a/fossee/asynchronous_fifo/async_code1.png b/fossee/asynchronous_fifo/async_code1.png
new file mode 100644
index 000000000..b2b691f63
Binary files /dev/null and b/fossee/asynchronous_fifo/async_code1.png differ
diff --git a/fossee/asynchronous_fifo/async_code2.png b/fossee/asynchronous_fifo/async_code2.png
new file mode 100644
index 000000000..624b3a123
Binary files /dev/null and b/fossee/asynchronous_fifo/async_code2.png differ
diff --git a/fossee/asynchronous_fifo/async_module.png b/fossee/asynchronous_fifo/async_module.png
new file mode 100644
index 000000000..dbb6dbb26
Binary files /dev/null and b/fossee/asynchronous_fifo/async_module.png differ
diff --git a/fossee/asynchronous_fifo/async_schematic.png b/fossee/asynchronous_fifo/async_schematic.png
new file mode 100644
index 000000000..a8ac07a60
Binary files /dev/null and b/fossee/asynchronous_fifo/async_schematic.png differ
diff --git a/fossee/asynchronous_fifo/async_simulation.jpeg b/fossee/asynchronous_fifo/async_simulation.jpeg
new file mode 100644
index 000000000..82ba10017
Binary files /dev/null and b/fossee/asynchronous_fifo/async_simulation.jpeg differ
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo/analysis b/fossee/asynchronous_fifo/asynchronous_fifo/analysis
new file mode 100644
index 000000000..9b264de7a
--- /dev/null
+++ b/fossee/asynchronous_fifo/asynchronous_fifo/analysis
@@ -0,0 +1 @@
+.tran 1e-09 450e-09 0e-09
\ No newline at end of file
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo-cache.lib b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo-cache.lib
new file mode 100644
index 000000000..45cb8e8a4
--- /dev/null
+++ b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo-cache.lib
@@ -0,0 +1,195 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_5
+#
+DEF adc_bridge_5 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_5" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -400 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X OUT1 6 550 50 200 L 50 50 1 1 O
+X OUT2 7 550 -50 200 L 50 50 1 1 O
+X OUT3 8 550 -150 200 L 50 50 1 1 O
+X OUT4 9 550 -250 200 L 50 50 1 1 O
+X OUT5 10 550 -350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# asynchronous_fifo
+#
+DEF asynchronous_fifo U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "asynchronous_fifo" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 500 0 1 0 N
+X wclk0 1 2150 1900 200 R 50 50 1 1 I
+X rclk0 2 2150 1800 200 R 50 50 1 1 I
+X rst0 3 2150 1700 200 R 50 50 1 1 I
+X wr_en0 4 2150 1600 200 R 50 50 1 1 I
+X rd_en0 5 2150 1500 200 R 50 50 1 1 I
+X din7 6 2150 1400 200 R 50 50 1 1 I
+X din6 7 2150 1300 200 R 50 50 1 1 I
+X din5 8 2150 1200 200 R 50 50 1 1 I
+X din4 9 2150 1100 200 R 50 50 1 1 I
+X din3 10 2150 1000 200 R 50 50 1 1 I
+X dout1 20 3550 1300 200 L 50 50 1 1 O
+X din2 11 2150 900 200 R 50 50 1 1 I
+X dout0 21 3550 1200 200 L 50 50 1 1 O
+X din1 12 2150 800 200 R 50 50 1 1 I
+X full0 22 3550 1100 200 L 50 50 1 1 O
+X din0 13 2150 700 200 R 50 50 1 1 I
+X empty0 23 3550 1000 200 L 50 50 1 1 O
+X dout7 14 3550 1900 200 L 50 50 1 1 O
+X dout6 15 3550 1800 200 L 50 50 1 1 O
+X dout5 16 3550 1700 200 L 50 50 1 1 O
+X dout4 17 3550 1600 200 L 50 50 1 1 O
+X dout3 18 3550 1500 200 L 50 50 1 1 O
+X dout2 19 3550 1400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.cir b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.cir
new file mode 100644
index 000000000..16c37f35d
--- /dev/null
+++ b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.cir
@@ -0,0 +1,52 @@
+* C:\Users\VLSI\eSim-Workspace\asynchronous_fifo\asynchronous_fifo.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/03/2026 19:49:05
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ Net-_U11-Pad9_ Net-_U11-Pad10_ Net-_U11-Pad11_ Net-_U11-Pad12_ Net-_U11-Pad13_ Net-_U11-Pad14_ Net-_U11-Pad15_ Net-_U11-Pad16_ Net-_U11-Pad17_ Net-_U11-Pad18_ Net-_U11-Pad19_ Net-_U11-Pad20_ Net-_U11-Pad21_ Net-_U11-Pad22_ Net-_U11-Pad23_ asynchronous_fifo
+U17 d7 d6 d5 d4 d3 d2 d1 d0 Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ Net-_U11-Pad9_ Net-_U11-Pad10_ Net-_U11-Pad11_ Net-_U11-Pad12_ Net-_U11-Pad13_ adc_bridge_8
+U16 wclk0 rclk0 rst0 wr_en0 rd_en0 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ adc_bridge_5
+U18 Net-_U11-Pad14_ Net-_U11-Pad15_ Net-_U11-Pad16_ Net-_U11-Pad17_ Net-_U11-Pad18_ Net-_U11-Pad19_ Net-_U11-Pad20_ Net-_U11-Pad21_ q7 q6 q5 q4 q3 q2 q1 q0 dac_bridge_8
+U19 Net-_U11-Pad22_ Net-_U11-Pad23_ full0 empty0 dac_bridge_2
+v11 wclk0 GND pulse
+v12 rclk0 GND pulse
+v13 rst0 GND pulse
+v5 wr_en0 GND pulse
+v6 rd_en0 GND pulse
+v7 d7 GND pulse
+v8 d6 GND pulse
+v1 d5 GND pulse
+v2 d4 GND pulse
+v9 d3 GND pulse
+v10 d2 GND pulse
+v3 d1 GND pulse
+v4 ? GND pulse
+U2 wclk0 plot_v1
+U1 rclk0 plot_v1
+U3 rst0 plot_v1
+U4 wr_en0 plot_v1
+U6 rd_en0 plot_v1
+U10 d7 plot_v1
+U7 d6 plot_v1
+U13 d5 plot_v1
+U9 d4 plot_v1
+U5 d3 plot_v1
+U15 d3 plot_v1
+U12 d2 plot_v1
+U14 d1 plot_v1
+U8 d0 plot_v1
+U20 q7 plot_v1
+U21 q6 plot_v1
+U22 q5 plot_v1
+U23 q4 plot_v1
+U24 q3 plot_v1
+U25 q2 plot_v1
+U26 q1 plot_v1
+U27 q0 plot_v1
+U28 full0 plot_v1
+U29 empty0 plot_v1
+
+.end
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.cir.out b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.cir.out
new file mode 100644
index 000000000..9c3a4cde5
--- /dev/null
+++ b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.cir.out
@@ -0,0 +1,69 @@
+* c:\users\vlsi\esim-workspace\asynchronous_fifo\asynchronous_fifo.cir
+
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ net-_u11-pad11_ net-_u11-pad12_ net-_u11-pad13_ net-_u11-pad14_ net-_u11-pad15_ net-_u11-pad16_ net-_u11-pad17_ net-_u11-pad18_ net-_u11-pad19_ net-_u11-pad20_ net-_u11-pad21_ net-_u11-pad22_ net-_u11-pad23_ asynchronous_fifo
+* u17 d7 d6 d5 d4 d3 d2 d1 d0 net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ net-_u11-pad11_ net-_u11-pad12_ net-_u11-pad13_ adc_bridge_8
+* u16 wclk0 rclk0 rst0 wr_en0 rd_en0 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ adc_bridge_5
+* u18 net-_u11-pad14_ net-_u11-pad15_ net-_u11-pad16_ net-_u11-pad17_ net-_u11-pad18_ net-_u11-pad19_ net-_u11-pad20_ net-_u11-pad21_ q7 q6 q5 q4 q3 q2 q1 q0 dac_bridge_8
+* u19 net-_u11-pad22_ net-_u11-pad23_ full0 empty0 dac_bridge_2
+v11 wclk0 gnd pulse(0 1 0n 1n 1n 10n 20n)
+v12 rclk0 gnd pulse(0 1 0n 1n 1n 15n 30n)
+v13 rst0 gnd pulse(0 1 40n 1n 1n 1000n 2000n)
+v5 wr_en0 gnd pulse(0 1 60n 1n 1n 120n 240n)
+v6 rd_en0 gnd pulse(0 1 200n 1n 1n 120n 240n)
+v4 d0 gnd pulse(0 1 60n 1n 1n 20n 40n)
+v3 d1 gnd pulse(0 1 80n 1n 1n 40n 80n)
+v10 d2 gnd pulse(0 1 120n 1n 1n 80n 160n)
+v9 d3 gnd pulse(0 0 0 0 0 0 0)
+v2 d4 gnd pulse(0 0 0 0 0 0 0)
+v1 d5 gnd pulse(0 0 0 0 0 0 0)
+v8 d6 gnd pulse(0 0 0 0 0 0 0)
+v7 d7 gnd pulse(0 0 0 0 0 0 0)
+* u2 wclk0 plot_v1
+* u1 rclk0 plot_v1
+* u3 rst0 plot_v1
+* u4 wr_en0 plot_v1
+* u6 rd_en0 plot_v1
+* u10 d7 plot_v1
+* u7 d6 plot_v1
+* u13 d5 plot_v1
+* u9 d4 plot_v1
+* u5 d3 plot_v1
+* u15 d3 plot_v1
+* u12 d2 plot_v1
+* u14 d1 plot_v1
+* u8 d0 plot_v1
+* u20 q7 plot_v1
+* u21 q6 plot_v1
+* u22 q5 plot_v1
+* u23 q4 plot_v1
+* u24 q3 plot_v1
+* u25 q2 plot_v1
+* u26 q1 plot_v1
+* u27 q0 plot_v1
+* u28 full0 plot_v1
+* u29 empty0 plot_v1
+a1 [net-_u11-pad1_ ] [net-_u11-pad2_ ] [net-_u11-pad3_ ] [net-_u11-pad4_ ] [net-_u11-pad5_ ] [net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ net-_u11-pad11_ net-_u11-pad12_ net-_u11-pad13_ ] [net-_u11-pad14_ net-_u11-pad15_ net-_u11-pad16_ net-_u11-pad17_ net-_u11-pad18_ net-_u11-pad19_ net-_u11-pad20_ net-_u11-pad21_ ] [net-_u11-pad22_ ] [net-_u11-pad23_ ] u11
+a2 [d7 d6 d5 d4 d3 d2 d1 d0 ] [net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ net-_u11-pad11_ net-_u11-pad12_ net-_u11-pad13_ ] u17
+a3 [wclk0 rclk0 rst0 wr_en0 rd_en0 ] [net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ ] u16
+a4 [net-_u11-pad14_ net-_u11-pad15_ net-_u11-pad16_ net-_u11-pad17_ net-_u11-pad18_ net-_u11-pad19_ net-_u11-pad20_ net-_u11-pad21_ ] [q7 q6 q5 q4 q3 q2 q1 q0 ] u18
+a5 [net-_u11-pad22_ net-_u11-pad23_ ] [full0 empty0 ] u19
+* Schematic Name: asynchronous_fifo, NgSpice Name: asynchronous_fifo
+.model u11 asynchronous_fifo(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u17 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_5, NgSpice Name: adc_bridge
+.model u16 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
+.model u18 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u19 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 1e-09 450e-09 0e-09
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(q0)+6 v(q1)+12 v(q2)+18 v(q3)+24 v(q4)+30 v(q5)+36 v(q6)+42 v(q7)+48 v(full0)+54 v(empty0)+60 v(d0)+66 v(d1)+72 v(d2)+78 v(d3)+84 v(d4)+90 v(d5)+96 v(d6)+102 v(d7)+108 v(wr_en0)+114 v(rd_en0)+120 v(rst0)+126 v(wclk0)+132 v(rclk0)+138
+.endc
+.end
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.pro b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.proj b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.proj
new file mode 100644
index 000000000..4347e6d6a
--- /dev/null
+++ b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.proj
@@ -0,0 +1 @@
+schematicFile asynchronous_fifo.sch
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.sch b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.sch
new file mode 100644
index 000000000..73c9317fc
--- /dev/null
+++ b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.sch
@@ -0,0 +1,936 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:asynchronous_fifo-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L asynchronous_fifo U11
+U 1 1 69A5990F
+P 3100 4750
+F 0 "U11" H 5950 6550 60 0000 C CNN
+F 1 "asynchronous_fifo" H 5950 6750 60 0000 C CNN
+F 2 "" H 5950 6700 60 0000 C CNN
+F 3 "" H 5950 6700 60 0000 C CNN
+ 1 3100 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_8 U17
+U 1 1 69A5994E
+P 4700 3400
+F 0 "U17" H 4700 3400 60 0000 C CNN
+F 1 "adc_bridge_8" H 4700 3550 60 0000 C CNN
+F 2 "" H 4700 3400 60 0000 C CNN
+F 3 "" H 4700 3400 60 0000 C CNN
+ 1 4700 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_5 U16
+U 1 1 69A599E9
+P 4050 2150
+F 0 "U16" H 4050 2150 60 0000 C CNN
+F 1 "adc_bridge_5" H 4050 2300 60 0000 C CNN
+F 2 "" H 4050 2150 60 0000 C CNN
+F 3 "" H 4050 2150 60 0000 C CNN
+ 1 4050 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_8 U18
+U 1 1 69A59AB7
+P 7250 2900
+F 0 "U18" H 7250 2900 60 0000 C CNN
+F 1 "dac_bridge_8" H 7250 3050 60 0000 C CNN
+F 2 "" H 7250 2900 60 0000 C CNN
+F 3 "" H 7250 2900 60 0000 C CNN
+ 1 7250 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_2 U19
+U 1 1 69A59B57
+P 7250 4050
+F 0 "U19" H 7250 4050 60 0000 C CNN
+F 1 "dac_bridge_2" H 7300 4200 60 0000 C CNN
+F 2 "" H 7250 4050 60 0000 C CNN
+F 3 "" H 7250 4050 60 0000 C CNN
+ 1 7250 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v11
+U 1 1 69A59EBF
+P 1550 1450
+F 0 "v11" H 1350 1550 60 0000 C CNN
+F 1 "pulse" H 1350 1400 60 0000 C CNN
+F 2 "R1" H 1250 1450 60 0000 C CNN
+F 3 "" H 1550 1450 60 0000 C CNN
+ 1 1550 1450
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v12
+U 1 1 69A59F40
+P 1550 1900
+F 0 "v12" H 1350 2000 60 0000 C CNN
+F 1 "pulse" H 1350 1850 60 0000 C CNN
+F 2 "R1" H 1250 1900 60 0000 C CNN
+F 3 "" H 1550 1900 60 0000 C CNN
+ 1 1550 1900
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v13
+U 1 1 69A59F6C
+P 1550 2350
+F 0 "v13" H 1350 2450 60 0000 C CNN
+F 1 "pulse" H 1350 2300 60 0000 C CNN
+F 2 "R1" H 1250 2350 60 0000 C CNN
+F 3 "" H 1550 2350 60 0000 C CNN
+ 1 1550 2350
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v5
+U 1 1 69A59FA7
+P 1500 2750
+F 0 "v5" H 1300 2850 60 0000 C CNN
+F 1 "pulse" H 1300 2700 60 0000 C CNN
+F 2 "R1" H 1200 2750 60 0000 C CNN
+F 3 "" H 1500 2750 60 0000 C CNN
+ 1 1500 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v6
+U 1 1 69A59FD7
+P 1500 3100
+F 0 "v6" H 1300 3200 60 0000 C CNN
+F 1 "pulse" H 1300 3050 60 0000 C CNN
+F 2 "R1" H 1200 3100 60 0000 C CNN
+F 3 "" H 1500 3100 60 0000 C CNN
+ 1 1500 3100
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v7
+U 1 1 69A5A06E
+P 1500 3700
+F 0 "v7" H 1300 3800 60 0000 C CNN
+F 1 "pulse" H 1300 3650 60 0000 C CNN
+F 2 "R1" H 1200 3700 60 0000 C CNN
+F 3 "" H 1500 3700 60 0000 C CNN
+ 1 1500 3700
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v8
+U 1 1 69A5A075
+P 1500 4150
+F 0 "v8" H 1300 4250 60 0000 C CNN
+F 1 "pulse" H 1300 4100 60 0000 C CNN
+F 2 "R1" H 1200 4150 60 0000 C CNN
+F 3 "" H 1500 4150 60 0000 C CNN
+ 1 1500 4150
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v1
+U 1 1 69A5A07C
+P 1450 4550
+F 0 "v1" H 1250 4650 60 0000 C CNN
+F 1 "pulse" H 1250 4500 60 0000 C CNN
+F 2 "R1" H 1150 4550 60 0000 C CNN
+F 3 "" H 1450 4550 60 0000 C CNN
+ 1 1450 4550
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v2
+U 1 1 69A5A083
+P 1450 4900
+F 0 "v2" H 1250 5000 60 0000 C CNN
+F 1 "pulse" H 1250 4850 60 0000 C CNN
+F 2 "R1" H 1150 4900 60 0000 C CNN
+F 3 "" H 1450 4900 60 0000 C CNN
+ 1 1450 4900
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v9
+U 1 1 69A5A4B4
+P 1500 5450
+F 0 "v9" H 1300 5550 60 0000 C CNN
+F 1 "pulse" H 1300 5400 60 0000 C CNN
+F 2 "R1" H 1200 5450 60 0000 C CNN
+F 3 "" H 1500 5450 60 0000 C CNN
+ 1 1500 5450
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v10
+U 1 1 69A5A4BB
+P 1500 5900
+F 0 "v10" H 1300 6000 60 0000 C CNN
+F 1 "pulse" H 1300 5850 60 0000 C CNN
+F 2 "R1" H 1200 5900 60 0000 C CNN
+F 3 "" H 1500 5900 60 0000 C CNN
+ 1 1500 5900
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v3
+U 1 1 69A5A4C2
+P 1450 6300
+F 0 "v3" H 1250 6400 60 0000 C CNN
+F 1 "pulse" H 1250 6250 60 0000 C CNN
+F 2 "R1" H 1150 6300 60 0000 C CNN
+F 3 "" H 1450 6300 60 0000 C CNN
+ 1 1450 6300
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v4
+U 1 1 69A5A4C9
+P 1450 6650
+F 0 "v4" H 1250 6750 60 0000 C CNN
+F 1 "pulse" H 1250 6600 60 0000 C CNN
+F 2 "R1" H 1150 6650 60 0000 C CNN
+F 3 "" H 1450 6650 60 0000 C CNN
+ 1 1450 6650
+ 0 1 1 0
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 69A5B8D2
+P 750 1450
+F 0 "#PWR01" H 750 1200 50 0001 C CNN
+F 1 "GND" H 750 1300 50 0000 C CNN
+F 2 "" H 750 1450 50 0001 C CNN
+F 3 "" H 750 1450 50 0001 C CNN
+ 1 750 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 69A5BCDB
+P 1100 1900
+F 0 "#PWR02" H 1100 1650 50 0001 C CNN
+F 1 "GND" H 1100 1750 50 0000 C CNN
+F 2 "" H 1100 1900 50 0001 C CNN
+F 3 "" H 1100 1900 50 0001 C CNN
+ 1 1100 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 69A5BD13
+P 1100 2350
+F 0 "#PWR03" H 1100 2100 50 0001 C CNN
+F 1 "GND" H 1100 2200 50 0000 C CNN
+F 2 "" H 1100 2350 50 0001 C CNN
+F 3 "" H 1100 2350 50 0001 C CNN
+ 1 1100 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR04
+U 1 1 69A5BD4B
+P 1050 2750
+F 0 "#PWR04" H 1050 2500 50 0001 C CNN
+F 1 "GND" H 1050 2600 50 0000 C CNN
+F 2 "" H 1050 2750 50 0001 C CNN
+F 3 "" H 1050 2750 50 0001 C CNN
+ 1 1050 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR05
+U 1 1 69A5BD83
+P 1050 3100
+F 0 "#PWR05" H 1050 2850 50 0001 C CNN
+F 1 "GND" H 1050 2950 50 0000 C CNN
+F 2 "" H 1050 3100 50 0001 C CNN
+F 3 "" H 1050 3100 50 0001 C CNN
+ 1 1050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR06
+U 1 1 69A5C11B
+P 1050 3700
+F 0 "#PWR06" H 1050 3450 50 0001 C CNN
+F 1 "GND" H 1050 3550 50 0000 C CNN
+F 2 "" H 1050 3700 50 0001 C CNN
+F 3 "" H 1050 3700 50 0001 C CNN
+ 1 1050 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR07
+U 1 1 69A5C153
+P 1050 4150
+F 0 "#PWR07" H 1050 3900 50 0001 C CNN
+F 1 "GND" H 1050 4000 50 0000 C CNN
+F 2 "" H 1050 4150 50 0001 C CNN
+F 3 "" H 1050 4150 50 0001 C CNN
+ 1 1050 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR08
+U 1 1 69A5C18B
+P 1000 4550
+F 0 "#PWR08" H 1000 4300 50 0001 C CNN
+F 1 "GND" H 1000 4400 50 0000 C CNN
+F 2 "" H 1000 4550 50 0001 C CNN
+F 3 "" H 1000 4550 50 0001 C CNN
+ 1 1000 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR09
+U 1 1 69A5C1C3
+P 1000 4900
+F 0 "#PWR09" H 1000 4650 50 0001 C CNN
+F 1 "GND" H 1000 4750 50 0000 C CNN
+F 2 "" H 1000 4900 50 0001 C CNN
+F 3 "" H 1000 4900 50 0001 C CNN
+ 1 1000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR010
+U 1 1 69A5C669
+P 1050 5450
+F 0 "#PWR010" H 1050 5200 50 0001 C CNN
+F 1 "GND" H 1050 5300 50 0000 C CNN
+F 2 "" H 1050 5450 50 0001 C CNN
+F 3 "" H 1050 5450 50 0001 C CNN
+ 1 1050 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR011
+U 1 1 69A5C6A1
+P 1050 5900
+F 0 "#PWR011" H 1050 5650 50 0001 C CNN
+F 1 "GND" H 1050 5750 50 0000 C CNN
+F 2 "" H 1050 5900 50 0001 C CNN
+F 3 "" H 1050 5900 50 0001 C CNN
+ 1 1050 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR012
+U 1 1 69A5C6D9
+P 1000 6300
+F 0 "#PWR012" H 1000 6050 50 0001 C CNN
+F 1 "GND" H 1000 6150 50 0000 C CNN
+F 2 "" H 1000 6300 50 0001 C CNN
+F 3 "" H 1000 6300 50 0001 C CNN
+ 1 1000 6300
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR013
+U 1 1 69A5C711
+P 1000 6650
+F 0 "#PWR013" H 1000 6400 50 0001 C CNN
+F 1 "GND" H 1000 6500 50 0000 C CNN
+F 2 "" H 1000 6650 50 0001 C CNN
+F 3 "" H 1000 6650 50 0001 C CNN
+ 1 1000 6650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG014
+U 1 1 69A5CC6F
+P 950 1200
+F 0 "#FLG014" H 950 1275 50 0001 C CNN
+F 1 "PWR_FLAG" H 950 1350 50 0000 C CNN
+F 2 "" H 950 1200 50 0001 C CNN
+F 3 "" H 950 1200 50 0001 C CNN
+ 1 950 1200
+ 1 0 0 -1
+$EndComp
+Text GLabel 3300 1450 1 60 Input ~ 0
+wclk0
+Text GLabel 3300 1900 1 60 Input ~ 0
+rclk0
+Text GLabel 3300 2300 1 60 Input ~ 0
+rst0
+Text GLabel 3150 2400 1 60 Input ~ 0
+wr_en0
+Text GLabel 3400 2500 1 60 Input ~ 0
+rd_en0
+Text GLabel 3750 3300 1 60 Input ~ 0
+d7
+Text GLabel 3950 3450 1 60 Input ~ 0
+d6
+Text GLabel 3800 3550 1 60 Input ~ 0
+d5
+Text GLabel 3950 3650 1 60 Input ~ 0
+d4
+Text GLabel 3800 3750 1 60 Input ~ 0
+d3
+Text GLabel 3800 3950 1 60 Input ~ 0
+d1
+Text GLabel 4000 3850 1 60 Input ~ 0
+d2
+Text GLabel 4000 4050 1 60 Input ~ 0
+d0
+$Comp
+L plot_v1 U2
+U 1 1 69A5EB63
+P 2400 1500
+F 0 "U2" H 2400 2000 60 0000 C CNN
+F 1 "plot_v1" H 2600 1850 60 0000 C CNN
+F 2 "" H 2400 1500 60 0000 C CNN
+F 3 "" H 2400 1500 60 0000 C CNN
+ 1 2400 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 69A5EBC2
+P 2200 1950
+F 0 "U1" H 2200 2450 60 0000 C CNN
+F 1 "plot_v1" H 2400 2300 60 0000 C CNN
+F 2 "" H 2200 1950 60 0000 C CNN
+F 3 "" H 2200 1950 60 0000 C CNN
+ 1 2200 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U3
+U 1 1 69A5EC15
+P 2400 2300
+F 0 "U3" H 2400 2800 60 0000 C CNN
+F 1 "plot_v1" H 2600 2650 60 0000 C CNN
+F 2 "" H 2400 2300 60 0000 C CNN
+F 3 "" H 2400 2300 60 0000 C CNN
+ 1 2400 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 69A5EC60
+P 2550 2550
+F 0 "U4" H 2550 3050 60 0000 C CNN
+F 1 "plot_v1" H 2750 2900 60 0000 C CNN
+F 2 "" H 2550 2550 60 0000 C CNN
+F 3 "" H 2550 2550 60 0000 C CNN
+ 1 2550 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 69A5ECB1
+P 2650 2650
+F 0 "U6" H 2650 3150 60 0000 C CNN
+F 1 "plot_v1" H 2850 3000 60 0000 C CNN
+F 2 "" H 2650 2650 60 0000 C CNN
+F 3 "" H 2650 2650 60 0000 C CNN
+ 1 2650 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U10
+U 1 1 69A5F66B
+P 3000 3350
+F 0 "U10" H 3000 3850 60 0000 C CNN
+F 1 "plot_v1" H 3200 3700 60 0000 C CNN
+F 2 "" H 3000 3350 60 0000 C CNN
+F 3 "" H 3000 3350 60 0000 C CNN
+ 1 3000 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U7
+U 1 1 69A5F6C4
+P 2700 3600
+F 0 "U7" H 2700 4100 60 0000 C CNN
+F 1 "plot_v1" H 2900 3950 60 0000 C CNN
+F 2 "" H 2700 3600 60 0000 C CNN
+F 3 "" H 2700 3600 60 0000 C CNN
+ 1 2700 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U13
+U 1 1 69A5F71D
+P 3300 3700
+F 0 "U13" H 3300 4200 60 0000 C CNN
+F 1 "plot_v1" H 3500 4050 60 0000 C CNN
+F 2 "" H 3300 3700 60 0000 C CNN
+F 3 "" H 3300 3700 60 0000 C CNN
+ 1 3300 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U9
+U 1 1 69A5F790
+P 2950 3800
+F 0 "U9" H 2950 4300 60 0000 C CNN
+F 1 "plot_v1" H 3150 4150 60 0000 C CNN
+F 2 "" H 2950 3800 60 0000 C CNN
+F 3 "" H 2950 3800 60 0000 C CNN
+ 1 2950 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 69A5F7F1
+P 2550 3900
+F 0 "U5" H 2550 4400 60 0000 C CNN
+F 1 "plot_v1" H 2750 4250 60 0000 C CNN
+F 2 "" H 2550 3900 60 0000 C CNN
+F 3 "" H 2550 3900 60 0000 C CNN
+ 1 2550 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U15
+U 1 1 69A5F850
+P 3550 3900
+F 0 "U15" H 3550 4400 60 0000 C CNN
+F 1 "plot_v1" H 3750 4250 60 0000 C CNN
+F 2 "" H 3550 3900 60 0000 C CNN
+F 3 "" H 3550 3900 60 0000 C CNN
+ 1 3550 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U12
+U 1 1 69A5F8CB
+P 3150 4000
+F 0 "U12" H 3150 4500 60 0000 C CNN
+F 1 "plot_v1" H 3350 4350 60 0000 C CNN
+F 2 "" H 3150 4000 60 0000 C CNN
+F 3 "" H 3150 4000 60 0000 C CNN
+ 1 3150 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U14
+U 1 1 69A5F938
+P 3400 4100
+F 0 "U14" H 3400 4600 60 0000 C CNN
+F 1 "plot_v1" H 3600 4450 60 0000 C CNN
+F 2 "" H 3400 4100 60 0000 C CNN
+F 3 "" H 3400 4100 60 0000 C CNN
+ 1 3400 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U8
+U 1 1 69A5F99F
+P 2800 4200
+F 0 "U8" H 2800 4700 60 0000 C CNN
+F 1 "plot_v1" H 3000 4550 60 0000 C CNN
+F 2 "" H 2800 4200 60 0000 C CNN
+F 3 "" H 2800 4200 60 0000 C CNN
+ 1 2800 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U20
+U 1 1 69A62650
+P 9800 1200
+F 0 "U20" H 9800 1700 60 0000 C CNN
+F 1 "plot_v1" H 10000 1550 60 0000 C CNN
+F 2 "" H 9800 1200 60 0000 C CNN
+F 3 "" H 9800 1200 60 0000 C CNN
+ 1 9800 1200
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U21
+U 1 1 69A626E7
+P 9800 1500
+F 0 "U21" H 9800 2000 60 0000 C CNN
+F 1 "plot_v1" H 10000 1850 60 0000 C CNN
+F 2 "" H 9800 1500 60 0000 C CNN
+F 3 "" H 9800 1500 60 0000 C CNN
+ 1 9800 1500
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U22
+U 1 1 69A62780
+P 9800 1850
+F 0 "U22" H 9800 2350 60 0000 C CNN
+F 1 "plot_v1" H 10000 2200 60 0000 C CNN
+F 2 "" H 9800 1850 60 0000 C CNN
+F 3 "" H 9800 1850 60 0000 C CNN
+ 1 9800 1850
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U23
+U 1 1 69A6283E
+P 9800 2150
+F 0 "U23" H 9800 2650 60 0000 C CNN
+F 1 "plot_v1" H 10000 2500 60 0000 C CNN
+F 2 "" H 9800 2150 60 0000 C CNN
+F 3 "" H 9800 2150 60 0000 C CNN
+ 1 9800 2150
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U24
+U 1 1 69A62A55
+P 9850 2400
+F 0 "U24" H 9850 2900 60 0000 C CNN
+F 1 "plot_v1" H 10050 2750 60 0000 C CNN
+F 2 "" H 9850 2400 60 0000 C CNN
+F 3 "" H 9850 2400 60 0000 C CNN
+ 1 9850 2400
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U25
+U 1 1 69A62A5C
+P 9850 2700
+F 0 "U25" H 9850 3200 60 0000 C CNN
+F 1 "plot_v1" H 10050 3050 60 0000 C CNN
+F 2 "" H 9850 2700 60 0000 C CNN
+F 3 "" H 9850 2700 60 0000 C CNN
+ 1 9850 2700
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U26
+U 1 1 69A62A63
+P 9850 3050
+F 0 "U26" H 9850 3550 60 0000 C CNN
+F 1 "plot_v1" H 10050 3400 60 0000 C CNN
+F 2 "" H 9850 3050 60 0000 C CNN
+F 3 "" H 9850 3050 60 0000 C CNN
+ 1 9850 3050
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U27
+U 1 1 69A62A6A
+P 9850 3350
+F 0 "U27" H 9850 3850 60 0000 C CNN
+F 1 "plot_v1" H 10050 3700 60 0000 C CNN
+F 2 "" H 9850 3350 60 0000 C CNN
+F 3 "" H 9850 3350 60 0000 C CNN
+ 1 9850 3350
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U28
+U 1 1 69A62B43
+P 9900 3850
+F 0 "U28" H 9900 4350 60 0000 C CNN
+F 1 "plot_v1" H 10100 4200 60 0000 C CNN
+F 2 "" H 9900 3850 60 0000 C CNN
+F 3 "" H 9900 3850 60 0000 C CNN
+ 1 9900 3850
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U29
+U 1 1 69A62B4A
+P 9900 4150
+F 0 "U29" H 9900 4650 60 0000 C CNN
+F 1 "plot_v1" H 10100 4500 60 0000 C CNN
+F 2 "" H 9900 4150 60 0000 C CNN
+F 3 "" H 9900 4150 60 0000 C CNN
+ 1 9900 4150
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 6800 4000 6800 3650
+Wire Wire Line
+ 6800 3650 6650 3650
+Wire Wire Line
+ 6650 3750 6750 3750
+Wire Wire Line
+ 6750 3750 6750 4100
+Wire Wire Line
+ 6750 4100 6800 4100
+Wire Wire Line
+ 4600 2100 5250 2100
+Wire Wire Line
+ 5250 2100 5250 2850
+Wire Wire Line
+ 4600 2200 5150 2200
+Wire Wire Line
+ 5150 2200 5150 2950
+Wire Wire Line
+ 5150 2950 5250 2950
+Wire Wire Line
+ 4600 2300 5100 2300
+Wire Wire Line
+ 5100 2300 5100 3050
+Wire Wire Line
+ 5100 3050 5250 3050
+Wire Wire Line
+ 4600 2400 5050 2400
+Wire Wire Line
+ 5050 2400 5050 3150
+Wire Wire Line
+ 5050 3150 5250 3150
+Wire Wire Line
+ 4600 2500 5000 2500
+Wire Wire Line
+ 5000 2500 5000 3250
+Wire Wire Line
+ 5000 3250 5250 3250
+Wire Wire Line
+ 2000 1450 3450 1450
+Wire Wire Line
+ 3450 1450 3450 2100
+Wire Wire Line
+ 2000 1900 3400 1900
+Wire Wire Line
+ 3400 1900 3400 2200
+Wire Wire Line
+ 3400 2200 3450 2200
+Wire Wire Line
+ 2000 2350 2300 2350
+Wire Wire Line
+ 2300 2350 2300 2300
+Wire Wire Line
+ 2300 2300 3450 2300
+Wire Wire Line
+ 1950 2750 1950 2400
+Wire Wire Line
+ 1950 2400 3450 2400
+Wire Wire Line
+ 1950 3100 2050 3100
+Wire Wire Line
+ 2050 3100 2050 2500
+Wire Wire Line
+ 2050 2500 3450 2500
+Wire Wire Line
+ 1950 3700 1950 3300
+Wire Wire Line
+ 1950 3300 4100 3300
+Wire Wire Line
+ 4100 3300 4100 3350
+Wire Wire Line
+ 1950 4150 2100 4150
+Wire Wire Line
+ 2100 4150 2100 3450
+Wire Wire Line
+ 2100 3450 4100 3450
+Wire Wire Line
+ 1900 4550 2150 4550
+Wire Wire Line
+ 2150 4550 2150 3550
+Wire Wire Line
+ 2150 3550 4100 3550
+Wire Wire Line
+ 1900 4900 2250 4900
+Wire Wire Line
+ 2250 4900 2250 3650
+Wire Wire Line
+ 2250 3650 4100 3650
+Wire Wire Line
+ 1950 5450 2350 5450
+Wire Wire Line
+ 2350 5450 2350 3750
+Wire Wire Line
+ 2350 3750 4100 3750
+Wire Wire Line
+ 1950 5900 2400 5900
+Wire Wire Line
+ 2400 5900 2400 3850
+Wire Wire Line
+ 2400 3850 4100 3850
+Wire Wire Line
+ 1900 6300 2500 6300
+Wire Wire Line
+ 2500 6300 2500 3950
+Wire Wire Line
+ 2500 3950 4100 3950
+Wire Wire Line
+ 1950 6650 2650 6650
+Wire Wire Line
+ 2650 6650 2650 4050
+Wire Wire Line
+ 2650 4050 4100 4050
+Wire Wire Line
+ 1100 1450 750 1450
+Wire Wire Line
+ 950 1200 950 1450
+Connection ~ 950 1450
+Wire Wire Line
+ 2400 1300 2400 1350
+Wire Wire Line
+ 2400 1350 2550 1350
+Wire Wire Line
+ 2550 1350 2550 1450
+Connection ~ 2550 1450
+Wire Wire Line
+ 2200 1750 2200 1900
+Connection ~ 2200 1900
+Wire Wire Line
+ 2400 2100 2400 2300
+Connection ~ 2400 2300
+Wire Wire Line
+ 2550 2350 2550 2400
+Connection ~ 2550 2400
+Wire Wire Line
+ 2650 2450 2650 2500
+Connection ~ 2650 2500
+Wire Wire Line
+ 3000 3150 3000 3300
+Connection ~ 3000 3300
+Wire Wire Line
+ 2700 3400 2700 3450
+Connection ~ 2700 3450
+Wire Wire Line
+ 2550 3700 2550 3750
+Connection ~ 2550 3750
+Wire Wire Line
+ 2950 3600 2950 3650
+Connection ~ 2950 3650
+Wire Wire Line
+ 3300 3500 3300 3550
+Connection ~ 3300 3550
+Wire Wire Line
+ 3150 3800 3150 3850
+Connection ~ 3150 3850
+Wire Wire Line
+ 3400 3900 3400 3950
+Connection ~ 3400 3950
+Wire Wire Line
+ 2800 4000 2800 4050
+Connection ~ 2800 4050
+Wire Wire Line
+ 3550 3700 3550 3750
+Connection ~ 3550 3750
+Wire Wire Line
+ 7800 2850 7800 1200
+Wire Wire Line
+ 7800 1200 10000 1200
+Wire Wire Line
+ 7800 2950 7950 2950
+Wire Wire Line
+ 7950 2950 7950 1500
+Wire Wire Line
+ 7950 1500 10000 1500
+Wire Wire Line
+ 7800 3050 8050 3050
+Wire Wire Line
+ 8050 3050 8050 1850
+Wire Wire Line
+ 8050 1850 10000 1850
+Wire Wire Line
+ 7800 3150 8100 3150
+Wire Wire Line
+ 8100 3150 8100 2150
+Wire Wire Line
+ 8100 2150 10000 2150
+Wire Wire Line
+ 7800 3250 8200 3250
+Wire Wire Line
+ 8200 3250 8200 2400
+Wire Wire Line
+ 8200 2400 10050 2400
+Wire Wire Line
+ 7800 3350 8350 3350
+Wire Wire Line
+ 8350 3350 8350 2700
+Wire Wire Line
+ 8350 2700 10050 2700
+Wire Wire Line
+ 7800 3450 8500 3450
+Wire Wire Line
+ 8500 3450 8500 3050
+Wire Wire Line
+ 8500 3050 10050 3050
+Wire Wire Line
+ 7800 3550 8650 3550
+Wire Wire Line
+ 8650 3550 8650 3350
+Wire Wire Line
+ 8650 3350 10050 3350
+Wire Wire Line
+ 7800 4000 10100 4000
+Wire Wire Line
+ 10100 4000 10100 3850
+Wire Wire Line
+ 7800 4100 10100 4100
+Wire Wire Line
+ 10100 4100 10100 4150
+Text GLabel 8400 1200 1 60 Input ~ 0
+q7
+Text GLabel 8550 1500 1 60 Input ~ 0
+q6
+Text GLabel 8700 1850 1 60 Input ~ 0
+q5
+Text GLabel 9050 2150 1 60 Input ~ 0
+q4
+Text GLabel 8650 2400 1 60 Input ~ 0
+q3
+Text GLabel 9150 2700 1 60 Input ~ 0
+q2
+Text GLabel 9550 3050 1 60 Input ~ 0
+q1
+Text GLabel 9750 3350 1 60 Input ~ 0
+q0
+Text GLabel 9450 4000 1 60 Input ~ 0
+full0
+Text GLabel 9200 4100 1 60 Input ~ 0
+empty0
+$EndSCHEMATC
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.v b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.v
new file mode 100644
index 000000000..587278b5b
--- /dev/null
+++ b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo.v
@@ -0,0 +1,100 @@
+module asynchronous_fifo (
+ input wclk,
+ input rclk,
+ input rst,
+ input wr_en,
+ input rd_en,
+ input [7:0] din,
+ output reg [7:0] dout,
+ output full,
+ output empty
+);
+
+localparam ADDR_WIDTH = 3;
+localparam DEPTH = 8;
+
+reg [7:0] mem [0:7];
+
+reg [3:0] wptr_bin, rptr_bin;
+reg [3:0] wptr_gray, rptr_gray;
+
+reg [3:0] wptr_gray_sync1, wptr_gray_sync2;
+reg [3:0] rptr_gray_sync1, rptr_gray_sync2;
+
+wire [3:0] wptr_bin_next;
+wire [3:0] wptr_gray_next;
+wire [3:0] rptr_bin_next;
+wire [3:0] rptr_gray_next;
+
+assign wptr_bin_next = wptr_bin + (wr_en & ~full);
+assign wptr_gray_next = (wptr_bin_next >> 1) ^ wptr_bin_next;
+
+assign rptr_bin_next = rptr_bin + (rd_en & ~empty);
+assign rptr_gray_next = (rptr_bin_next >> 1) ^ rptr_bin_next;
+
+initial begin
+ wptr_bin = 0;
+ rptr_bin = 0;
+ wptr_gray = 0;
+ rptr_gray = 0;
+ dout = 0;
+end
+
+// WRITE DOMAIN
+always @(posedge wclk) begin
+ if (rst) begin
+ wptr_bin <= 0;
+ wptr_gray <= 0;
+ end else begin
+ wptr_bin <= wptr_bin_next;
+ wptr_gray <= wptr_gray_next;
+
+ if (wr_en && !full)
+ mem[wptr_bin[2:0]] <= din;
+ end
+end
+
+// READ DOMAIN
+always @(posedge rclk) begin
+ if (rst) begin
+ rptr_bin <= 0;
+ rptr_gray <= 0;
+ dout <= 0;
+ end else begin
+ rptr_bin <= rptr_bin_next;
+ rptr_gray <= rptr_gray_next;
+
+ if (rd_en && !empty)
+ dout <= mem[rptr_bin[2:0]];
+ end
+end
+
+// Synchronizers
+always @(posedge wclk) begin
+ if (rst) begin
+ rptr_gray_sync1 <= 0;
+ rptr_gray_sync2 <= 0;
+ end else begin
+ rptr_gray_sync1 <= rptr_gray;
+ rptr_gray_sync2 <= rptr_gray_sync1;
+ end
+end
+
+always @(posedge rclk) begin
+ if (rst) begin
+ wptr_gray_sync1 <= 0;
+ wptr_gray_sync2 <= 0;
+ end else begin
+ wptr_gray_sync1 <= wptr_gray;
+ wptr_gray_sync2 <= wptr_gray_sync1;
+ end
+end
+
+assign empty = (rptr_gray == wptr_gray_sync2);
+
+assign full =
+ (wptr_gray_next ==
+ {~rptr_gray_sync2[3:2],
+ rptr_gray_sync2[1:0]});
+
+endmodule
\ No newline at end of file
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo_Previous_Values.xml b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo_Previous_Values.xml
new file mode 100644
index 000000000..de6a11945
--- /dev/null
+++ b/fossee/asynchronous_fifo/asynchronous_fifo/asynchronous_fifo_Previous_Values.xml
@@ -0,0 +1 @@
+pulsepulsepulsepulsepulsepulsepulsepulsepulsepulsepulse010.01ns0.001ns0.001ns10ns20nspulsepulseadc_bridgeadc_bridgedac_bridgedac_bridgeasynchronous_fifoadc_bridgeasynchronous_fifoadc_bridgedac_bridgedac_bridgetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01450nsnsns
\ No newline at end of file
diff --git a/fossee/asynchronous_fifo/asynchronous_fifo_waveforms.png b/fossee/asynchronous_fifo/asynchronous_fifo_waveforms.png
new file mode 100644
index 000000000..579da0de1
Binary files /dev/null and b/fossee/asynchronous_fifo/asynchronous_fifo_waveforms.png differ
diff --git a/fossee/booth_wallace/booth_flow_digran.png b/fossee/booth_wallace/booth_flow_digran.png
new file mode 100644
index 000000000..6e8e374a9
Binary files /dev/null and b/fossee/booth_wallace/booth_flow_digran.png differ
diff --git a/fossee/booth_wallace/booth_vivado.png b/fossee/booth_wallace/booth_vivado.png
new file mode 100644
index 000000000..2db28aa45
Binary files /dev/null and b/fossee/booth_wallace/booth_vivado.png differ
diff --git a/fossee/booth_wallace/booth_wallace_cmd.png b/fossee/booth_wallace/booth_wallace_cmd.png
new file mode 100644
index 000000000..0e19272ac
Binary files /dev/null and b/fossee/booth_wallace/booth_wallace_cmd.png differ
diff --git a/fossee/booth_wallace/booth_wallace_ip_wave.png b/fossee/booth_wallace/booth_wallace_ip_wave.png
new file mode 100644
index 000000000..097c35dcb
Binary files /dev/null and b/fossee/booth_wallace/booth_wallace_ip_wave.png differ
diff --git a/fossee/booth_wallace/booth_wallace_module.png b/fossee/booth_wallace/booth_wallace_module.png
new file mode 100644
index 000000000..bbd9ee73c
Binary files /dev/null and b/fossee/booth_wallace/booth_wallace_module.png differ
diff --git a/fossee/booth_wallace/booth_wallace_mul/2.5) b/fossee/booth_wallace/booth_wallace_mul/2.5)
new file mode 100644
index 000000000..e69de29bb
diff --git a/fossee/booth_wallace/booth_wallace_mul/2.5, b/fossee/booth_wallace/booth_wallace_mul/2.5,
new file mode 100644
index 000000000..e69de29bb
diff --git a/fossee/booth_wallace/booth_wallace_mul/analysis b/fossee/booth_wallace/booth_wallace_mul/analysis
new file mode 100644
index 000000000..bba331247
--- /dev/null
+++ b/fossee/booth_wallace/booth_wallace_mul/analysis
@@ -0,0 +1 @@
+.tran 1e-09 100e-09 0e-09
\ No newline at end of file
diff --git a/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul-cache.lib b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul-cache.lib
new file mode 100644
index 000000000..3bfcf8654
--- /dev/null
+++ b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul-cache.lib
@@ -0,0 +1,144 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# booth_wallace_mul
+#
+DEF booth_wallace_mul U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "booth_wallace_mul" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1000 0 1 0 N
+X A3 1 2150 1900 200 R 50 50 1 1 I
+X A2 2 2150 1800 200 R 50 50 1 1 I
+X A1 3 2150 1700 200 R 50 50 1 1 I
+X A0 4 2150 1600 200 R 50 50 1 1 I
+X B3 5 2150 1500 200 R 50 50 1 1 I
+X B2 6 2150 1400 200 R 50 50 1 1 I
+X B1 7 2150 1300 200 R 50 50 1 1 I
+X B0 8 2150 1200 200 R 50 50 1 1 I
+X P7 9 3550 1900 200 L 50 50 1 1 O
+X P6 10 3550 1800 200 L 50 50 1 1 O
+X P5 11 3550 1700 200 L 50 50 1 1 O
+X P4 12 3550 1600 200 L 50 50 1 1 O
+X P3 13 3550 1500 200 L 50 50 1 1 O
+X P2 14 3550 1400 200 L 50 50 1 1 O
+X P1 15 3550 1300 200 L 50 50 1 1 O
+X P0 16 3550 1200 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.cir b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.cir
new file mode 100644
index 000000000..a5aa5fd58
--- /dev/null
+++ b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.cir
@@ -0,0 +1,37 @@
+* C:\Users\VLSI\eSim-Workspace\booth_wallace_mul\booth_wallace_mul.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/03/2026 17:20:33
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U9 Net-_U10-Pad9_ Net-_U10-Pad10_ Net-_U10-Pad11_ Net-_U10-Pad12_ Net-_U10-Pad13_ Net-_U10-Pad14_ Net-_U10-Pad15_ Net-_U10-Pad16_ Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ booth_wallace_mul
+v6 a3 GND DC
+v7 a2 GND DC
+v8 a1 GND DC
+v1 a0 GND DC
+v2 b3 GND DC
+v3 b2 GND DC
+v4 b1 GND DC
+v5 b0 GND DC
+U10 a3 a2 a1 a0 b3 b2 b1 b0 Net-_U10-Pad9_ Net-_U10-Pad10_ Net-_U10-Pad11_ Net-_U10-Pad12_ Net-_U10-Pad13_ Net-_U10-Pad14_ Net-_U10-Pad15_ Net-_U10-Pad16_ adc_bridge_8
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ p7 p6 p5 p4 p3 p2 p1 p0 dac_bridge_8
+U6 a3 plot_v1
+U5 a2 plot_v1
+U2 a1 plot_v1
+U1 a0 plot_v1
+U7 b3 plot_v1
+U8 b2 plot_v1
+U4 b1 plot_v1
+U3 b0 plot_v1
+U12 p7 plot_v1
+U13 p6 plot_v1
+U14 p5 plot_v1
+U15 p4 plot_v1
+U16 p3 plot_v1
+U17 p2 plot_v1
+U18 p1 plot_v1
+U19 p0 plot_v1
+
+.end
diff --git a/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.cir.out b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.cir.out
new file mode 100644
index 000000000..266effaeb
--- /dev/null
+++ b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.cir.out
@@ -0,0 +1,54 @@
+* c:\users\vlsi\esim-workspace\booth_wallace_mul\booth_wallace_mul.cir
+
+* u9 net-_u10-pad9_ net-_u10-pad10_ net-_u10-pad11_ net-_u10-pad12_ net-_u10-pad13_ net-_u10-pad14_ net-_u10-pad15_ net-_u10-pad16_ net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ booth_wallace_mul
+v6 a3 gnd dc 0
+v7 a2 gnd dc 5
+v8 a1 gnd dc 5
+v1 a0 gnd dc 5
+v2 b3 gnd dc 0
+v3 b2 gnd dc 5
+v4 b1 gnd dc 5
+v5 b0 gnd dc 5
+* u10 a3 a2 a1 a0 b3 b2 b1 b0 net-_u10-pad9_ net-_u10-pad10_ net-_u10-pad11_ net-_u10-pad12_ net-_u10-pad13_ net-_u10-pad14_ net-_u10-pad15_ net-_u10-pad16_ adc_bridge_8
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ p7 p6 p5 p4 p3 p2 p1 p0 dac_bridge_8
+* u6 a3 plot_v1
+* u5 a2 plot_v1
+* u2 a1 plot_v1
+* u1 a0 plot_v1
+* u7 b3 plot_v1
+* u8 b2 plot_v1
+* u4 b1 plot_v1
+* u3 b0 plot_v1
+* u12 p7 plot_v1
+* u13 p6 plot_v1
+* u14 p5 plot_v1
+* u15 p4 plot_v1
+* u16 p3 plot_v1
+* u17 p2 plot_v1
+* u18 p1 plot_v1
+* u19 p0 plot_v1
+a1 [net-_u10-pad9_ net-_u10-pad10_ net-_u10-pad11_ net-_u10-pad12_ ] [net-_u10-pad13_ net-_u10-pad14_ net-_u10-pad15_ net-_u10-pad16_ ] [net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ ] u9
+a2 [a3 a2 a1 a0 b3 b2 b1 b0 ] [net-_u10-pad9_ net-_u10-pad10_ net-_u10-pad11_ net-_u10-pad12_ net-_u10-pad13_ net-_u10-pad14_ net-_u10-pad15_ net-_u10-pad16_ ] u10
+a3 [net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ ] [p7 p6 p5 p4 p3 p2 p1 p0 ] u11
+* Schematic Name: booth_wallace_mul, NgSpice Name: booth_wallace_mul
+.model u9 booth_wallace_mul(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 1e-09 100e-09 0e-09
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+
+set xbrushwidth=2
+plot v(a0)+6 v(a1)+12 v(a2)+18 v(a3)+24 v(b0)+30 v(b1)+36 v(b2)+42 v(b3)+48
+plot v(p0)+6 v(p1)+12 v(p2)+18 v(p3)+24 v(p4)+30 v(p5)+36 v(p6)+42 v(p7)+48
+
+
+
+.endc
+.end
diff --git a/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.pro b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.proj b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.proj
new file mode 100644
index 000000000..07b489712
--- /dev/null
+++ b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.proj
@@ -0,0 +1 @@
+schematicFile booth_wallace_mul.sch
diff --git a/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.sch b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.sch
new file mode 100644
index 000000000..5b6ee07a4
--- /dev/null
+++ b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.sch
@@ -0,0 +1,621 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L booth_wallace_mul U9
+U 1 1 69A6C8EA
+P 3350 4650
+F 0 "U9" H 6200 6450 60 0000 C CNN
+F 1 "booth_wallace_mul" H 6200 6650 60 0000 C CNN
+F 2 "" H 6200 6600 60 0000 C CNN
+F 3 "" H 6200 6600 60 0000 C CNN
+ 1 3350 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v6
+U 1 1 69A6C92E
+P 1900 2000
+F 0 "v6" H 1700 2100 60 0000 C CNN
+F 1 "DC" H 1700 1950 60 0000 C CNN
+F 2 "R1" H 1600 2000 60 0000 C CNN
+F 3 "" H 1900 2000 60 0000 C CNN
+ 1 1900 2000
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v7
+U 1 1 69A6C983
+P 1900 2400
+F 0 "v7" H 1700 2500 60 0000 C CNN
+F 1 "DC" H 1700 2350 60 0000 C CNN
+F 2 "R1" H 1600 2400 60 0000 C CNN
+F 3 "" H 1900 2400 60 0000 C CNN
+ 1 1900 2400
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v8
+U 1 1 69A6C9C0
+P 1900 2800
+F 0 "v8" H 1700 2900 60 0000 C CNN
+F 1 "DC" H 1700 2750 60 0000 C CNN
+F 2 "R1" H 1600 2800 60 0000 C CNN
+F 3 "" H 1900 2800 60 0000 C CNN
+ 1 1900 2800
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v1
+U 1 1 69A6CAF6
+P 1850 3150
+F 0 "v1" H 1650 3250 60 0000 C CNN
+F 1 "DC" H 1650 3100 60 0000 C CNN
+F 2 "R1" H 1550 3150 60 0000 C CNN
+F 3 "" H 1850 3150 60 0000 C CNN
+ 1 1850 3150
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v2
+U 1 1 69A6CAFD
+P 1850 4050
+F 0 "v2" H 1650 4150 60 0000 C CNN
+F 1 "DC" H 1650 4000 60 0000 C CNN
+F 2 "R1" H 1550 4050 60 0000 C CNN
+F 3 "" H 1850 4050 60 0000 C CNN
+ 1 1850 4050
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v3
+U 1 1 69A6CB04
+P 1850 4450
+F 0 "v3" H 1650 4550 60 0000 C CNN
+F 1 "DC" H 1650 4400 60 0000 C CNN
+F 2 "R1" H 1550 4450 60 0000 C CNN
+F 3 "" H 1850 4450 60 0000 C CNN
+ 1 1850 4450
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v4
+U 1 1 69A6CBCA
+P 1850 4800
+F 0 "v4" H 1650 4900 60 0000 C CNN
+F 1 "DC" H 1650 4750 60 0000 C CNN
+F 2 "R1" H 1550 4800 60 0000 C CNN
+F 3 "" H 1850 4800 60 0000 C CNN
+ 1 1850 4800
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v5
+U 1 1 69A6CBD1
+P 1850 5200
+F 0 "v5" H 1650 5300 60 0000 C CNN
+F 1 "DC" H 1650 5150 60 0000 C CNN
+F 2 "R1" H 1550 5200 60 0000 C CNN
+F 3 "" H 1850 5200 60 0000 C CNN
+ 1 1850 5200
+ 0 1 1 0
+$EndComp
+$Comp
+L adc_bridge_8 U10
+U 1 1 69A6CBE3
+P 4950 2800
+F 0 "U10" H 4950 2800 60 0000 C CNN
+F 1 "adc_bridge_8" H 4950 2950 60 0000 C CNN
+F 2 "" H 4950 2800 60 0000 C CNN
+F 3 "" H 4950 2800 60 0000 C CNN
+ 1 4950 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_8 U11
+U 1 1 69A6CC56
+P 7500 2800
+F 0 "U11" H 7500 2800 60 0000 C CNN
+F 1 "dac_bridge_8" H 7500 2950 60 0000 C CNN
+F 2 "" H 7500 2800 60 0000 C CNN
+F 3 "" H 7500 2800 60 0000 C CNN
+ 1 7500 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR1
+U 1 1 69A6CCC3
+P 900 2000
+F 0 "#PWR1" H 900 1750 50 0001 C CNN
+F 1 "GND" H 900 1850 50 0000 C CNN
+F 2 "" H 900 2000 50 0001 C CNN
+F 3 "" H 900 2000 50 0001 C CNN
+ 1 900 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR7
+U 1 1 69A6CCED
+P 1450 2400
+F 0 "#PWR7" H 1450 2150 50 0001 C CNN
+F 1 "GND" H 1450 2250 50 0000 C CNN
+F 2 "" H 1450 2400 50 0001 C CNN
+F 3 "" H 1450 2400 50 0001 C CNN
+ 1 1450 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR8
+U 1 1 69A6CDD5
+P 1450 2800
+F 0 "#PWR8" H 1450 2550 50 0001 C CNN
+F 1 "GND" H 1450 2650 50 0000 C CNN
+F 2 "" H 1450 2800 50 0001 C CNN
+F 3 "" H 1450 2800 50 0001 C CNN
+ 1 1450 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR2
+U 1 1 69A6D21D
+P 1400 3150
+F 0 "#PWR2" H 1400 2900 50 0001 C CNN
+F 1 "GND" H 1400 3000 50 0000 C CNN
+F 2 "" H 1400 3150 50 0001 C CNN
+F 3 "" H 1400 3150 50 0001 C CNN
+ 1 1400 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR3
+U 1 1 69A6D247
+P 1400 4050
+F 0 "#PWR3" H 1400 3800 50 0001 C CNN
+F 1 "GND" H 1400 3900 50 0000 C CNN
+F 2 "" H 1400 4050 50 0001 C CNN
+F 3 "" H 1400 4050 50 0001 C CNN
+ 1 1400 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR4
+U 1 1 69A6D271
+P 1400 4450
+F 0 "#PWR4" H 1400 4200 50 0001 C CNN
+F 1 "GND" H 1400 4300 50 0000 C CNN
+F 2 "" H 1400 4450 50 0001 C CNN
+F 3 "" H 1400 4450 50 0001 C CNN
+ 1 1400 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR5
+U 1 1 69A6D29B
+P 1400 4800
+F 0 "#PWR5" H 1400 4550 50 0001 C CNN
+F 1 "GND" H 1400 4650 50 0000 C CNN
+F 2 "" H 1400 4800 50 0001 C CNN
+F 3 "" H 1400 4800 50 0001 C CNN
+ 1 1400 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR6
+U 1 1 69A6D2C5
+P 1400 5200
+F 0 "#PWR6" H 1400 4950 50 0001 C CNN
+F 1 "GND" H 1400 5050 50 0000 C CNN
+F 2 "" H 1400 5200 50 0001 C CNN
+F 3 "" H 1400 5200 50 0001 C CNN
+ 1 1400 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG1
+U 1 1 69A6D5BC
+P 1200 1800
+F 0 "#FLG1" H 1200 1875 50 0001 C CNN
+F 1 "PWR_FLAG" H 1200 1950 50 0000 C CNN
+F 2 "" H 1200 1800 50 0001 C CNN
+F 3 "" H 1200 1800 50 0001 C CNN
+ 1 1200 1800
+ 1 0 0 -1
+$EndComp
+Text GLabel 3900 3450 1 60 Input ~ 0
+b0
+Text GLabel 3700 3350 1 60 Input ~ 0
+b1
+Text GLabel 4100 3250 1 60 Input ~ 0
+b2
+Text GLabel 3900 3150 1 60 Input ~ 0
+b3
+Text GLabel 4250 3050 1 60 Input ~ 0
+a0
+Text GLabel 3850 2800 1 60 Input ~ 0
+a1
+Text GLabel 3900 2400 1 60 Input ~ 0
+a2
+Text GLabel 4100 2000 1 60 Input ~ 0
+a3
+$Comp
+L plot_v1 U6
+U 1 1 69A6DE50
+P 3000 2050
+F 0 "U6" H 3000 2550 60 0000 C CNN
+F 1 "plot_v1" H 3200 2400 60 0000 C CNN
+F 2 "" H 3000 2050 60 0000 C CNN
+F 3 "" H 3000 2050 60 0000 C CNN
+ 1 3000 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 69A6DE93
+P 2800 2400
+F 0 "U5" H 2800 2900 60 0000 C CNN
+F 1 "plot_v1" H 3000 2750 60 0000 C CNN
+F 2 "" H 2800 2400 60 0000 C CNN
+F 3 "" H 2800 2400 60 0000 C CNN
+ 1 2800 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U2
+U 1 1 69A6DED2
+P 2600 2700
+F 0 "U2" H 2600 3200 60 0000 C CNN
+F 1 "plot_v1" H 2800 3050 60 0000 C CNN
+F 2 "" H 2600 2700 60 0000 C CNN
+F 3 "" H 2600 2700 60 0000 C CNN
+ 1 2600 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 69A6DF0F
+P 2450 3100
+F 0 "U1" H 2450 3600 60 0000 C CNN
+F 1 "plot_v1" H 2650 3450 60 0000 C CNN
+F 2 "" H 2450 3100 60 0000 C CNN
+F 3 "" H 2450 3100 60 0000 C CNN
+ 1 2450 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U7
+U 1 1 69A6DF52
+P 3000 3350
+F 0 "U7" H 3000 3850 60 0000 C CNN
+F 1 "plot_v1" H 3200 3700 60 0000 C CNN
+F 2 "" H 3000 3350 60 0000 C CNN
+F 3 "" H 3000 3350 60 0000 C CNN
+ 1 3000 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U8
+U 1 1 69A6DF9B
+P 3200 3550
+F 0 "U8" H 3200 4050 60 0000 C CNN
+F 1 "plot_v1" H 3400 3900 60 0000 C CNN
+F 2 "" H 3200 3550 60 0000 C CNN
+F 3 "" H 3200 3550 60 0000 C CNN
+ 1 3200 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 69A6DFE2
+P 2750 3650
+F 0 "U4" H 2750 4150 60 0000 C CNN
+F 1 "plot_v1" H 2950 4000 60 0000 C CNN
+F 2 "" H 2750 3650 60 0000 C CNN
+F 3 "" H 2750 3650 60 0000 C CNN
+ 1 2750 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U3
+U 1 1 69A6E02B
+P 2650 3900
+F 0 "U3" H 2650 4400 60 0000 C CNN
+F 1 "plot_v1" H 2850 4250 60 0000 C CNN
+F 2 "" H 2650 3900 60 0000 C CNN
+F 3 "" H 2650 3900 60 0000 C CNN
+ 1 2650 3900
+ 1 0 0 -1
+$EndComp
+Connection ~ 2700 3700
+Wire Wire Line
+ 2650 3700 2700 3700
+Connection ~ 2750 3500
+Wire Wire Line
+ 2750 3450 2750 3500
+Connection ~ 3200 3400
+Wire Wire Line
+ 3200 3350 3200 3400
+Connection ~ 3000 3300
+Wire Wire Line
+ 3000 3150 3000 3300
+Connection ~ 2500 3150
+Wire Wire Line
+ 2450 3150 2500 3150
+Wire Wire Line
+ 2450 2900 2450 3150
+Connection ~ 2650 2800
+Wire Wire Line
+ 2600 2800 2650 2800
+Wire Wire Line
+ 2600 2500 2600 2800
+Connection ~ 2800 2400
+Wire Wire Line
+ 2800 2200 2800 2400
+Connection ~ 3000 2000
+Wire Wire Line
+ 3000 1850 3000 2000
+Wire Wire Line
+ 3600 3450 4350 3450
+Wire Wire Line
+ 3600 3600 3600 3450
+Wire Wire Line
+ 2700 3600 3600 3600
+Wire Wire Line
+ 2700 5200 2700 3600
+Wire Wire Line
+ 2300 5200 2700 5200
+Wire Wire Line
+ 3450 3350 4350 3350
+Wire Wire Line
+ 3450 3500 3450 3350
+Wire Wire Line
+ 2550 3500 3450 3500
+Wire Wire Line
+ 2550 4800 2550 3500
+Wire Wire Line
+ 2300 4800 2550 4800
+Wire Wire Line
+ 3300 3250 4350 3250
+Wire Wire Line
+ 3300 3400 3300 3250
+Wire Wire Line
+ 2450 3400 3300 3400
+Wire Wire Line
+ 2450 4450 2450 3400
+Wire Wire Line
+ 2300 4450 2450 4450
+Wire Wire Line
+ 3250 3150 4350 3150
+Wire Wire Line
+ 3250 3300 3250 3150
+Wire Wire Line
+ 2300 3300 3250 3300
+Wire Wire Line
+ 2300 4050 2300 3300
+Wire Wire Line
+ 2650 3050 4350 3050
+Wire Wire Line
+ 2650 3150 2650 3050
+Wire Wire Line
+ 2300 3150 2650 3150
+Wire Wire Line
+ 3900 2950 4350 2950
+Wire Wire Line
+ 3900 2800 3900 2950
+Wire Wire Line
+ 2350 2800 3900 2800
+Wire Wire Line
+ 4350 2000 4350 2750
+Wire Wire Line
+ 2350 2000 4350 2000
+Wire Wire Line
+ 3950 2850 4350 2850
+Wire Wire Line
+ 3950 2400 3950 2850
+Wire Wire Line
+ 2350 2400 3950 2400
+Wire Wire Line
+ 900 2000 1450 2000
+Wire Wire Line
+ 1200 1800 1200 2000
+Connection ~ 1200 2000
+$Comp
+L plot_v1 U12
+U 1 1 69A6F4E5
+P 9800 1200
+F 0 "U12" H 9800 1700 60 0000 C CNN
+F 1 "plot_v1" H 10000 1550 60 0000 C CNN
+F 2 "" H 9800 1200 60 0000 C CNN
+F 3 "" H 9800 1200 60 0000 C CNN
+ 1 9800 1200
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U13
+U 1 1 69A6F54A
+P 9850 1600
+F 0 "U13" H 9850 2100 60 0000 C CNN
+F 1 "plot_v1" H 10050 1950 60 0000 C CNN
+F 2 "" H 9850 1600 60 0000 C CNN
+F 3 "" H 9850 1600 60 0000 C CNN
+ 1 9850 1600
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U14
+U 1 1 69A6F5A9
+P 9850 1950
+F 0 "U14" H 9850 2450 60 0000 C CNN
+F 1 "plot_v1" H 10050 2300 60 0000 C CNN
+F 2 "" H 9850 1950 60 0000 C CNN
+F 3 "" H 9850 1950 60 0000 C CNN
+ 1 9850 1950
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U15
+U 1 1 69A6F600
+P 9900 2300
+F 0 "U15" H 9900 2800 60 0000 C CNN
+F 1 "plot_v1" H 10100 2650 60 0000 C CNN
+F 2 "" H 9900 2300 60 0000 C CNN
+F 3 "" H 9900 2300 60 0000 C CNN
+ 1 9900 2300
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U16
+U 1 1 69A6F70C
+P 9900 2800
+F 0 "U16" H 9900 3300 60 0000 C CNN
+F 1 "plot_v1" H 10100 3150 60 0000 C CNN
+F 2 "" H 9900 2800 60 0000 C CNN
+F 3 "" H 9900 2800 60 0000 C CNN
+ 1 9900 2800
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U17
+U 1 1 69A6F713
+P 9950 3200
+F 0 "U17" H 9950 3700 60 0000 C CNN
+F 1 "plot_v1" H 10150 3550 60 0000 C CNN
+F 2 "" H 9950 3200 60 0000 C CNN
+F 3 "" H 9950 3200 60 0000 C CNN
+ 1 9950 3200
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U18
+U 1 1 69A6F71A
+P 9950 3550
+F 0 "U18" H 9950 4050 60 0000 C CNN
+F 1 "plot_v1" H 10150 3900 60 0000 C CNN
+F 2 "" H 9950 3550 60 0000 C CNN
+F 3 "" H 9950 3550 60 0000 C CNN
+ 1 9950 3550
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U19
+U 1 1 69A6F721
+P 10000 3900
+F 0 "U19" H 10000 4400 60 0000 C CNN
+F 1 "plot_v1" H 10200 4250 60 0000 C CNN
+F 2 "" H 10000 3900 60 0000 C CNN
+F 3 "" H 10000 3900 60 0000 C CNN
+ 1 10000 3900
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 8050 2750 8050 1200
+Wire Wire Line
+ 8050 1200 10000 1200
+Wire Wire Line
+ 8050 2850 8250 2850
+Wire Wire Line
+ 8250 2850 8250 1600
+Wire Wire Line
+ 8250 1600 10050 1600
+Wire Wire Line
+ 8050 2950 8450 2950
+Wire Wire Line
+ 8450 2950 8450 1950
+Wire Wire Line
+ 8450 1950 10050 1950
+Wire Wire Line
+ 8050 3050 8650 3050
+Wire Wire Line
+ 8650 3050 8650 2300
+Wire Wire Line
+ 8650 2300 10100 2300
+Wire Wire Line
+ 8050 3450 8050 4100
+Wire Wire Line
+ 8050 4100 10200 4100
+Wire Wire Line
+ 10200 4100 10200 3900
+Wire Wire Line
+ 8050 3150 9050 3150
+Wire Wire Line
+ 9050 3150 9050 2800
+Wire Wire Line
+ 9050 2800 10100 2800
+Wire Wire Line
+ 8050 3350 8500 3350
+Wire Wire Line
+ 8500 3350 8500 3550
+Wire Wire Line
+ 8500 3550 10150 3550
+Wire Wire Line
+ 8050 3250 10150 3250
+Wire Wire Line
+ 10150 3250 10150 3200
+Text GLabel 9250 1200 1 60 Input ~ 0
+p7
+Text GLabel 9300 1600 1 60 Input ~ 0
+p6
+Text GLabel 9550 1950 1 60 Input ~ 0
+p5
+Text GLabel 9600 2300 1 60 Input ~ 0
+p4
+Text GLabel 9600 2800 1 60 Input ~ 0
+p3
+Text GLabel 9600 3250 1 60 Input ~ 0
+p2
+Text GLabel 9450 3550 1 60 Input ~ 0
+p1
+Text GLabel 9550 4100 1 60 Input ~ 0
+p0
+$EndSCHEMATC
diff --git a/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.v b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.v
new file mode 100644
index 000000000..da05c1bc8
--- /dev/null
+++ b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul.v
@@ -0,0 +1,101 @@
+
+
+module booth_wallace_mul (
+ input [3:0] A, // 4-bit 2's complement
+ input [3:0] B, // 4-bit 2's complement
+ output [7:0] P // 8-bit 2's complement product
+);
+
+ // Treat inputs as signed internally
+ wire signed [3:0] As = A;
+ wire signed [3:0] Bs = B;
+
+ // Sign extend multiplicand
+ wire signed [7:0] A_ext = {{4{As[3]}}, As};
+ wire signed [7:0] negA = -A_ext;
+
+ // Booth radix-2 ops (no function; safest for tools)
+ wire signed [7:0] op0 =
+ ({Bs[0],1'b0} == 2'b01) ? A_ext :
+ ({Bs[0],1'b0} == 2'b10) ? negA :
+ 8'sd0;
+
+ wire signed [7:0] op1 =
+ ({Bs[1],Bs[0]} == 2'b01) ? A_ext :
+ ({Bs[1],Bs[0]} == 2'b10) ? negA :
+ 8'sd0;
+
+ wire signed [7:0] op2 =
+ ({Bs[2],Bs[1]} == 2'b01) ? A_ext :
+ ({Bs[2],Bs[1]} == 2'b10) ? negA :
+ 8'sd0;
+
+ wire signed [7:0] op3 =
+ ({Bs[3],Bs[2]} == 2'b01) ? A_ext :
+ ({Bs[3],Bs[2]} == 2'b10) ? negA :
+ 8'sd0;
+
+ // Partial products (left shifts)
+ wire [7:0] pp0 = op0 <<< 0;
+ wire [7:0] pp1 = op1 <<< 1;
+ wire [7:0] pp2 = op2 <<< 2;
+ wire [7:0] pp3 = op3 <<< 3;
+
+ // Wallace tree using CSA (2 stages for 4 rows)
+ wire [7:0] s1, c1;
+ wire [7:0] s2, c2;
+
+ csa_8bit CSA1 (.x(pp0), .y(pp1), .z(pp2), .sum(s1), .carry(c1));
+ csa_8bit CSA2 (.x(s1), .y(c1), .z(pp3), .sum(s2), .carry(c2));
+
+ // Final carry-propagate add
+ assign P = s2 + c2;
+
+endmodule
+
+
+//============================================================
+// 8-bit Carry Save Adder (3→2 compressor)
+// carry output is already shifted left by 1
+//============================================================
+module csa_8bit (
+ input [7:0] x,
+ input [7:0] y,
+ input [7:0] z,
+ output [7:0] sum,
+ output [7:0] carry
+);
+ wire [7:0] c;
+
+ genvar i;
+ generate
+ for (i=0; i<8; i=i+1) begin : CSA
+ full_adder FA (
+ .a(x[i]),
+ .b(y[i]),
+ .cin(z[i]),
+ .sum(sum[i]),
+ .cout(c[i])
+ );
+ end
+ endgenerate
+
+ assign carry[0] = 1'b0;
+ assign carry[7:1] = c[6:0];
+
+endmodule
+
+
+//============================================================
+// 1-bit Full Adder
+//============================================================
+module full_adder (
+ input a,
+ input b,
+ input cin,
+ output sum,
+ output cout
+);
+ assign sum = a ^ b ^ cin;
+ assign cout = (a & b) | (a & cin) | (b & cin);
+endmodule
\ No newline at end of file
diff --git a/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul_Previous_Values.xml b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul_Previous_Values.xml
new file mode 100644
index 000000000..c235d7ff1
--- /dev/null
+++ b/fossee/booth_wallace/booth_wallace_mul/booth_wallace_mul_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01100nsnsnsdc5dc5dc5dc5dc5dc5dc5dc5booth_wallace_muladc_bridgedac_bridge
\ No newline at end of file
diff --git a/fossee/booth_wallace/booth_wallace_op_wave.png b/fossee/booth_wallace/booth_wallace_op_wave.png
new file mode 100644
index 000000000..0a176ea75
Binary files /dev/null and b/fossee/booth_wallace/booth_wallace_op_wave.png differ
diff --git a/fossee/booth_wallace/booth_wallace_schematic.png b/fossee/booth_wallace/booth_wallace_schematic.png
new file mode 100644
index 000000000..3acd97a1d
Binary files /dev/null and b/fossee/booth_wallace/booth_wallace_schematic.png differ
diff --git a/fossee/booth_wallace/multiplier.v b/fossee/booth_wallace/multiplier.v
new file mode 100644
index 000000000..97bffb85f
--- /dev/null
+++ b/fossee/booth_wallace/multiplier.v
@@ -0,0 +1,119 @@
+`timescale 1ns/1ps
+
+// ============================================================
+// 4x4 Signed Booth + Wallace (CSA) Multiplier
+// ============================================================
+
+module booth_wallace_4x4 (
+ input signed [3:0] A,
+ input signed [3:0] B,
+ output signed [7:0] P
+);
+
+ // --------------------------------------------------
+ // Sign extend A
+ // --------------------------------------------------
+ wire signed [7:0] A_ext = {{4{A[3]}}, A};
+ wire signed [7:0] negA = -A_ext;
+
+ // --------------------------------------------------
+ // Booth Encoding (Radix-2)
+ // --------------------------------------------------
+
+ wire signed [7:0] op0 =
+ ({B[0],1'b0} == 2'b01) ? A_ext :
+ ({B[0],1'b0} == 2'b10) ? negA :
+ 8'sd0;
+
+ wire signed [7:0] op1 =
+ ({B[1],B[0]} == 2'b01) ? A_ext :
+ ({B[1],B[0]} == 2'b10) ? negA :
+ 8'sd0;
+
+ wire signed [7:0] op2 =
+ ({B[2],B[1]} == 2'b01) ? A_ext :
+ ({B[2],B[1]} == 2'b10) ? negA :
+ 8'sd0;
+
+ wire signed [7:0] op3 =
+ ({B[3],B[2]} == 2'b01) ? A_ext :
+ ({B[3],B[2]} == 2'b10) ? negA :
+ 8'sd0;
+
+ // Shift partial products
+ wire signed [7:0] pp0 = op0 <<< 0;
+ wire signed [7:0] pp1 = op1 <<< 1;
+ wire signed [7:0] pp2 = op2 <<< 2;
+ wire signed [7:0] pp3 = op3 <<< 3;
+
+ // --------------------------------------------------
+ // Wallace Tree (CSA Stage 1)
+ // --------------------------------------------------
+ wire [7:0] s1, c1;
+ csa_8bit CSA1 (.x(pp0), .y(pp1), .z(pp2), .sum(s1), .carry(c1));
+
+ // --------------------------------------------------
+ // Wallace Tree (CSA Stage 2)
+ // --------------------------------------------------
+ wire [7:0] s2, c2;
+ csa_8bit CSA2 (.x(s1), .y(c1), .z(pp3), .sum(s2), .carry(c2));
+
+ // --------------------------------------------------
+ // Final Carry Propagate Adder
+ // --------------------------------------------------
+ assign P = s2 + c2;
+
+endmodule
+
+
+
+// ============================================================
+// 8-bit Carry Save Adder (3→2 compressor)
+// ============================================================
+
+module csa_8bit (
+ input [7:0] x,
+ input [7:0] y,
+ input [7:0] z,
+ output [7:0] sum,
+ output [7:0] carry
+);
+
+ wire [7:0] c;
+
+ genvar i;
+ generate
+ for (i = 0; i < 8; i = i + 1) begin : CSA
+ full_adder FA (
+ .a(x[i]),
+ .b(y[i]),
+ .cin(z[i]),
+ .sum(sum[i]),
+ .cout(c[i])
+ );
+ end
+ endgenerate
+
+ // Shift carry left by 1
+ assign carry[0] = 1'b0;
+ assign carry[7:1] = c[6:0];
+
+endmodule
+
+
+
+// ============================================================
+// 1-bit Full Adder
+// ============================================================
+
+module full_adder (
+ input a,
+ input b,
+ input cin,
+ output sum,
+ output cout
+);
+
+ assign sum = a ^ b ^ cin;
+ assign cout = (a & b) | (a & cin) | (b & cin);
+ endmodule
\ No newline at end of file
diff --git a/fossee/booth_wallace/tb.v b/fossee/booth_wallace/tb.v
new file mode 100644
index 000000000..bc0f75db5
--- /dev/null
+++ b/fossee/booth_wallace/tb.v
@@ -0,0 +1,36 @@
+`timescale 1ns/1ps
+
+module tb_booth_wallace;
+
+ reg signed [3:0] A, B;
+ wire signed [7:0] P;
+
+ // Instantiate DUT
+ booth_wallace_4x4 DUT (
+ .A(A),
+ .B(B),
+ .P(P)
+ );
+
+ initial begin
+
+ // Apply inputs
+ A = 7;
+ B = -5;
+
+ #5; // wait for combinational logic
+
+ $display("A = %0d", A);
+ $display("B = %0d", B);
+ $display("Product = %0d", P);
+
+ if (P == -20)
+ $display("TEST PASSED ✅");
+ else
+ $display("TEST FAILED ❌");
+
+ $finish;
+
+ end
+
+endmodule
\ No newline at end of file
diff --git a/fossee/bram/bram.png b/fossee/bram/bram.png
new file mode 100644
index 000000000..eb46d8d41
Binary files /dev/null and b/fossee/bram/bram.png differ
diff --git a/fossee/bram/bram.zip b/fossee/bram/bram.zip
new file mode 100644
index 000000000..a6c57c258
Binary files /dev/null and b/fossee/bram/bram.zip differ
diff --git a/fossee/bram/bram_cmd.png b/fossee/bram/bram_cmd.png
new file mode 100644
index 000000000..23b5a872d
Binary files /dev/null and b/fossee/bram/bram_cmd.png differ
diff --git a/fossee/bram/bram_ip.png b/fossee/bram/bram_ip.png
new file mode 100644
index 000000000..466d1448f
Binary files /dev/null and b/fossee/bram/bram_ip.png differ
diff --git a/fossee/bram/bram_op.png b/fossee/bram/bram_op.png
new file mode 100644
index 000000000..99b768a34
Binary files /dev/null and b/fossee/bram/bram_op.png differ
diff --git a/fossee/bram/bram_schematic.png b/fossee/bram/bram_schematic.png
new file mode 100644
index 000000000..d7deba64d
Binary files /dev/null and b/fossee/bram/bram_schematic.png differ
diff --git a/fossee/divider/divider.v b/fossee/divider/divider.v
new file mode 100644
index 000000000..6c3145c55
--- /dev/null
+++ b/fossee/divider/divider.v
@@ -0,0 +1,87 @@
+module divider_8bit_pipeline (
+ input wire clk,
+ input wire rst,
+ input wire in_valid,
+ input wire [7:0] dividend,
+ input wire [7:0] divisor,
+ output wire out_valid,
+ output wire [7:0] quotient,
+ output wire [7:0] remainder
+);
+
+ // Pipeline registers
+ reg valid_pipe [0:8];
+ reg [7:0] divisor_pipe [0:8];
+ reg [7:0] quotient_pipe [0:8];
+ reg [8:0] remainder_pipe [0:8];
+ reg div0_pipe [0:8]; // NEW: divide-by-zero pipeline
+
+ // Stage 0 (Input stage)
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ valid_pipe[0] <= 0;
+ quotient_pipe[0] <= 0;
+ remainder_pipe[0] <= 0;
+ divisor_pipe[0] <= 0;
+ div0_pipe[0] <= 0;
+ end
+ else begin
+ valid_pipe[0] <= in_valid;
+ quotient_pipe[0] <= dividend;
+ remainder_pipe[0] <= 0;
+ divisor_pipe[0] <= divisor;
+ div0_pipe[0] <= (divisor == 0); // detect divide-by-zero
+ end
+ end
+
+ // Pipeline stages
+ genvar s;
+ generate
+ for (s = 1; s <= 8; s = s + 1) begin : PIPE
+
+ reg [8:0] rem_shift;
+ reg [7:0] quot_shift;
+
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ valid_pipe[s] <= 0;
+ quotient_pipe[s] <= 0;
+ remainder_pipe[s] <= 0;
+ divisor_pipe[s] <= 0;
+ div0_pipe[s] <= 0;
+ end
+ else begin
+ valid_pipe[s] <= valid_pipe[s-1];
+ divisor_pipe[s] <= divisor_pipe[s-1];
+ div0_pipe[s] <= div0_pipe[s-1];
+
+ // If divide-by-zero, just propagate
+ if (div0_pipe[s-1]) begin
+ quotient_pipe[s] <= 0;
+ remainder_pipe[s] <= quotient_pipe[s-1];
+ end
+ else begin
+ // Normal division
+ rem_shift = {remainder_pipe[s-1][7:0], quotient_pipe[s-1][7]};
+ quot_shift = {quotient_pipe[s-1][6:0], 1'b0};
+
+ if (rem_shift >= divisor_pipe[s-1]) begin
+ remainder_pipe[s] <= rem_shift - divisor_pipe[s-1];
+ quotient_pipe[s] <= {quot_shift[7:1], 1'b1};
+ end
+ else begin
+ remainder_pipe[s] <= rem_shift;
+ quotient_pipe[s] <= {quot_shift[7:1], 1'b0};
+ end
+ end
+ end
+ end
+
+ end
+ endgenerate
+
+ assign out_valid = valid_pipe[8];
+ assign quotient = quotient_pipe[8];
+ assign remainder = remainder_pipe[8][7:0];
+
+endmodule
\ No newline at end of file
diff --git a/fossee/divider/divider/analysis b/fossee/divider/divider/analysis
new file mode 100644
index 000000000..6887867a2
--- /dev/null
+++ b/fossee/divider/divider/analysis
@@ -0,0 +1 @@
+.tran 1e-09 500e-09 0e-00
\ No newline at end of file
diff --git a/fossee/divider/divider/divider-cache.lib b/fossee/divider/divider/divider-cache.lib
new file mode 100644
index 000000000..4a4b16ffd
--- /dev/null
+++ b/fossee/divider/divider/divider-cache.lib
@@ -0,0 +1,219 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_3
+#
+DEF adc_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# divider
+#
+DEF divider U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "divider" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 -100 0 1 0 N
+X clk0 1 2150 1900 200 R 50 50 1 1 I
+X rst0 2 2150 1800 200 R 50 50 1 1 I
+X in_valid0 3 2150 1700 200 R 50 50 1 1 I
+X dividend7 4 2150 1600 200 R 50 50 1 1 I
+X dividend6 5 2150 1500 200 R 50 50 1 1 I
+X dividend5 6 2150 1400 200 R 50 50 1 1 I
+X dividend4 7 2150 1300 200 R 50 50 1 1 I
+X dividend3 8 2150 1200 200 R 50 50 1 1 I
+X dividend2 9 2150 1100 200 R 50 50 1 1 I
+X dividend1 10 2150 1000 200 R 50 50 1 1 I
+X out_valid0 20 3550 1900 200 L 50 50 1 1 O
+X remainder6 30 3550 900 200 L 50 50 1 1 O
+X dividend0 11 2150 900 200 R 50 50 1 1 I
+X quotient7 21 3550 1800 200 L 50 50 1 1 O
+X remainder5 31 3550 800 200 L 50 50 1 1 O
+X divisor7 12 2150 800 200 R 50 50 1 1 I
+X quotient6 22 3550 1700 200 L 50 50 1 1 O
+X remainder4 32 3550 700 200 L 50 50 1 1 O
+X divisor6 13 2150 700 200 R 50 50 1 1 I
+X quotient5 23 3550 1600 200 L 50 50 1 1 O
+X remainder3 33 3550 600 200 L 50 50 1 1 O
+X divisor5 14 2150 600 200 R 50 50 1 1 I
+X quotient4 24 3550 1500 200 L 50 50 1 1 O
+X remainder2 34 3550 500 200 L 50 50 1 1 O
+X divisor4 15 2150 500 200 R 50 50 1 1 I
+X quotient3 25 3550 1400 200 L 50 50 1 1 O
+X remainder1 35 3550 400 200 L 50 50 1 1 O
+X divisor3 16 2150 400 200 R 50 50 1 1 I
+X quotient2 26 3550 1300 200 L 50 50 1 1 O
+X remainder0 36 3550 300 200 L 50 50 1 1 O
+X divisor2 17 2150 300 200 R 50 50 1 1 I
+X quotient1 27 3550 1200 200 L 50 50 1 1 O
+X divisor1 18 2150 200 200 R 50 50 1 1 I
+X quotient0 28 3550 1100 200 L 50 50 1 1 O
+X divisor0 19 2150 100 200 R 50 50 1 1 I
+X remainder7 29 3550 1000 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/fossee/divider/divider/divider.cir b/fossee/divider/divider/divider.cir
new file mode 100644
index 000000000..279bc16e9
--- /dev/null
+++ b/fossee/divider/divider/divider.cir
@@ -0,0 +1,72 @@
+* C:\Users\VLSI\eSim-Workspace\divider\divider.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/03/2026 19:46:01
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ Net-_U19-Pad4_ Net-_U19-Pad5_ Net-_U19-Pad6_ Net-_U19-Pad7_ Net-_U19-Pad8_ Net-_U19-Pad9_ Net-_U19-Pad10_ Net-_U19-Pad11_ Net-_U19-Pad12_ Net-_U19-Pad13_ Net-_U19-Pad14_ Net-_U19-Pad15_ Net-_U19-Pad16_ Net-_U19-Pad17_ Net-_U19-Pad18_ Net-_U19-Pad19_ Net-_U19-Pad20_ Net-_U19-Pad21_ Net-_U19-Pad22_ Net-_U19-Pad23_ Net-_U19-Pad24_ Net-_U19-Pad25_ Net-_U19-Pad26_ Net-_U19-Pad27_ Net-_U19-Pad28_ Net-_U19-Pad29_ Net-_U19-Pad30_ Net-_U19-Pad31_ Net-_U19-Pad32_ Net-_U19-Pad33_ Net-_U19-Pad34_ Net-_U19-Pad35_ Net-_U19-Pad36_ divider
+v1 clk0 GND pulse
+v2 rst0 GND pulse
+v11 divend7 GND DC
+v12 divend6 GND DC
+v13 divend5 GND DC
+v14 divend4 GND DC
+v15 divend3 GND DC
+v16 divend2 GND DC
+v17 divend1 GND DC
+v18 divend0 GND DC
+v3 div7 GND DC
+v4 div6 GND DC
+v5 div5 GND DC
+v6 div4 GND DC
+v7 div3 GND DC
+v8 div2 GND DC
+v9 div1 GND DC
+v19 GND div0 DC
+v10 in_valid0 GND DC
+U21 div7 div6 div5 div4 div3 div2 div1 div0 Net-_U19-Pad12_ Net-_U19-Pad13_ Net-_U19-Pad14_ Net-_U19-Pad15_ Net-_U19-Pad16_ Net-_U19-Pad17_ Net-_U19-Pad18_ Net-_U19-Pad19_ adc_bridge_8
+U23 divend7 divend6 divend5 divend4 divend3 divend2 divend1 divend0 Net-_U19-Pad4_ Net-_U19-Pad5_ Net-_U19-Pad6_ Net-_U19-Pad7_ Net-_U19-Pad8_ Net-_U19-Pad9_ Net-_U19-Pad10_ Net-_U19-Pad11_ adc_bridge_8
+U22 clk0 rst0 in_valid0 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ adc_bridge_3
+U26 Net-_U19-Pad29_ Net-_U19-Pad30_ Net-_U19-Pad31_ Net-_U19-Pad32_ Net-_U19-Pad33_ Net-_U19-Pad34_ Net-_U19-Pad35_ Net-_U19-Pad36_ r7 r6 r5 r4 r3 r2 r1 r0 dac_bridge_8
+U25 Net-_U19-Pad21_ Net-_U19-Pad22_ Net-_U19-Pad23_ Net-_U19-Pad24_ Net-_U19-Pad25_ Net-_U19-Pad26_ Net-_U19-Pad27_ Net-_U19-Pad28_ q7 q6 q5 q4 q3 q2 q1 q0 dac_bridge_8
+U24 Net-_U19-Pad20_ ou_valid0 dac_bridge_1
+U13 clk0 plot_v1
+U6 rst0 plot_v1
+U3 in_valid0 plot_v1
+U12 divend7 plot_v1
+U7 divend6 plot_v1
+U9 divend5 plot_v1
+U4 divend4 plot_v1
+U10 divend3 plot_v1
+U5 divend2 plot_v1
+U15 divend1 plot_v1
+U1 divend0 plot_v1
+U2 div7 plot_v1
+U8 div6 plot_v1
+U11 div5 plot_v1
+U14 div4 plot_v1
+U16 div3 plot_v1
+U17 div2 plot_v1
+U18 div1 plot_v1
+U20 div0 plot_v1
+U28 q7 plot_v1
+U29 q6 plot_v1
+U30 q5 plot_v1
+U31 q4 plot_v1
+U32 q3 plot_v1
+U33 q2 plot_v1
+U34 q1 plot_v1
+U35 q0 plot_v1
+U36 r7 plot_v1
+U37 r6 plot_v1
+U38 r5 plot_v1
+U39 r4 plot_v1
+U40 r3 plot_v1
+U41 r2 plot_v1
+U42 r1 plot_v1
+U43 r0 plot_v1
+U27 ou_valid0 plot_v1
+
+.end
diff --git a/fossee/divider/divider/divider.cir.out b/fossee/divider/divider/divider.cir.out
new file mode 100644
index 000000000..0b7ac71ba
--- /dev/null
+++ b/fossee/divider/divider/divider.cir.out
@@ -0,0 +1,101 @@
+* c:\users\vlsi\esim-workspace\divider\divider.cir
+
+* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ net-_u19-pad4_ net-_u19-pad5_ net-_u19-pad6_ net-_u19-pad7_ net-_u19-pad8_ net-_u19-pad9_ net-_u19-pad10_ net-_u19-pad11_ net-_u19-pad12_ net-_u19-pad13_ net-_u19-pad14_ net-_u19-pad15_ net-_u19-pad16_ net-_u19-pad17_ net-_u19-pad18_ net-_u19-pad19_ net-_u19-pad20_ net-_u19-pad21_ net-_u19-pad22_ net-_u19-pad23_ net-_u19-pad24_ net-_u19-pad25_ net-_u19-pad26_ net-_u19-pad27_ net-_u19-pad28_ net-_u19-pad29_ net-_u19-pad30_ net-_u19-pad31_ net-_u19-pad32_ net-_u19-pad33_ net-_u19-pad34_ net-_u19-pad35_ net-_u19-pad36_ divider
+v1 clk0 gnd pulse(0 1 0.01ns 0.001ns 0.001ns 10ns 20ns)
+v2 rst0 gnd pulse(0 1 0.001ns 0.001ns 0.001ns 15ns 300ns)
+v11 divend7 gnd dc 0
+v12 divend6 gnd dc 0
+v13 divend5 gnd dc 0
+v14 divend4 gnd dc 0
+v15 divend3 gnd dc 5
+v16 divend2 gnd dc 5
+v17 divend1 gnd dc 5
+v18 divend0 gnd dc 5
+v3 div7 gnd dc 0
+v4 div6 gnd dc 0
+v5 div5 gnd dc 0
+v6 div4 gnd dc 0
+v7 div3 gnd dc 0
+v8 div2 gnd dc 5
+v9 div1 gnd dc 0
+v19 gnd div0 dc 0
+v10 in_valid0 gnd dc 5
+* u21 div7 div6 div5 div4 div3 div2 div1 div0 net-_u19-pad12_ net-_u19-pad13_ net-_u19-pad14_ net-_u19-pad15_ net-_u19-pad16_ net-_u19-pad17_ net-_u19-pad18_ net-_u19-pad19_ adc_bridge_8
+* u23 divend7 divend6 divend5 divend4 divend3 divend2 divend1 divend0 net-_u19-pad4_ net-_u19-pad5_ net-_u19-pad6_ net-_u19-pad7_ net-_u19-pad8_ net-_u19-pad9_ net-_u19-pad10_ net-_u19-pad11_ adc_bridge_8
+* u22 clk0 rst0 in_valid0 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ adc_bridge_3
+* u26 net-_u19-pad29_ net-_u19-pad30_ net-_u19-pad31_ net-_u19-pad32_ net-_u19-pad33_ net-_u19-pad34_ net-_u19-pad35_ net-_u19-pad36_ r7 r6 r5 r4 r3 r2 r1 r0 dac_bridge_8
+* u25 net-_u19-pad21_ net-_u19-pad22_ net-_u19-pad23_ net-_u19-pad24_ net-_u19-pad25_ net-_u19-pad26_ net-_u19-pad27_ net-_u19-pad28_ q7 q6 q5 q4 q3 q2 q1 q0 dac_bridge_8
+* u24 net-_u19-pad20_ ou_valid0 dac_bridge_1
+* u13 clk0 plot_v1
+* u6 rst0 plot_v1
+* u3 in_valid0 plot_v1
+* u12 divend7 plot_v1
+* u7 divend6 plot_v1
+* u9 divend5 plot_v1
+* u4 divend4 plot_v1
+* u10 divend3 plot_v1
+* u5 divend2 plot_v1
+* u15 divend1 plot_v1
+* u1 divend0 plot_v1
+* u2 div7 plot_v1
+* u8 div6 plot_v1
+* u11 div5 plot_v1
+* u14 div4 plot_v1
+* u16 div3 plot_v1
+* u17 div2 plot_v1
+* u18 div1 plot_v1
+* u20 div0 plot_v1
+* u28 q7 plot_v1
+* u29 q6 plot_v1
+* u30 q5 plot_v1
+* u31 q4 plot_v1
+* u32 q3 plot_v1
+* u33 q2 plot_v1
+* u34 q1 plot_v1
+* u35 q0 plot_v1
+* u36 r7 plot_v1
+* u37 r6 plot_v1
+* u38 r5 plot_v1
+* u39 r4 plot_v1
+* u40 r3 plot_v1
+* u41 r2 plot_v1
+* u42 r1 plot_v1
+* u43 r0 plot_v1
+* u27 ou_valid0 plot_v1
+a1 [net-_u19-pad1_ ] [net-_u19-pad2_ ] [net-_u19-pad3_ ] [net-_u19-pad4_ net-_u19-pad5_ net-_u19-pad6_ net-_u19-pad7_ net-_u19-pad8_ net-_u19-pad9_ net-_u19-pad10_ net-_u19-pad11_ ] [net-_u19-pad12_ net-_u19-pad13_ net-_u19-pad14_ net-_u19-pad15_ net-_u19-pad16_ net-_u19-pad17_ net-_u19-pad18_ net-_u19-pad19_ ] [net-_u19-pad20_ ] [net-_u19-pad21_ net-_u19-pad22_ net-_u19-pad23_ net-_u19-pad24_ net-_u19-pad25_ net-_u19-pad26_ net-_u19-pad27_ net-_u19-pad28_ ] [net-_u19-pad29_ net-_u19-pad30_ net-_u19-pad31_ net-_u19-pad32_ net-_u19-pad33_ net-_u19-pad34_ net-_u19-pad35_ net-_u19-pad36_ ] u19
+a2 [div7 div6 div5 div4 div3 div2 div1 div0 ] [net-_u19-pad12_ net-_u19-pad13_ net-_u19-pad14_ net-_u19-pad15_ net-_u19-pad16_ net-_u19-pad17_ net-_u19-pad18_ net-_u19-pad19_ ] u21
+a3 [divend7 divend6 divend5 divend4 divend3 divend2 divend1 divend0 ] [net-_u19-pad4_ net-_u19-pad5_ net-_u19-pad6_ net-_u19-pad7_ net-_u19-pad8_ net-_u19-pad9_ net-_u19-pad10_ net-_u19-pad11_ ] u23
+a4 [clk0 rst0 in_valid0 ] [net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ ] u22
+a5 [net-_u19-pad29_ net-_u19-pad30_ net-_u19-pad31_ net-_u19-pad32_ net-_u19-pad33_ net-_u19-pad34_ net-_u19-pad35_ net-_u19-pad36_ ] [r7 r6 r5 r4 r3 r2 r1 r0 ] u26
+a6 [net-_u19-pad21_ net-_u19-pad22_ net-_u19-pad23_ net-_u19-pad24_ net-_u19-pad25_ net-_u19-pad26_ net-_u19-pad27_ net-_u19-pad28_ ] [q7 q6 q5 q4 q3 q2 q1 q0 ] u25
+a7 [net-_u19-pad20_ ] [ou_valid0 ] u24
+* Schematic Name: divider, NgSpice Name: divider
+.model u19 divider(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u21 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u23 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u22 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
+.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
+.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 1e-09 500e-09 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(ou_valid0) +6 v(in_valid0) +12 v(rst0) +18 v(clk0) +24
+plot v(q0)+6 v(q1)+12 v(q2)+18 v(q3)+24 v(q4)+30 v(q5)+36 v(q6)+42 v(q7)+48
+plot v(r0)+6 v(r1)+12 v(r2)+18 v(r3)+24 v(r4)+30 v(r5)+36 v(r6)+42 v(r7)+48
+plot v(divend0)+6 v(divend1)+12 v(divend2)+18 v(divend3)+24 v(divend4)+30 v(divend5)+36 v(divend6)+42 v(divend7)+48
+plot v(div0)+6 v(div1)+12 v(div2)+18 v(div3)+24 v(div4)+30 v(div5)+36 v(div6)+42 v(div7)+48
+
+
+.endc
+.end
diff --git a/fossee/divider/divider/divider.pro b/fossee/divider/divider/divider.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/fossee/divider/divider/divider.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/fossee/divider/divider/divider.proj b/fossee/divider/divider/divider.proj
new file mode 100644
index 000000000..071adcdac
--- /dev/null
+++ b/fossee/divider/divider/divider.proj
@@ -0,0 +1 @@
+schematicFile divider.sch
diff --git a/fossee/divider/divider/divider.sch b/fossee/divider/divider/divider.sch
new file mode 100644
index 000000000..32fcd028d
--- /dev/null
+++ b/fossee/divider/divider/divider.sch
@@ -0,0 +1,1415 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L divider U19
+U 1 1 69A6E73F
+P 2900 4750
+F 0 "U19" H 5750 6550 60 0000 C CNN
+F 1 "divider" H 5750 6750 60 0000 C CNN
+F 2 "" H 5750 6700 60 0000 C CNN
+F 3 "" H 5750 6700 60 0000 C CNN
+ 1 2900 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v1
+U 1 1 69A6E7C4
+P 1250 1350
+F 0 "v1" H 1050 1450 60 0000 C CNN
+F 1 "pulse" H 1050 1300 60 0000 C CNN
+F 2 "R1" H 950 1350 60 0000 C CNN
+F 3 "" H 1250 1350 60 0000 C CNN
+ 1 1250 1350
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v2
+U 1 1 69A6E829
+P 1250 1700
+F 0 "v2" H 1050 1800 60 0000 C CNN
+F 1 "pulse" H 1050 1650 60 0000 C CNN
+F 2 "R1" H 950 1700 60 0000 C CNN
+F 3 "" H 1250 1700 60 0000 C CNN
+ 1 1250 1700
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v11
+U 1 1 69A6E862
+P 1300 2550
+F 0 "v11" H 1100 2650 60 0000 C CNN
+F 1 "DC" H 1100 2500 60 0000 C CNN
+F 2 "R1" H 1000 2550 60 0000 C CNN
+F 3 "" H 1300 2550 60 0000 C CNN
+ 1 1300 2550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v12
+U 1 1 69A6E931
+P 1300 2900
+F 0 "v12" H 1100 3000 60 0000 C CNN
+F 1 "DC" H 1100 2850 60 0000 C CNN
+F 2 "R1" H 1000 2900 60 0000 C CNN
+F 3 "" H 1300 2900 60 0000 C CNN
+ 1 1300 2900
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v13
+U 1 1 69A6EA39
+P 1300 3200
+F 0 "v13" H 1100 3300 60 0000 C CNN
+F 1 "DC" H 1100 3150 60 0000 C CNN
+F 2 "R1" H 1000 3200 60 0000 C CNN
+F 3 "" H 1300 3200 60 0000 C CNN
+ 1 1300 3200
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v14
+U 1 1 69A6EA40
+P 1300 3550
+F 0 "v14" H 1100 3650 60 0000 C CNN
+F 1 "DC" H 1100 3500 60 0000 C CNN
+F 2 "R1" H 1000 3550 60 0000 C CNN
+F 3 "" H 1300 3550 60 0000 C CNN
+ 1 1300 3550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v15
+U 1 1 69A6EB31
+P 1300 3900
+F 0 "v15" H 1100 4000 60 0000 C CNN
+F 1 "DC" H 1100 3850 60 0000 C CNN
+F 2 "R1" H 1000 3900 60 0000 C CNN
+F 3 "" H 1300 3900 60 0000 C CNN
+ 1 1300 3900
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v16
+U 1 1 69A6EB38
+P 1300 4250
+F 0 "v16" H 1100 4350 60 0000 C CNN
+F 1 "DC" H 1100 4200 60 0000 C CNN
+F 2 "R1" H 1000 4250 60 0000 C CNN
+F 3 "" H 1300 4250 60 0000 C CNN
+ 1 1300 4250
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v17
+U 1 1 69A6EB3F
+P 1300 4550
+F 0 "v17" H 1100 4650 60 0000 C CNN
+F 1 "DC" H 1100 4500 60 0000 C CNN
+F 2 "R1" H 1000 4550 60 0000 C CNN
+F 3 "" H 1300 4550 60 0000 C CNN
+ 1 1300 4550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v18
+U 1 1 69A6EB46
+P 1300 4900
+F 0 "v18" H 1100 5000 60 0000 C CNN
+F 1 "DC" H 1100 4850 60 0000 C CNN
+F 2 "R1" H 1000 4900 60 0000 C CNN
+F 3 "" H 1300 4900 60 0000 C CNN
+ 1 1300 4900
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v3
+U 1 1 69A6EE4B
+P 1250 5500
+F 0 "v3" H 1050 5600 60 0000 C CNN
+F 1 "DC" H 1050 5450 60 0000 C CNN
+F 2 "R1" H 950 5500 60 0000 C CNN
+F 3 "" H 1250 5500 60 0000 C CNN
+ 1 1250 5500
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v4
+U 1 1 69A6EE52
+P 1250 5850
+F 0 "v4" H 1050 5950 60 0000 C CNN
+F 1 "DC" H 1050 5800 60 0000 C CNN
+F 2 "R1" H 950 5850 60 0000 C CNN
+F 3 "" H 1250 5850 60 0000 C CNN
+ 1 1250 5850
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v5
+U 1 1 69A6EE59
+P 1250 6150
+F 0 "v5" H 1050 6250 60 0000 C CNN
+F 1 "DC" H 1050 6100 60 0000 C CNN
+F 2 "R1" H 950 6150 60 0000 C CNN
+F 3 "" H 1250 6150 60 0000 C CNN
+ 1 1250 6150
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v6
+U 1 1 69A6EE60
+P 1250 6500
+F 0 "v6" H 1050 6600 60 0000 C CNN
+F 1 "DC" H 1050 6450 60 0000 C CNN
+F 2 "R1" H 950 6500 60 0000 C CNN
+F 3 "" H 1250 6500 60 0000 C CNN
+ 1 1250 6500
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v7
+U 1 1 69A6EE67
+P 1250 6850
+F 0 "v7" H 1050 6950 60 0000 C CNN
+F 1 "DC" H 1050 6800 60 0000 C CNN
+F 2 "R1" H 950 6850 60 0000 C CNN
+F 3 "" H 1250 6850 60 0000 C CNN
+ 1 1250 6850
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v8
+U 1 1 69A6EE6E
+P 1250 7200
+F 0 "v8" H 1050 7300 60 0000 C CNN
+F 1 "DC" H 1050 7150 60 0000 C CNN
+F 2 "R1" H 950 7200 60 0000 C CNN
+F 3 "" H 1250 7200 60 0000 C CNN
+ 1 1250 7200
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v9
+U 1 1 69A6EE75
+P 1250 7500
+F 0 "v9" H 1050 7600 60 0000 C CNN
+F 1 "DC" H 1050 7450 60 0000 C CNN
+F 2 "R1" H 950 7500 60 0000 C CNN
+F 3 "" H 1250 7500 60 0000 C CNN
+ 1 1250 7500
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v19
+U 1 1 69A6EE7C
+P 3400 6100
+F 0 "v19" H 3200 6200 60 0000 C CNN
+F 1 "DC" H 3200 6050 60 0000 C CNN
+F 2 "R1" H 3100 6100 60 0000 C CNN
+F 3 "" H 3400 6100 60 0000 C CNN
+ 1 3400 6100
+ -1 0 0 1
+$EndComp
+$Comp
+L DC v10
+U 1 1 69A6EFA1
+P 1300 2050
+F 0 "v10" H 1100 2150 60 0000 C CNN
+F 1 "DC" H 1100 2000 60 0000 C CNN
+F 2 "R1" H 1000 2050 60 0000 C CNN
+F 3 "" H 1300 2050 60 0000 C CNN
+ 1 1300 2050
+ 0 1 1 0
+$EndComp
+$Comp
+L adc_bridge_8 U21
+U 1 1 69A6F342
+P 3950 4500
+F 0 "U21" H 3950 4500 60 0000 C CNN
+F 1 "adc_bridge_8" H 3950 4650 60 0000 C CNN
+F 2 "" H 3950 4500 60 0000 C CNN
+F 3 "" H 3950 4500 60 0000 C CNN
+ 1 3950 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_8 U23
+U 1 1 69A6F3F3
+P 4500 3200
+F 0 "U23" H 4500 3200 60 0000 C CNN
+F 1 "adc_bridge_8" H 4500 3350 60 0000 C CNN
+F 2 "" H 4500 3200 60 0000 C CNN
+F 3 "" H 4500 3200 60 0000 C CNN
+ 1 4500 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_3 U22
+U 1 1 69A6F72E
+P 4500 2900
+F 0 "U22" H 4500 2900 60 0000 C CNN
+F 1 "adc_bridge_3" H 4500 3050 60 0000 C CNN
+F 2 "" H 4500 2900 60 0000 C CNN
+F 3 "" H 4500 2900 60 0000 C CNN
+ 1 4500 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_8 U26
+U 1 1 69A6F7B1
+P 7550 4050
+F 0 "U26" H 7550 4050 60 0000 C CNN
+F 1 "dac_bridge_8" H 7550 4200 60 0000 C CNN
+F 2 "" H 7550 4050 60 0000 C CNN
+F 3 "" H 7550 4050 60 0000 C CNN
+ 1 7550 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_8 U25
+U 1 1 69A6F83C
+P 7050 3000
+F 0 "U25" H 7050 3000 60 0000 C CNN
+F 1 "dac_bridge_8" H 7050 3150 60 0000 C CNN
+F 2 "" H 7050 3000 60 0000 C CNN
+F 3 "" H 7050 3000 60 0000 C CNN
+ 1 7050 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_1 U24
+U 1 1 69A6F897
+P 7050 2600
+F 0 "U24" H 7050 2600 60 0000 C CNN
+F 1 "dac_bridge_1" H 7050 2750 60 0000 C CNN
+F 2 "" H 7050 2600 60 0000 C CNN
+F 3 "" H 7050 2600 60 0000 C CNN
+ 1 7050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 69A71B42
+P 550 1200
+F 0 "#PWR01" H 550 950 50 0001 C CNN
+F 1 "GND" H 550 1050 50 0000 C CNN
+F 2 "" H 550 1200 50 0001 C CNN
+F 3 "" H 550 1200 50 0001 C CNN
+ 1 550 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 69A71B8A
+P 800 1700
+F 0 "#PWR02" H 800 1450 50 0001 C CNN
+F 1 "GND" H 800 1550 50 0000 C CNN
+F 2 "" H 800 1700 50 0001 C CNN
+F 3 "" H 800 1700 50 0001 C CNN
+ 1 800 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 69A71BEC
+P 850 2050
+F 0 "#PWR03" H 850 1800 50 0001 C CNN
+F 1 "GND" H 850 1900 50 0000 C CNN
+F 2 "" H 850 2050 50 0001 C CNN
+F 3 "" H 850 2050 50 0001 C CNN
+ 1 850 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR04
+U 1 1 69A71C34
+P 850 2550
+F 0 "#PWR04" H 850 2300 50 0001 C CNN
+F 1 "GND" H 850 2400 50 0000 C CNN
+F 2 "" H 850 2550 50 0001 C CNN
+F 3 "" H 850 2550 50 0001 C CNN
+ 1 850 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR05
+U 1 1 69A71C7C
+P 850 2900
+F 0 "#PWR05" H 850 2650 50 0001 C CNN
+F 1 "GND" H 850 2750 50 0000 C CNN
+F 2 "" H 850 2900 50 0001 C CNN
+F 3 "" H 850 2900 50 0001 C CNN
+ 1 850 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR06
+U 1 1 69A71CC4
+P 850 3200
+F 0 "#PWR06" H 850 2950 50 0001 C CNN
+F 1 "GND" H 850 3050 50 0000 C CNN
+F 2 "" H 850 3200 50 0001 C CNN
+F 3 "" H 850 3200 50 0001 C CNN
+ 1 850 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR07
+U 1 1 69A71D0C
+P 850 3550
+F 0 "#PWR07" H 850 3300 50 0001 C CNN
+F 1 "GND" H 850 3400 50 0000 C CNN
+F 2 "" H 850 3550 50 0001 C CNN
+F 3 "" H 850 3550 50 0001 C CNN
+ 1 850 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR08
+U 1 1 69A71DBD
+P 850 3900
+F 0 "#PWR08" H 850 3650 50 0001 C CNN
+F 1 "GND" H 850 3750 50 0000 C CNN
+F 2 "" H 850 3900 50 0001 C CNN
+F 3 "" H 850 3900 50 0001 C CNN
+ 1 850 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR09
+U 1 1 69A7234D
+P 850 4250
+F 0 "#PWR09" H 850 4000 50 0001 C CNN
+F 1 "GND" H 850 4100 50 0000 C CNN
+F 2 "" H 850 4250 50 0001 C CNN
+F 3 "" H 850 4250 50 0001 C CNN
+ 1 850 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR010
+U 1 1 69A72395
+P 850 4550
+F 0 "#PWR010" H 850 4300 50 0001 C CNN
+F 1 "GND" H 850 4400 50 0000 C CNN
+F 2 "" H 850 4550 50 0001 C CNN
+F 3 "" H 850 4550 50 0001 C CNN
+ 1 850 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR011
+U 1 1 69A723DD
+P 850 4900
+F 0 "#PWR011" H 850 4650 50 0001 C CNN
+F 1 "GND" H 850 4750 50 0000 C CNN
+F 2 "" H 850 4900 50 0001 C CNN
+F 3 "" H 850 4900 50 0001 C CNN
+ 1 850 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR012
+U 1 1 69A72425
+P 800 5500
+F 0 "#PWR012" H 800 5250 50 0001 C CNN
+F 1 "GND" H 800 5350 50 0000 C CNN
+F 2 "" H 800 5500 50 0001 C CNN
+F 3 "" H 800 5500 50 0001 C CNN
+ 1 800 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR013
+U 1 1 69A7246D
+P 800 5850
+F 0 "#PWR013" H 800 5600 50 0001 C CNN
+F 1 "GND" H 800 5700 50 0000 C CNN
+F 2 "" H 800 5850 50 0001 C CNN
+F 3 "" H 800 5850 50 0001 C CNN
+ 1 800 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR014
+U 1 1 69A7297B
+P 800 6150
+F 0 "#PWR014" H 800 5900 50 0001 C CNN
+F 1 "GND" H 800 6000 50 0000 C CNN
+F 2 "" H 800 6150 50 0001 C CNN
+F 3 "" H 800 6150 50 0001 C CNN
+ 1 800 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR015
+U 1 1 69A72A25
+P 800 6500
+F 0 "#PWR015" H 800 6250 50 0001 C CNN
+F 1 "GND" H 800 6350 50 0000 C CNN
+F 2 "" H 800 6500 50 0001 C CNN
+F 3 "" H 800 6500 50 0001 C CNN
+ 1 800 6500
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR016
+U 1 1 69A72A6D
+P 800 6850
+F 0 "#PWR016" H 800 6600 50 0001 C CNN
+F 1 "GND" H 800 6700 50 0000 C CNN
+F 2 "" H 800 6850 50 0001 C CNN
+F 3 "" H 800 6850 50 0001 C CNN
+ 1 800 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR017
+U 1 1 69A72AB5
+P 800 7200
+F 0 "#PWR017" H 800 6950 50 0001 C CNN
+F 1 "GND" H 800 7050 50 0000 C CNN
+F 2 "" H 800 7200 50 0001 C CNN
+F 3 "" H 800 7200 50 0001 C CNN
+ 1 800 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR018
+U 1 1 69A72AFD
+P 800 7500
+F 0 "#PWR018" H 800 7250 50 0001 C CNN
+F 1 "GND" H 800 7350 50 0000 C CNN
+F 2 "" H 800 7500 50 0001 C CNN
+F 3 "" H 800 7500 50 0001 C CNN
+ 1 800 7500
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR019
+U 1 1 69A72B45
+P 3400 6550
+F 0 "#PWR019" H 3400 6300 50 0001 C CNN
+F 1 "GND" H 3400 6400 50 0000 C CNN
+F 2 "" H 3400 6550 50 0001 C CNN
+F 3 "" H 3400 6550 50 0001 C CNN
+ 1 3400 6550
+ 1 0 0 -1
+$EndComp
+Text GLabel 2600 1350 1 60 Input ~ 0
+clk0
+Text GLabel 2800 1700 1 60 Input ~ 0
+rst0
+Text GLabel 3500 2050 1 60 Input ~ 0
+in_valid0
+Text GLabel 3450 2550 1 60 Input ~ 0
+divend7
+Text GLabel 3500 2900 1 60 Input ~ 0
+divend6
+Text GLabel 3450 3200 1 60 Input ~ 0
+divend5
+Text GLabel 3400 3550 1 60 Input ~ 0
+divend4
+Text GLabel 3250 3650 1 60 Input ~ 0
+divend3
+Text GLabel 3050 3750 1 60 Input ~ 0
+divend2
+Text GLabel 2900 3800 1 60 Input ~ 0
+divend1
+Text GLabel 3400 3850 1 60 Input ~ 0
+divend0
+Text GLabel 3300 4450 1 60 Input ~ 0
+div7
+Text GLabel 3200 4550 1 60 Input ~ 0
+div6
+Text GLabel 3300 4650 1 60 Input ~ 0
+div5
+Text GLabel 3200 4750 1 60 Input ~ 0
+div4
+Text GLabel 3250 4850 1 60 Input ~ 0
+div3
+Text GLabel 3200 4950 1 60 Input ~ 0
+div2
+Text GLabel 3300 5050 1 60 Input ~ 0
+div1
+Text GLabel 3350 5350 0 60 Input ~ 0
+div0
+$Comp
+L plot_v1 U13
+U 1 1 69A75CEE
+P 2050 1450
+F 0 "U13" H 2050 1950 60 0000 C CNN
+F 1 "plot_v1" H 2250 1800 60 0000 C CNN
+F 2 "" H 2050 1450 60 0000 C CNN
+F 3 "" H 2050 1450 60 0000 C CNN
+ 1 2050 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 69A75D55
+P 1850 1750
+F 0 "U6" H 1850 2250 60 0000 C CNN
+F 1 "plot_v1" H 2050 2100 60 0000 C CNN
+F 2 "" H 1850 1750 60 0000 C CNN
+F 3 "" H 1850 1750 60 0000 C CNN
+ 1 1850 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U3
+U 1 1 69A75DB8
+P 1800 2150
+F 0 "U3" H 1800 2650 60 0000 C CNN
+F 1 "plot_v1" H 2000 2500 60 0000 C CNN
+F 2 "" H 1800 2150 60 0000 C CNN
+F 3 "" H 1800 2150 60 0000 C CNN
+ 1 1800 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U12
+U 1 1 69A75E1B
+P 2000 2650
+F 0 "U12" H 2000 3150 60 0000 C CNN
+F 1 "plot_v1" H 2200 3000 60 0000 C CNN
+F 2 "" H 2000 2650 60 0000 C CNN
+F 3 "" H 2000 2650 60 0000 C CNN
+ 1 2000 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U7
+U 1 1 69A75E80
+P 1850 2950
+F 0 "U7" H 1850 3450 60 0000 C CNN
+F 1 "plot_v1" H 2050 3300 60 0000 C CNN
+F 2 "" H 1850 2950 60 0000 C CNN
+F 3 "" H 1850 2950 60 0000 C CNN
+ 1 1850 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U9
+U 1 1 69A75EE3
+P 1950 3350
+F 0 "U9" H 1950 3850 60 0000 C CNN
+F 1 "plot_v1" H 2150 3700 60 0000 C CNN
+F 2 "" H 1950 3350 60 0000 C CNN
+F 3 "" H 1950 3350 60 0000 C CNN
+ 1 1950 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 69A76470
+P 1800 3650
+F 0 "U4" H 1800 4150 60 0000 C CNN
+F 1 "plot_v1" H 2000 4000 60 0000 C CNN
+F 2 "" H 1800 3650 60 0000 C CNN
+F 3 "" H 1800 3650 60 0000 C CNN
+ 1 1800 3650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3900 2850 3900 1350
+Wire Wire Line
+ 3900 1350 1700 1350
+Wire Wire Line
+ 1700 1700 3850 1700
+Wire Wire Line
+ 3850 1700 3850 2950
+Wire Wire Line
+ 3850 2950 3900 2950
+Wire Wire Line
+ 1750 2050 3800 2050
+Wire Wire Line
+ 3800 2050 3800 3050
+Wire Wire Line
+ 3800 3050 3900 3050
+Wire Wire Line
+ 1750 2550 3750 2550
+Wire Wire Line
+ 3750 2550 3750 3150
+Wire Wire Line
+ 3750 3150 3900 3150
+Wire Wire Line
+ 1750 2900 3700 2900
+Wire Wire Line
+ 3700 2900 3700 3250
+Wire Wire Line
+ 3700 3250 3900 3250
+Wire Wire Line
+ 1750 3200 3650 3200
+Wire Wire Line
+ 3650 3200 3650 3350
+Wire Wire Line
+ 3650 3350 3900 3350
+Wire Wire Line
+ 1750 3550 3650 3550
+Wire Wire Line
+ 3650 3550 3650 3450
+Wire Wire Line
+ 3650 3450 3900 3450
+Wire Wire Line
+ 3900 3550 3700 3550
+Wire Wire Line
+ 3700 3550 3700 3650
+Wire Wire Line
+ 3700 3650 2250 3650
+Wire Wire Line
+ 2250 3650 2250 3900
+Wire Wire Line
+ 2250 3900 1750 3900
+Wire Wire Line
+ 1750 4250 2400 4250
+Wire Wire Line
+ 2400 4250 2400 3750
+Wire Wire Line
+ 2400 3750 3750 3750
+Wire Wire Line
+ 3750 3750 3750 3650
+Wire Wire Line
+ 3750 3650 3900 3650
+Wire Wire Line
+ 1750 4550 2600 4550
+Wire Wire Line
+ 2600 4550 2600 3800
+Wire Wire Line
+ 2600 3800 3850 3800
+Wire Wire Line
+ 3850 3800 3850 3750
+Wire Wire Line
+ 3850 3750 3900 3750
+Wire Wire Line
+ 1750 4900 2750 4900
+Wire Wire Line
+ 2750 4900 2750 3850
+Wire Wire Line
+ 2750 3850 3900 3850
+Wire Wire Line
+ 4500 4450 4650 4450
+Wire Wire Line
+ 4650 4450 4650 3950
+Wire Wire Line
+ 4650 3950 5050 3950
+Wire Wire Line
+ 4500 4550 4700 4550
+Wire Wire Line
+ 4700 4550 4700 4050
+Wire Wire Line
+ 4700 4050 5050 4050
+Wire Wire Line
+ 4500 4650 4750 4650
+Wire Wire Line
+ 4750 4650 4750 4150
+Wire Wire Line
+ 4750 4150 5050 4150
+Wire Wire Line
+ 4500 4750 4800 4750
+Wire Wire Line
+ 4800 4750 4800 4250
+Wire Wire Line
+ 4800 4250 5050 4250
+Wire Wire Line
+ 4500 4850 4850 4850
+Wire Wire Line
+ 4850 4850 4850 4350
+Wire Wire Line
+ 4850 4350 5050 4350
+Wire Wire Line
+ 4500 4950 4900 4950
+Wire Wire Line
+ 4900 4950 4900 4450
+Wire Wire Line
+ 4900 4450 5050 4450
+Wire Wire Line
+ 4500 5050 4950 5050
+Wire Wire Line
+ 4950 5050 4950 4550
+Wire Wire Line
+ 4950 4550 5050 4550
+Wire Wire Line
+ 4500 5150 5050 5150
+Wire Wire Line
+ 5050 5150 5050 4650
+Wire Wire Line
+ 3350 4450 2800 4450
+Wire Wire Line
+ 2800 4450 2800 5500
+Wire Wire Line
+ 2800 5500 1700 5500
+Wire Wire Line
+ 2850 4550 3350 4550
+Wire Wire Line
+ 2850 4550 2850 5850
+Wire Wire Line
+ 2850 5850 1700 5850
+Wire Wire Line
+ 3350 4650 2900 4650
+Wire Wire Line
+ 2900 4650 2900 6150
+Wire Wire Line
+ 2900 6150 1700 6150
+Wire Wire Line
+ 1700 6500 2950 6500
+Wire Wire Line
+ 2950 6500 2950 4750
+Wire Wire Line
+ 2950 4750 3350 4750
+Wire Wire Line
+ 3350 4850 3000 4850
+Wire Wire Line
+ 3000 4850 3000 6850
+Wire Wire Line
+ 3000 6850 1700 6850
+Wire Wire Line
+ 1700 7200 3050 7200
+Wire Wire Line
+ 3050 7200 3050 4950
+Wire Wire Line
+ 3050 4950 3350 4950
+Wire Wire Line
+ 3350 5050 3150 5050
+Wire Wire Line
+ 3150 5050 3150 7500
+Wire Wire Line
+ 3150 7500 1700 7500
+Wire Wire Line
+ 3350 5150 3350 5650
+Wire Wire Line
+ 3350 5650 3400 5650
+Wire Wire Line
+ 6450 2850 6450 2550
+Wire Wire Line
+ 6450 3750 6950 3750
+Wire Wire Line
+ 6950 3750 6950 4000
+Wire Wire Line
+ 6450 3850 6900 3850
+Wire Wire Line
+ 6900 3850 6900 4100
+Wire Wire Line
+ 6900 4100 6950 4100
+Wire Wire Line
+ 6450 3950 6850 3950
+Wire Wire Line
+ 6850 3950 6850 4200
+Wire Wire Line
+ 6850 4200 6950 4200
+Wire Wire Line
+ 6450 4050 6800 4050
+Wire Wire Line
+ 6800 4050 6800 4300
+Wire Wire Line
+ 6800 4300 6950 4300
+Wire Wire Line
+ 6450 4150 6750 4150
+Wire Wire Line
+ 6750 4150 6750 4400
+Wire Wire Line
+ 6750 4400 6950 4400
+Wire Wire Line
+ 6450 4250 6700 4250
+Wire Wire Line
+ 6700 4250 6700 4500
+Wire Wire Line
+ 6700 4500 6950 4500
+Wire Wire Line
+ 6450 4350 6650 4350
+Wire Wire Line
+ 6650 4350 6650 4600
+Wire Wire Line
+ 6650 4600 6950 4600
+Wire Wire Line
+ 6450 4450 6600 4450
+Wire Wire Line
+ 6600 4450 6600 4700
+Wire Wire Line
+ 6600 4700 6950 4700
+Wire Wire Line
+ 2050 1250 2050 1350
+Connection ~ 2050 1350
+Wire Wire Line
+ 1850 1550 1850 1700
+Wire Wire Line
+ 1850 1700 1950 1700
+Connection ~ 1950 1700
+Wire Wire Line
+ 1800 1950 1800 2050
+Connection ~ 1800 2050
+Wire Wire Line
+ 2000 2450 2000 2550
+Connection ~ 2000 2550
+Wire Wire Line
+ 1850 2750 1850 2900
+Connection ~ 1850 2900
+Wire Wire Line
+ 1950 3150 1950 3200
+Connection ~ 1950 3200
+Wire Wire Line
+ 1800 3450 1800 3550
+Connection ~ 1800 3550
+$Comp
+L plot_v1 U10
+U 1 1 69A76A0E
+P 1950 4000
+F 0 "U10" H 1950 4500 60 0000 C CNN
+F 1 "plot_v1" H 2150 4350 60 0000 C CNN
+F 2 "" H 1950 4000 60 0000 C CNN
+F 3 "" H 1950 4000 60 0000 C CNN
+ 1 1950 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 69A76A77
+P 1800 4300
+F 0 "U5" H 1800 4800 60 0000 C CNN
+F 1 "plot_v1" H 2000 4650 60 0000 C CNN
+F 2 "" H 1800 4300 60 0000 C CNN
+F 3 "" H 1800 4300 60 0000 C CNN
+ 1 1800 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U15
+U 1 1 69A76ADE
+P 2150 4600
+F 0 "U15" H 2150 5100 60 0000 C CNN
+F 1 "plot_v1" H 2350 4950 60 0000 C CNN
+F 2 "" H 2150 4600 60 0000 C CNN
+F 3 "" H 2150 4600 60 0000 C CNN
+ 1 2150 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 69A77253
+P 1750 5000
+F 0 "U1" H 1750 5500 60 0000 C CNN
+F 1 "plot_v1" H 1950 5350 60 0000 C CNN
+F 2 "" H 1750 5000 60 0000 C CNN
+F 3 "" H 1750 5000 60 0000 C CNN
+ 1 1750 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U2
+U 1 1 69A772C4
+P 1750 5650
+F 0 "U2" H 1750 6150 60 0000 C CNN
+F 1 "plot_v1" H 1950 6000 60 0000 C CNN
+F 2 "" H 1750 5650 60 0000 C CNN
+F 3 "" H 1750 5650 60 0000 C CNN
+ 1 1750 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U8
+U 1 1 69A77341
+P 1850 5950
+F 0 "U8" H 1850 6450 60 0000 C CNN
+F 1 "plot_v1" H 2050 6300 60 0000 C CNN
+F 2 "" H 1850 5950 60 0000 C CNN
+F 3 "" H 1850 5950 60 0000 C CNN
+ 1 1850 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U11
+U 1 1 69A773B2
+P 1950 6250
+F 0 "U11" H 1950 6750 60 0000 C CNN
+F 1 "plot_v1" H 2150 6600 60 0000 C CNN
+F 2 "" H 1950 6250 60 0000 C CNN
+F 3 "" H 1950 6250 60 0000 C CNN
+ 1 1950 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U14
+U 1 1 69A77463
+P 2050 6600
+F 0 "U14" H 2050 7100 60 0000 C CNN
+F 1 "plot_v1" H 2250 6950 60 0000 C CNN
+F 2 "" H 2050 6600 60 0000 C CNN
+F 3 "" H 2050 6600 60 0000 C CNN
+ 1 2050 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U16
+U 1 1 69A774D8
+P 2200 6950
+F 0 "U16" H 2200 7450 60 0000 C CNN
+F 1 "plot_v1" H 2400 7300 60 0000 C CNN
+F 2 "" H 2200 6950 60 0000 C CNN
+F 3 "" H 2200 6950 60 0000 C CNN
+ 1 2200 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U17
+U 1 1 69A7754F
+P 2350 7300
+F 0 "U17" H 2350 7800 60 0000 C CNN
+F 1 "plot_v1" H 2550 7650 60 0000 C CNN
+F 2 "" H 2350 7300 60 0000 C CNN
+F 3 "" H 2350 7300 60 0000 C CNN
+ 1 2350 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U18
+U 1 1 69A775CC
+P 2500 7600
+F 0 "U18" H 2500 8100 60 0000 C CNN
+F 1 "plot_v1" H 2700 7950 60 0000 C CNN
+F 2 "" H 2500 7600 60 0000 C CNN
+F 3 "" H 2500 7600 60 0000 C CNN
+ 1 2500 7600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U20
+U 1 1 69A77649
+P 3550 5700
+F 0 "U20" H 3550 6200 60 0000 C CNN
+F 1 "plot_v1" H 3750 6050 60 0000 C CNN
+F 2 "" H 3550 5700 60 0000 C CNN
+F 3 "" H 3550 5700 60 0000 C CNN
+ 1 3550 5700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1950 3800 1950 3900
+Connection ~ 1950 3900
+Wire Wire Line
+ 1800 4100 1800 4250
+Wire Wire Line
+ 1800 4250 1850 4250
+Connection ~ 1850 4250
+Wire Wire Line
+ 2150 4400 2150 4550
+Connection ~ 2150 4550
+Wire Wire Line
+ 1750 4800 1750 4900
+Wire Wire Line
+ 1750 5450 1750 5500
+Connection ~ 1750 5500
+Wire Wire Line
+ 1850 5750 1850 5850
+Connection ~ 1850 5850
+Wire Wire Line
+ 1950 6050 1950 6150
+Connection ~ 1950 6150
+Wire Wire Line
+ 2050 6400 2050 6500
+Connection ~ 2050 6500
+Wire Wire Line
+ 2200 6750 2200 6850
+Connection ~ 2200 6850
+Wire Wire Line
+ 2350 7100 2350 7200
+Wire Wire Line
+ 2350 7200 2400 7200
+Connection ~ 2400 7200
+Wire Wire Line
+ 2500 7400 2500 7500
+Connection ~ 2500 7500
+Wire Wire Line
+ 3550 5500 3350 5500
+Wire Wire Line
+ 3350 5500 3350 5550
+Connection ~ 3350 5550
+$Comp
+L plot_v1 U28
+U 1 1 69A7D061
+P 10050 1100
+F 0 "U28" H 10050 1600 60 0000 C CNN
+F 1 "plot_v1" H 10250 1450 60 0000 C CNN
+F 2 "" H 10050 1100 60 0000 C CNN
+F 3 "" H 10050 1100 60 0000 C CNN
+ 1 10050 1100
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U29
+U 1 1 69A7D0F0
+P 10050 1350
+F 0 "U29" H 10050 1850 60 0000 C CNN
+F 1 "plot_v1" H 10250 1700 60 0000 C CNN
+F 2 "" H 10050 1350 60 0000 C CNN
+F 3 "" H 10050 1350 60 0000 C CNN
+ 1 10050 1350
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U30
+U 1 1 69A7D1F2
+P 10050 1600
+F 0 "U30" H 10050 2100 60 0000 C CNN
+F 1 "plot_v1" H 10250 1950 60 0000 C CNN
+F 2 "" H 10050 1600 60 0000 C CNN
+F 3 "" H 10050 1600 60 0000 C CNN
+ 1 10050 1600
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U31
+U 1 1 69A7D1F9
+P 10050 1850
+F 0 "U31" H 10050 2350 60 0000 C CNN
+F 1 "plot_v1" H 10250 2200 60 0000 C CNN
+F 2 "" H 10050 1850 60 0000 C CNN
+F 3 "" H 10050 1850 60 0000 C CNN
+ 1 10050 1850
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U32
+U 1 1 69A7D251
+P 10050 2150
+F 0 "U32" H 10050 2650 60 0000 C CNN
+F 1 "plot_v1" H 10250 2500 60 0000 C CNN
+F 2 "" H 10050 2150 60 0000 C CNN
+F 3 "" H 10050 2150 60 0000 C CNN
+ 1 10050 2150
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U33
+U 1 1 69A7D258
+P 10050 2400
+F 0 "U33" H 10050 2900 60 0000 C CNN
+F 1 "plot_v1" H 10250 2750 60 0000 C CNN
+F 2 "" H 10050 2400 60 0000 C CNN
+F 3 "" H 10050 2400 60 0000 C CNN
+ 1 10050 2400
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U34
+U 1 1 69A7D2C6
+P 10050 2650
+F 0 "U34" H 10050 3150 60 0000 C CNN
+F 1 "plot_v1" H 10250 3000 60 0000 C CNN
+F 2 "" H 10050 2650 60 0000 C CNN
+F 3 "" H 10050 2650 60 0000 C CNN
+ 1 10050 2650
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U35
+U 1 1 69A7D2CD
+P 10050 2900
+F 0 "U35" H 10050 3400 60 0000 C CNN
+F 1 "plot_v1" H 10250 3250 60 0000 C CNN
+F 2 "" H 10050 2900 60 0000 C CNN
+F 3 "" H 10050 2900 60 0000 C CNN
+ 1 10050 2900
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U36
+U 1 1 69A7D526
+P 10050 3500
+F 0 "U36" H 10050 4000 60 0000 C CNN
+F 1 "plot_v1" H 10250 3850 60 0000 C CNN
+F 2 "" H 10050 3500 60 0000 C CNN
+F 3 "" H 10050 3500 60 0000 C CNN
+ 1 10050 3500
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U37
+U 1 1 69A7D52D
+P 10050 3750
+F 0 "U37" H 10050 4250 60 0000 C CNN
+F 1 "plot_v1" H 10250 4100 60 0000 C CNN
+F 2 "" H 10050 3750 60 0000 C CNN
+F 3 "" H 10050 3750 60 0000 C CNN
+ 1 10050 3750
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U38
+U 1 1 69A7D534
+P 10050 4000
+F 0 "U38" H 10050 4500 60 0000 C CNN
+F 1 "plot_v1" H 10250 4350 60 0000 C CNN
+F 2 "" H 10050 4000 60 0000 C CNN
+F 3 "" H 10050 4000 60 0000 C CNN
+ 1 10050 4000
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U39
+U 1 1 69A7D53B
+P 10050 4250
+F 0 "U39" H 10050 4750 60 0000 C CNN
+F 1 "plot_v1" H 10250 4600 60 0000 C CNN
+F 2 "" H 10050 4250 60 0000 C CNN
+F 3 "" H 10050 4250 60 0000 C CNN
+ 1 10050 4250
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U40
+U 1 1 69A7D542
+P 10050 4550
+F 0 "U40" H 10050 5050 60 0000 C CNN
+F 1 "plot_v1" H 10250 4900 60 0000 C CNN
+F 2 "" H 10050 4550 60 0000 C CNN
+F 3 "" H 10050 4550 60 0000 C CNN
+ 1 10050 4550
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U41
+U 1 1 69A7D549
+P 10050 4800
+F 0 "U41" H 10050 5300 60 0000 C CNN
+F 1 "plot_v1" H 10250 5150 60 0000 C CNN
+F 2 "" H 10050 4800 60 0000 C CNN
+F 3 "" H 10050 4800 60 0000 C CNN
+ 1 10050 4800
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U42
+U 1 1 69A7D550
+P 10050 5050
+F 0 "U42" H 10050 5550 60 0000 C CNN
+F 1 "plot_v1" H 10250 5400 60 0000 C CNN
+F 2 "" H 10050 5050 60 0000 C CNN
+F 3 "" H 10050 5050 60 0000 C CNN
+ 1 10050 5050
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U43
+U 1 1 69A7D557
+P 10050 5300
+F 0 "U43" H 10050 5800 60 0000 C CNN
+F 1 "plot_v1" H 10250 5650 60 0000 C CNN
+F 2 "" H 10050 5300 60 0000 C CNN
+F 3 "" H 10050 5300 60 0000 C CNN
+ 1 10050 5300
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U27
+U 1 1 69A7DA53
+P 10000 700
+F 0 "U27" H 10000 1200 60 0000 C CNN
+F 1 "plot_v1" H 10200 1050 60 0000 C CNN
+F 2 "" H 10000 700 60 0000 C CNN
+F 3 "" H 10000 700 60 0000 C CNN
+ 1 10000 700
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 7600 2550 7600 650
+Wire Wire Line
+ 7600 650 10200 650
+Wire Wire Line
+ 10200 650 10200 700
+Wire Wire Line
+ 7600 2950 7650 2950
+Wire Wire Line
+ 7650 2950 7650 1100
+Wire Wire Line
+ 7650 1100 10250 1100
+Wire Wire Line
+ 7600 3050 7700 3050
+Wire Wire Line
+ 7700 3050 7700 1350
+Wire Wire Line
+ 7700 1350 10250 1350
+Wire Wire Line
+ 7600 3150 7750 3150
+Wire Wire Line
+ 7750 3150 7750 1600
+Wire Wire Line
+ 7750 1600 10250 1600
+Wire Wire Line
+ 7600 3250 7800 3250
+Wire Wire Line
+ 7800 3250 7800 1850
+Wire Wire Line
+ 7800 1850 10250 1850
+Wire Wire Line
+ 7600 3350 7850 3350
+Wire Wire Line
+ 7850 3350 7850 2150
+Wire Wire Line
+ 7850 2150 10250 2150
+Wire Wire Line
+ 7600 3450 7900 3450
+Wire Wire Line
+ 7900 3450 7900 2400
+Wire Wire Line
+ 7900 2400 10250 2400
+Wire Wire Line
+ 7600 3550 7950 3550
+Wire Wire Line
+ 7950 3550 7950 2650
+Wire Wire Line
+ 7950 2650 10250 2650
+Wire Wire Line
+ 7600 3650 8000 3650
+Wire Wire Line
+ 8000 3650 8000 2900
+Wire Wire Line
+ 8000 2900 10250 2900
+Wire Wire Line
+ 8100 4000 8250 4000
+Wire Wire Line
+ 8250 4000 8250 3500
+Wire Wire Line
+ 8250 3500 10250 3500
+Wire Wire Line
+ 8100 4100 8350 4100
+Wire Wire Line
+ 8350 4100 8350 3750
+Wire Wire Line
+ 8350 3750 10250 3750
+Wire Wire Line
+ 8100 4200 8450 4200
+Wire Wire Line
+ 8450 4200 8450 4000
+Wire Wire Line
+ 8450 4000 10250 4000
+Wire Wire Line
+ 8100 4300 10250 4300
+Wire Wire Line
+ 10250 4300 10250 4250
+Wire Wire Line
+ 8100 4700 8100 5300
+Wire Wire Line
+ 8100 5300 10250 5300
+Wire Wire Line
+ 8100 4600 8150 4600
+Wire Wire Line
+ 8150 4600 8150 5050
+Wire Wire Line
+ 8150 5050 10250 5050
+Wire Wire Line
+ 8100 4500 8200 4500
+Wire Wire Line
+ 8200 4500 8200 4800
+Wire Wire Line
+ 8200 4800 10250 4800
+Wire Wire Line
+ 8100 4400 8250 4400
+Wire Wire Line
+ 8250 4400 8250 4550
+Wire Wire Line
+ 8250 4550 10250 4550
+Text GLabel 9300 650 1 60 Input ~ 0
+ou_valid0
+Text GLabel 9450 1100 1 60 Input ~ 0
+q7
+Text GLabel 9750 1350 1 60 Input ~ 0
+q6
+Text GLabel 9650 1600 1 60 Input ~ 0
+q5
+Text GLabel 9550 1850 1 60 Input ~ 0
+q4
+Text GLabel 9550 2150 1 60 Input ~ 0
+q3
+Text GLabel 9700 2400 1 60 Input ~ 0
+q2
+Text GLabel 9600 2650 1 60 Input ~ 0
+q1
+Text GLabel 9600 2900 1 60 Input ~ 0
+q0
+Text GLabel 9150 3500 1 60 Input ~ 0
+r7
+Text GLabel 9350 3750 1 60 Input ~ 0
+r6
+Text GLabel 9550 4000 1 60 Input ~ 0
+r5
+Text GLabel 9600 4300 1 60 Input ~ 0
+r4
+Text GLabel 9750 4550 1 60 Input ~ 0
+r3
+Text GLabel 9700 4800 1 60 Input ~ 0
+r2
+Text GLabel 9700 5050 1 60 Input ~ 0
+r1
+Text GLabel 9850 5300 1 60 Input ~ 0
+r0
+Wire Wire Line
+ 550 1200 800 1200
+Wire Wire Line
+ 800 1200 800 1350
+$Comp
+L PWR_FLAG #FLG?
+U 1 1 69A84ADD
+P 750 1050
+F 0 "#FLG?" H 750 1125 50 0001 C CNN
+F 1 "PWR_FLAG" H 750 1200 50 0000 C CNN
+F 2 "" H 750 1050 50 0001 C CNN
+F 3 "" H 750 1050 50 0001 C CNN
+ 1 750 1050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 750 1050 750 1200
+Connection ~ 750 1200
+$EndSCHEMATC
diff --git a/fossee/divider/divider/divider.v b/fossee/divider/divider/divider.v
new file mode 100644
index 000000000..4da9b5078
--- /dev/null
+++ b/fossee/divider/divider/divider.v
@@ -0,0 +1,87 @@
+module divider (
+ input wire clk,
+ input wire rst,
+ input wire in_valid,
+ input wire [7:0] dividend,
+ input wire [7:0] divisor,
+ output wire out_valid,
+ output wire [7:0] quotient,
+ output wire [7:0] remainder
+);
+
+ // Pipeline registers
+ reg valid_pipe [0:8];
+ reg [7:0] divisor_pipe [0:8];
+ reg [7:0] quotient_pipe [0:8];
+ reg [8:0] remainder_pipe [0:8];
+ reg div0_pipe [0:8]; // NEW: divide-by-zero pipeline
+
+ // Stage 0 (Input stage)
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ valid_pipe[0] <= 0;
+ quotient_pipe[0] <= 0;
+ remainder_pipe[0] <= 0;
+ divisor_pipe[0] <= 0;
+ div0_pipe[0] <= 0;
+ end
+ else begin
+ valid_pipe[0] <= in_valid;
+ quotient_pipe[0] <= dividend;
+ remainder_pipe[0] <= 0;
+ divisor_pipe[0] <= divisor;
+ div0_pipe[0] <= (divisor == 0); // detect divide-by-zero
+ end
+ end
+
+ // Pipeline stages
+ genvar s;
+ generate
+ for (s = 1; s <= 8; s = s + 1) begin : PIPE
+
+ reg [8:0] rem_shift;
+ reg [7:0] quot_shift;
+
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ valid_pipe[s] <= 0;
+ quotient_pipe[s] <= 0;
+ remainder_pipe[s] <= 0;
+ divisor_pipe[s] <= 0;
+ div0_pipe[s] <= 0;
+ end
+ else begin
+ valid_pipe[s] <= valid_pipe[s-1];
+ divisor_pipe[s] <= divisor_pipe[s-1];
+ div0_pipe[s] <= div0_pipe[s-1];
+
+ // If divide-by-zero, just propagate
+ if (div0_pipe[s-1]) begin
+ quotient_pipe[s] <= 0;
+ remainder_pipe[s] <= quotient_pipe[s-1];
+ end
+ else begin
+ // Normal division
+ rem_shift = {remainder_pipe[s-1][7:0], quotient_pipe[s-1][7]};
+ quot_shift = {quotient_pipe[s-1][6:0], 1'b0};
+
+ if (rem_shift >= divisor_pipe[s-1]) begin
+ remainder_pipe[s] <= rem_shift - divisor_pipe[s-1];
+ quotient_pipe[s] <= {quot_shift[7:1], 1'b1};
+ end
+ else begin
+ remainder_pipe[s] <= rem_shift;
+ quotient_pipe[s] <= {quot_shift[7:1], 1'b0};
+ end
+ end
+ end
+ end
+
+ end
+ endgenerate
+
+ assign out_valid = valid_pipe[8];
+ assign quotient = quotient_pipe[8];
+ assign remainder = remainder_pipe[8][7:0];
+
+endmodule
\ No newline at end of file
diff --git a/fossee/divider/divider/divider_Previous_Values.xml b/fossee/divider/divider/divider_Previous_Values.xml
new file mode 100644
index 000000000..2d45ad3b3
--- /dev/null
+++ b/fossee/divider/divider/divider_Previous_Values.xml
@@ -0,0 +1 @@
+pulse010.01ns0.001ns0.001ns10ns30nspulse010.001ns0.001ns0.001ns15ns300nsdcdcdcdcdcdcdcdcdcdcdcdcdcdcdcdcdcdivideradc_bridgeadc_bridgeadc_bridgedac_bridgedac_bridgedac_bridgetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01500secnsns
\ No newline at end of file
diff --git a/fossee/divider/divider_algorithm.png b/fossee/divider/divider_algorithm.png
new file mode 100644
index 000000000..8fb9b8aa9
Binary files /dev/null and b/fossee/divider/divider_algorithm.png differ
diff --git a/fossee/divider/divider_cmd.png b/fossee/divider/divider_cmd.png
new file mode 100644
index 000000000..d35fb2b63
Binary files /dev/null and b/fossee/divider/divider_cmd.png differ
diff --git a/fossee/divider/divider_dividend.png b/fossee/divider/divider_dividend.png
new file mode 100644
index 000000000..8c3b2ab05
Binary files /dev/null and b/fossee/divider/divider_dividend.png differ
diff --git a/fossee/divider/divider_divisor.png b/fossee/divider/divider_divisor.png
new file mode 100644
index 000000000..7b2073160
Binary files /dev/null and b/fossee/divider/divider_divisor.png differ
diff --git a/fossee/divider/divider_ip.png b/fossee/divider/divider_ip.png
new file mode 100644
index 000000000..94a5dd02a
Binary files /dev/null and b/fossee/divider/divider_ip.png differ
diff --git a/fossee/divider/divider_module.png b/fossee/divider/divider_module.png
new file mode 100644
index 000000000..ab79c9f81
Binary files /dev/null and b/fossee/divider/divider_module.png differ
diff --git a/fossee/divider/divider_quiotiet.png b/fossee/divider/divider_quiotiet.png
new file mode 100644
index 000000000..9e2489fa6
Binary files /dev/null and b/fossee/divider/divider_quiotiet.png differ
diff --git a/fossee/divider/divider_remainder.png b/fossee/divider/divider_remainder.png
new file mode 100644
index 000000000..11e16bd1b
Binary files /dev/null and b/fossee/divider/divider_remainder.png differ
diff --git a/fossee/divider/divider_schematic.png b/fossee/divider/divider_schematic.png
new file mode 100644
index 000000000..4dd9fe4af
Binary files /dev/null and b/fossee/divider/divider_schematic.png differ
diff --git a/fossee/divider/divider_vivado.png b/fossee/divider/divider_vivado.png
new file mode 100644
index 000000000..648aaa28c
Binary files /dev/null and b/fossee/divider/divider_vivado.png differ
diff --git a/fossee/divider/tb.v b/fossee/divider/tb.v
new file mode 100644
index 000000000..303bb87af
--- /dev/null
+++ b/fossee/divider/tb.v
@@ -0,0 +1,68 @@
+module tb_divider_8bit_pipeline;
+
+ reg clk, rst;
+ reg in_valid;
+ reg [7:0] dividend, divisor;
+ wire out_valid;
+ wire [7:0] quotient, remainder;
+
+ divider_8bit_pipeline DUT (
+ .clk(clk),
+ .rst(rst),
+ .in_valid(in_valid),
+ .dividend(dividend),
+ .divisor(divisor),
+ .out_valid(out_valid),
+ .quotient(quotient),
+ .remainder(remainder)
+ );
+
+ // 100 MHz clock
+ always #5 clk = ~clk;
+
+ task send_div;
+ input [7:0] a;
+ input [7:0] b;
+ begin
+ @(posedge clk);
+ dividend <= a;
+ divisor <= b;
+ in_valid <= 1'b1;
+
+ @(posedge clk);
+ in_valid <= 1'b0;
+ end
+ endtask
+
+ initial begin
+ clk = 0;
+ rst = 1;
+ in_valid = 0;
+ dividend = 0;
+ divisor = 0;
+
+ // reset
+ repeat (5) @(posedge clk);
+ rst = 0;
+
+ // Apply inputs
+ send_div(8'd10, 8'd10);
+ send_div(8'd25, 8'd5);
+ send_div(8'd15, 8'd4);
+ send_div(8'd9, 8'd2);
+ send_div(8'd100, 8'd7);
+
+ // Wait enough clocks for pipeline to flush
+ repeat (20) @(posedge clk);
+
+ $finish;
+ end
+
+ // Monitor outputs
+ always @(posedge clk) begin
+ if (out_valid) begin
+ $display("Time=%0t Q=%0d R=%0d", $time, quotient, remainder);
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/fossee/fir_filter/Transposed-direct-form-TDF-FIR-filter.png b/fossee/fir_filter/Transposed-direct-form-TDF-FIR-filter.png
new file mode 100644
index 000000000..84549a8e4
Binary files /dev/null and b/fossee/fir_filter/Transposed-direct-form-TDF-FIR-filter.png differ
diff --git a/fossee/fir_filter/fir_filter/analysis b/fossee/fir_filter/fir_filter/analysis
new file mode 100644
index 000000000..f7cfa973f
--- /dev/null
+++ b/fossee/fir_filter/fir_filter/analysis
@@ -0,0 +1 @@
+.tran 1e-09 1.717e-06 0e-09
\ No newline at end of file
diff --git a/fossee/fir_filter/fir_filter/fir_filter-cache.lib b/fossee/fir_filter/fir_filter/fir_filter-cache.lib
new file mode 100644
index 000000000..e86737308
--- /dev/null
+++ b/fossee/fir_filter/fir_filter/fir_filter-cache.lib
@@ -0,0 +1,168 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# fir_filter
+#
+DEF fir_filter U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "fir_filter" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 800 0 1 0 N
+X clk0 1 2150 1900 200 R 50 50 1 1 I
+X rst0 2 2150 1800 200 R 50 50 1 1 I
+X x7 3 2150 1700 200 R 50 50 1 1 I
+X x6 4 2150 1600 200 R 50 50 1 1 I
+X x5 5 2150 1500 200 R 50 50 1 1 I
+X x4 6 2150 1400 200 R 50 50 1 1 I
+X x3 7 2150 1300 200 R 50 50 1 1 I
+X x2 8 2150 1200 200 R 50 50 1 1 I
+X x1 9 2150 1100 200 R 50 50 1 1 I
+X x0 10 2150 1000 200 R 50 50 1 1 I
+X y7 11 3550 1900 200 L 50 50 1 1 O
+X y6 12 3550 1800 200 L 50 50 1 1 O
+X y5 13 3550 1700 200 L 50 50 1 1 O
+X y4 14 3550 1600 200 L 50 50 1 1 O
+X y3 15 3550 1500 200 L 50 50 1 1 O
+X y2 16 3550 1400 200 L 50 50 1 1 O
+X y1 17 3550 1300 200 L 50 50 1 1 O
+X y0 18 3550 1200 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/fossee/fir_filter/fir_filter/fir_filter.cir b/fossee/fir_filter/fir_filter/fir_filter.cir
new file mode 100644
index 000000000..5900f2502
--- /dev/null
+++ b/fossee/fir_filter/fir_filter/fir_filter.cir
@@ -0,0 +1,32 @@
+* C:\Users\VLSI\eSim-Workspace\fir_filter\fir_filter.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 28/02/2026 17:24:53
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ fir_filter
+U3 x7 x6 x5 x4 x3 x2 x1 x0 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ adc_bridge_8
+U2 clk0 rst0 Net-_U1-Pad1_ Net-_U1-Pad2_ adc_bridge_2
+U4 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ y7 y6 y5 y4 y3 y2 y1 y0 dac_bridge_8
+v9 clk0 GND pulse
+v10 rst0 GND pulse
+v1 x7 GND pulse
+v2 x6 GND pulse
+v3 x5 GND pulse
+v4 x4 GND pulse
+v5 x3 GND pulse
+v6 x2 GND pulse
+v7 x1 GND pulse
+v8 x0 GND pulse
+U6 y7 plot_v1
+U7 y6 plot_v1
+U11 y5 plot_v1
+U12 y4 plot_v1
+U9 y3 plot_v1
+U10 y2 plot_v1
+U8 y1 plot_v1
+U5 y0 plot_v1
+
+.end
diff --git a/fossee/fir_filter/fir_filter/fir_filter.cir.out b/fossee/fir_filter/fir_filter/fir_filter.cir.out
new file mode 100644
index 000000000..8cd64b156
--- /dev/null
+++ b/fossee/fir_filter/fir_filter/fir_filter.cir.out
@@ -0,0 +1,46 @@
+* c:\users\vlsi\esim-workspace\fir_filter\fir_filter.cir
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ fir_filter
+* u3 x7 x6 x5 x4 x3 x2 x1 x0 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ adc_bridge_8
+* u2 clk0 rst0 net-_u1-pad1_ net-_u1-pad2_ adc_bridge_2
+* u4 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ y7 y6 y5 y4 y3 y2 y1 y0 dac_bridge_8
+v9 clk0 gnd pulse(0 5 0.01n 0.01n 0.01n 70n 100n)
+v10 rst0 gnd pulse(0 5 0.01n 0.01n 0.01n 40n 50n)
+v1 x7 gnd pulse(0 5 0.01n 0.01n 0.01n 50n 100n)
+v2 x6 gnd pulse(0 5 0.01n 0.01n 0.01n 30n 50n)
+v3 x5 gnd pulse(0 5 0.01n 0.01n 0.01n 1n 2n)
+v4 x4 gnd pulse(0 5 0.01n 0.01n 0.01n 1.2u 3u)
+v5 x3 gnd pulse(0 5 0.01n 0.01n 0.01n 60n 70n)
+v6 x2 gnd pulse(0 5 0.01n 0.01n 0.01n 20n 40n)
+v7 x1 gnd pulse(0 5 0.01n 0.01n 0.01n 570n 1.2u)
+v8 x0 gnd pulse(0 5 0.01n 0.01n 0.01n 2.9u 3u)
+* u6 y7 plot_v1
+* u7 y6 plot_v1
+* u11 y5 plot_v1
+* u12 y4 plot_v1
+* u9 y3 plot_v1
+* u10 y2 plot_v1
+* u8 y1 plot_v1
+* u5 y0 plot_v1
+a1 [net-_u1-pad1_ ] [net-_u1-pad2_ ] [net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ ] [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ ] u1
+a2 [x7 x6 x5 x4 x3 x2 x1 x0 ] [net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ ] u3
+a3 [clk0 rst0 ] [net-_u1-pad1_ net-_u1-pad2_ ] u2
+a4 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ ] [y7 y6 y5 y4 y3 y2 y1 y0 ] u4
+* Schematic Name: fir_filter, NgSpice Name: fir_filter
+.model u1 fir_filter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 1e-09 1.717e-06 0e-09
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(y7)+6 v(y6)+12v(y5)+18 v(y4)+24 v(y3)+30 v(y2)+36 v(y1)+42 v(y0)
+.endc
+.end
diff --git a/fossee/fir_filter/fir_filter/fir_filter.pro b/fossee/fir_filter/fir_filter/fir_filter.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/fossee/fir_filter/fir_filter/fir_filter.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/fossee/fir_filter/fir_filter/fir_filter.proj b/fossee/fir_filter/fir_filter/fir_filter.proj
new file mode 100644
index 000000000..643409e71
--- /dev/null
+++ b/fossee/fir_filter/fir_filter/fir_filter.proj
@@ -0,0 +1 @@
+schematicFile fir_filter.sch
diff --git a/fossee/fir_filter/fir_filter/fir_filter.sch b/fossee/fir_filter/fir_filter/fir_filter.sch
new file mode 100644
index 000000000..a21829b7c
--- /dev/null
+++ b/fossee/fir_filter/fir_filter/fir_filter.sch
@@ -0,0 +1,629 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:fir_filter-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L fir_filter U?
+U 1 1 69A2D363
+P 3000 4700
+F 0 "U?" H 5850 6500 60 0000 C CNN
+F 1 "fir_filter" H 5850 6700 60 0000 C CNN
+F 2 "" H 5850 6650 60 0000 C CNN
+F 3 "" H 5850 6650 60 0000 C CNN
+ 1 3000 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_8 U?
+U 1 1 69A2D3F4
+P 4200 3200
+F 0 "U?" H 4200 3200 60 0000 C CNN
+F 1 "adc_bridge_8" H 4200 3350 60 0000 C CNN
+F 2 "" H 4200 3200 60 0000 C CNN
+F 3 "" H 4200 3200 60 0000 C CNN
+ 1 4200 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_2 U?
+U 1 1 69A2D43D
+P 4200 2700
+F 0 "U?" H 4200 2700 60 0000 C CNN
+F 1 "adc_bridge_2" H 4200 2850 60 0000 C CNN
+F 2 "" H 4200 2700 60 0000 C CNN
+F 3 "" H 4200 2700 60 0000 C CNN
+ 1 4200 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_8 U?
+U 1 1 69A2D4C9
+P 7400 2850
+F 0 "U?" H 7400 2850 60 0000 C CNN
+F 1 "dac_bridge_8" H 7400 3000 60 0000 C CNN
+F 2 "" H 7400 2850 60 0000 C CNN
+F 3 "" H 7400 2850 60 0000 C CNN
+ 1 7400 2850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4750 2650 5150 2650
+Wire Wire Line
+ 5150 2650 5150 2800
+Wire Wire Line
+ 4750 2750 5100 2750
+Wire Wire Line
+ 5100 2750 5100 2900
+Wire Wire Line
+ 5100 2900 5150 2900
+Wire Wire Line
+ 4750 3150 4800 3150
+Wire Wire Line
+ 4800 3150 4800 3000
+Wire Wire Line
+ 4800 3000 5150 3000
+Wire Wire Line
+ 4750 3250 4850 3250
+Wire Wire Line
+ 4850 3250 4850 3100
+Wire Wire Line
+ 4850 3100 5150 3100
+Wire Wire Line
+ 4750 3350 4900 3350
+Wire Wire Line
+ 4900 3350 4900 3200
+Wire Wire Line
+ 4900 3200 5150 3200
+Wire Wire Line
+ 4750 3450 4950 3450
+Wire Wire Line
+ 4950 3450 4950 3300
+Wire Wire Line
+ 4950 3300 5150 3300
+Wire Wire Line
+ 4750 3550 5000 3550
+Wire Wire Line
+ 5000 3550 5000 3400
+Wire Wire Line
+ 5000 3400 5150 3400
+Wire Wire Line
+ 4750 3650 5050 3650
+Wire Wire Line
+ 5050 3650 5050 3500
+Wire Wire Line
+ 5050 3500 5150 3500
+Wire Wire Line
+ 4750 3750 5100 3750
+Wire Wire Line
+ 5100 3750 5100 3600
+Wire Wire Line
+ 5100 3600 5150 3600
+Wire Wire Line
+ 4750 3850 5150 3850
+Wire Wire Line
+ 5150 3850 5150 3700
+Wire Wire Line
+ 6550 2800 6800 2800
+Wire Wire Line
+ 6550 2900 6800 2900
+Wire Wire Line
+ 6550 3000 6800 3000
+Wire Wire Line
+ 6550 3100 6800 3100
+Wire Wire Line
+ 6550 3200 6800 3200
+Wire Wire Line
+ 6550 3300 6800 3300
+Wire Wire Line
+ 6550 3400 6800 3400
+Wire Wire Line
+ 6550 3500 6800 3500
+Wire Wire Line
+ 7950 2800 8350 2800
+Wire Wire Line
+ 8350 2800 8350 2700
+Wire Wire Line
+ 7950 2900 8450 2900
+Wire Wire Line
+ 8450 2900 8450 2700
+Wire Wire Line
+ 7950 3000 8700 3000
+Wire Wire Line
+ 8700 3000 8700 2700
+Wire Wire Line
+ 7950 3100 8800 3100
+Wire Wire Line
+ 8800 3100 8800 3050
+Wire Wire Line
+ 7950 3200 8800 3200
+Wire Wire Line
+ 8800 3200 8800 3250
+Wire Wire Line
+ 7950 3300 8650 3300
+Wire Wire Line
+ 8650 3300 8650 3350
+Wire Wire Line
+ 7950 3400 8450 3400
+Wire Wire Line
+ 7950 3500 8250 3500
+Wire Wire Line
+ 8250 3500 8250 3550
+Text GLabel 8150 2800 1 60 Input ~ 0
+y7
+Text GLabel 8250 2900 1 60 Input ~ 0
+y6
+Text GLabel 8050 3000 1 60 Input ~ 0
+y5
+Text GLabel 8400 3100 1 60 Input ~ 0
+y4
+Text GLabel 8200 3200 1 60 Input ~ 0
+y3
+Text GLabel 8450 3300 1 60 Input ~ 0
+y2
+Text GLabel 8100 3400 1 60 Input ~ 0
+y1
+Text GLabel 8050 3500 1 60 Input ~ 0
+y0
+Wire Wire Line
+ 2950 2650 3600 2650
+Wire Wire Line
+ 2450 2750 3600 2750
+Wire Wire Line
+ 3600 3150 2950 3150
+Wire Wire Line
+ 3600 3250 2950 3250
+Wire Wire Line
+ 2350 3350 3600 3350
+Wire Wire Line
+ 2500 3450 3600 3450
+Wire Wire Line
+ 2550 3550 3600 3550
+Wire Wire Line
+ 2600 3650 3600 3650
+Wire Wire Line
+ 2700 3750 3600 3750
+Wire Wire Line
+ 3600 3850 2950 3850
+Text GLabel 3550 2650 1 60 Input ~ 0
+clk0
+Text GLabel 3250 2750 1 60 Input ~ 0
+rst0
+Text GLabel 3600 3150 1 60 Input ~ 0
+x7
+Text GLabel 3450 3250 1 60 Input ~ 0
+x6
+Text GLabel 3350 3350 1 60 Input ~ 0
+x5
+Text GLabel 3200 3450 1 60 Input ~ 0
+x4
+Text GLabel 3100 3550 1 60 Input ~ 0
+x3
+Text GLabel 3400 3650 1 60 Input ~ 0
+x2
+Text GLabel 3550 3750 1 60 Input ~ 0
+x1
+Text GLabel 3350 3850 1 60 Input ~ 0
+x0
+$Comp
+L pulse v?
+U 1 1 69A2E898
+P 2000 2100
+F 0 "v?" H 1800 2200 60 0000 C CNN
+F 1 "pulse" H 1800 2050 60 0000 C CNN
+F 2 "R1" H 1700 2100 60 0000 C CNN
+F 3 "" H 2000 2100 60 0000 C CNN
+ 1 2000 2100
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A2E8D7
+P 2000 2450
+F 0 "v?" H 1800 2550 60 0000 C CNN
+F 1 "pulse" H 1800 2400 60 0000 C CNN
+F 2 "R1" H 1700 2450 60 0000 C CNN
+F 3 "" H 2000 2450 60 0000 C CNN
+ 1 2000 2450
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A2E9C6
+P 1850 3050
+F 0 "v?" H 1650 3150 60 0000 C CNN
+F 1 "pulse" H 1650 3000 60 0000 C CNN
+F 2 "R1" H 1550 3050 60 0000 C CNN
+F 3 "" H 1850 3050 60 0000 C CNN
+ 1 1850 3050
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A2E9CD
+P 1850 3400
+F 0 "v?" H 1650 3500 60 0000 C CNN
+F 1 "pulse" H 1650 3350 60 0000 C CNN
+F 2 "R1" H 1550 3400 60 0000 C CNN
+F 3 "" H 1850 3400 60 0000 C CNN
+ 1 1850 3400
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A2EA98
+P 1850 3700
+F 0 "v?" H 1650 3800 60 0000 C CNN
+F 1 "pulse" H 1650 3650 60 0000 C CNN
+F 2 "R1" H 1550 3700 60 0000 C CNN
+F 3 "" H 1850 3700 60 0000 C CNN
+ 1 1850 3700
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A2EA9F
+P 1850 4050
+F 0 "v?" H 1650 4150 60 0000 C CNN
+F 1 "pulse" H 1650 4000 60 0000 C CNN
+F 2 "R1" H 1550 4050 60 0000 C CNN
+F 3 "" H 1850 4050 60 0000 C CNN
+ 1 1850 4050
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A2EB46
+P 1850 4450
+F 0 "v?" H 1650 4550 60 0000 C CNN
+F 1 "pulse" H 1650 4400 60 0000 C CNN
+F 2 "R1" H 1550 4450 60 0000 C CNN
+F 3 "" H 1850 4450 60 0000 C CNN
+ 1 1850 4450
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A2EB4D
+P 1850 4800
+F 0 "v?" H 1650 4900 60 0000 C CNN
+F 1 "pulse" H 1650 4750 60 0000 C CNN
+F 2 "R1" H 1550 4800 60 0000 C CNN
+F 3 "" H 1850 4800 60 0000 C CNN
+ 1 1850 4800
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A2EB54
+P 1850 5100
+F 0 "v?" H 1650 5200 60 0000 C CNN
+F 1 "pulse" H 1650 5050 60 0000 C CNN
+F 2 "R1" H 1550 5100 60 0000 C CNN
+F 3 "" H 1850 5100 60 0000 C CNN
+ 1 1850 5100
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A2EB5B
+P 1850 5450
+F 0 "v?" H 1650 5550 60 0000 C CNN
+F 1 "pulse" H 1650 5400 60 0000 C CNN
+F 2 "R1" H 1550 5450 60 0000 C CNN
+F 3 "" H 1850 5450 60 0000 C CNN
+ 1 1850 5450
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 2300 3050 2950 3050
+Wire Wire Line
+ 2950 3050 2950 3150
+Wire Wire Line
+ 2300 3400 2300 3200
+Wire Wire Line
+ 2300 3200 2950 3200
+Wire Wire Line
+ 2950 3200 2950 3250
+Wire Wire Line
+ 2300 3700 2300 3450
+Wire Wire Line
+ 2300 3450 2350 3450
+Wire Wire Line
+ 2350 3450 2350 3350
+Wire Wire Line
+ 2300 4050 2500 4050
+Wire Wire Line
+ 2500 4050 2500 3450
+Wire Wire Line
+ 2300 4450 2550 4450
+Wire Wire Line
+ 2550 4450 2550 3550
+Wire Wire Line
+ 2300 4800 2600 4800
+Wire Wire Line
+ 2600 4800 2600 3650
+Wire Wire Line
+ 2300 5100 2700 5100
+Wire Wire Line
+ 2700 5100 2700 3750
+Wire Wire Line
+ 2300 5450 2950 5450
+Wire Wire Line
+ 2950 5450 2950 3850
+Wire Wire Line
+ 2450 2750 2450 2450
+Wire Wire Line
+ 2450 2100 2950 2100
+Wire Wire Line
+ 2950 2100 2950 2650
+$Comp
+L GND #PWR?
+U 1 1 69A2F1FC
+P 1550 2100
+F 0 "#PWR?" H 1550 1850 50 0001 C CNN
+F 1 "GND" H 1550 1950 50 0000 C CNN
+F 2 "" H 1550 2100 50 0001 C CNN
+F 3 "" H 1550 2100 50 0001 C CNN
+ 1 1550 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A2F26A
+P 1550 2450
+F 0 "#PWR?" H 1550 2200 50 0001 C CNN
+F 1 "GND" H 1550 2300 50 0000 C CNN
+F 2 "" H 1550 2450 50 0001 C CNN
+F 3 "" H 1550 2450 50 0001 C CNN
+ 1 1550 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A2F29A
+P 1400 3050
+F 0 "#PWR?" H 1400 2800 50 0001 C CNN
+F 1 "GND" H 1400 2900 50 0000 C CNN
+F 2 "" H 1400 3050 50 0001 C CNN
+F 3 "" H 1400 3050 50 0001 C CNN
+ 1 1400 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A2F2CA
+P 1400 3400
+F 0 "#PWR?" H 1400 3150 50 0001 C CNN
+F 1 "GND" H 1400 3250 50 0000 C CNN
+F 2 "" H 1400 3400 50 0001 C CNN
+F 3 "" H 1400 3400 50 0001 C CNN
+ 1 1400 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A2F2FA
+P 1400 3700
+F 0 "#PWR?" H 1400 3450 50 0001 C CNN
+F 1 "GND" H 1400 3550 50 0000 C CNN
+F 2 "" H 1400 3700 50 0001 C CNN
+F 3 "" H 1400 3700 50 0001 C CNN
+ 1 1400 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A2F32A
+P 1400 4050
+F 0 "#PWR?" H 1400 3800 50 0001 C CNN
+F 1 "GND" H 1400 3900 50 0000 C CNN
+F 2 "" H 1400 4050 50 0001 C CNN
+F 3 "" H 1400 4050 50 0001 C CNN
+ 1 1400 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A2F35A
+P 1400 4450
+F 0 "#PWR?" H 1400 4200 50 0001 C CNN
+F 1 "GND" H 1400 4300 50 0000 C CNN
+F 2 "" H 1400 4450 50 0001 C CNN
+F 3 "" H 1400 4450 50 0001 C CNN
+ 1 1400 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A2F6A8
+P 1400 4800
+F 0 "#PWR?" H 1400 4550 50 0001 C CNN
+F 1 "GND" H 1400 4650 50 0000 C CNN
+F 2 "" H 1400 4800 50 0001 C CNN
+F 3 "" H 1400 4800 50 0001 C CNN
+ 1 1400 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A2F6D8
+P 1400 5100
+F 0 "#PWR?" H 1400 4850 50 0001 C CNN
+F 1 "GND" H 1400 4950 50 0000 C CNN
+F 2 "" H 1400 5100 50 0001 C CNN
+F 3 "" H 1400 5100 50 0001 C CNN
+ 1 1400 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A2F708
+P 1350 5600
+F 0 "#PWR?" H 1350 5350 50 0001 C CNN
+F 1 "GND" H 1350 5450 50 0000 C CNN
+F 2 "" H 1350 5600 50 0001 C CNN
+F 3 "" H 1350 5600 50 0001 C CNN
+ 1 1350 5600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1400 5450 1350 5450
+Wire Wire Line
+ 1350 5450 1350 5600
+$Comp
+L PWR_FLAG #FLG?
+U 1 1 69A2F79A
+P 1100 5500
+F 0 "#FLG?" H 1100 5575 50 0001 C CNN
+F 1 "PWR_FLAG" H 1100 5650 50 0000 C CNN
+F 2 "" H 1100 5500 50 0001 C CNN
+F 3 "" H 1100 5500 50 0001 C CNN
+ 1 1100 5500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1100 5500 1350 5500
+Wire Wire Line
+ 1350 5500 1350 5550
+Connection ~ 1350 5550
+$Comp
+L plot_v1 U?
+U 1 1 69A2DCAB
+P 8350 2900
+F 0 "U?" H 8350 3400 60 0000 C CNN
+F 1 "plot_v1" H 8550 3250 60 0000 C CNN
+F 2 "" H 8350 2900 60 0000 C CNN
+F 3 "" H 8350 2900 60 0000 C CNN
+ 1 8350 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A2DCFE
+P 8450 2900
+F 0 "U?" H 8450 3400 60 0000 C CNN
+F 1 "plot_v1" H 8650 3250 60 0000 C CNN
+F 2 "" H 8450 2900 60 0000 C CNN
+F 3 "" H 8450 2900 60 0000 C CNN
+ 1 8450 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A2DD4B
+P 8700 2900
+F 0 "U?" H 8700 3400 60 0000 C CNN
+F 1 "plot_v1" H 8900 3250 60 0000 C CNN
+F 2 "" H 8700 2900 60 0000 C CNN
+F 3 "" H 8700 2900 60 0000 C CNN
+ 1 8700 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A2DD86
+P 8800 3250
+F 0 "U?" H 8800 3750 60 0000 C CNN
+F 1 "plot_v1" H 9000 3600 60 0000 C CNN
+F 2 "" H 8800 3250 60 0000 C CNN
+F 3 "" H 8800 3250 60 0000 C CNN
+ 1 8800 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A2DDCB
+P 8600 3250
+F 0 "U?" H 8600 3750 60 0000 C CNN
+F 1 "plot_v1" H 8800 3600 60 0000 C CNN
+F 2 "" H 8600 3250 60 0000 C CNN
+F 3 "" H 8600 3250 60 0000 C CNN
+ 1 8600 3250
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A2DE2A
+P 8650 3150
+F 0 "U?" H 8650 3650 60 0000 C CNN
+F 1 "plot_v1" H 8850 3500 60 0000 C CNN
+F 2 "" H 8650 3150 60 0000 C CNN
+F 3 "" H 8650 3150 60 0000 C CNN
+ 1 8650 3150
+ -1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A2DE9B
+P 8450 3600
+F 0 "U?" H 8450 4100 60 0000 C CNN
+F 1 "plot_v1" H 8650 3950 60 0000 C CNN
+F 2 "" H 8450 3600 60 0000 C CNN
+F 3 "" H 8450 3600 60 0000 C CNN
+ 1 8450 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A2DEEA
+P 8250 3750
+F 0 "U?" H 8250 4250 60 0000 C CNN
+F 1 "plot_v1" H 8450 4100 60 0000 C CNN
+F 2 "" H 8250 3750 60 0000 C CNN
+F 3 "" H 8250 3750 60 0000 C CNN
+ 1 8250 3750
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/fossee/fir_filter/fir_filter/fir_filter.v b/fossee/fir_filter/fir_filter/fir_filter.v
new file mode 100644
index 000000000..21ed5f9e7
--- /dev/null
+++ b/fossee/fir_filter/fir_filter/fir_filter.v
@@ -0,0 +1,67 @@
+module fir_filter (
+ input clk,
+ input rst,
+ input signed [7:0] x,
+ output signed [15:0] y
+);
+
+ // coefficients (symmetric low-pass)
+ parameter signed [7:0] b0 = 8'd1;
+ parameter signed [7:0] b1 = 8'd3;
+ parameter signed [7:0] b2 = 8'd6;
+ parameter signed [7:0] b3 = 8'd10;
+ parameter signed [7:0] b4 = 8'd15;
+ parameter signed [7:0] b5 = 8'd18;
+ parameter signed [7:0] b6 = 8'd18;
+ parameter signed [7:0] b7 = 8'd15;
+ parameter signed [7:0] b8 = 8'd10;
+ parameter signed [7:0] b9 = 8'd6;
+ parameter signed [7:0] b10 = 8'd3;
+ parameter signed [7:0] b11 = 8'd1;
+
+ // delay line
+ reg signed [7:0] x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11;
+
+ // multipliers
+ wire signed [15:0]
+ m0,m1,m2,m3,m4,m5,
+ m6,m7,m8,m9,m10,m11;
+
+ assign m0 = b0 * x;
+ assign m1 = b1 * x1;
+ assign m2 = b2 * x2;
+ assign m3 = b3 * x3;
+ assign m4 = b4 * x4;
+ assign m5 = b5 * x5;
+ assign m6 = b6 * x6;
+ assign m7 = b7 * x7;
+ assign m8 = b8 * x8;
+ assign m9 = b9 * x9;
+ assign m10 = b10 * x10;
+ assign m11 = b11 * x11;
+
+ // sum
+ assign y = m0+m1+m2+m3+m4+m5+
+ m6+m7+m8+m9+m10+m11;
+
+ // shift register
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ x1<=0; x2<=0; x3<=0; x4<=0; x5<=0; x6<=0;
+ x7<=0; x8<=0; x9<=0; x10<=0; x11<=0;
+ end else begin
+ x1<=x;
+ x2<=x1;
+ x3<=x2;
+ x4<=x3;
+ x5<=x4;
+ x6<=x5;
+ x7<=x6;
+ x8<=x7;
+ x9<=x8;
+ x10<=x9;
+ x11<=x10;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/fossee/fir_filter/fir_filter/fir_filter_Previous_Values.xml b/fossee/fir_filter/fir_filter/fir_filter_Previous_Values.xml
new file mode 100644
index 000000000..07757cb31
--- /dev/null
+++ b/fossee/fir_filter/fir_filter/fir_filter_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecpulsepulsepulsepulsepulsepulsepulsepulsepulsepulsefir_filteradc_bridgeadc_bridgedac_bridge
\ No newline at end of file
diff --git a/fossee/fir_filter/fir_module.png b/fossee/fir_filter/fir_module.png
new file mode 100644
index 000000000..512187a30
Binary files /dev/null and b/fossee/fir_filter/fir_module.png differ
diff --git a/fossee/fir_filter/fir_schematic.png b/fossee/fir_filter/fir_schematic.png
new file mode 100644
index 000000000..a98343225
Binary files /dev/null and b/fossee/fir_filter/fir_schematic.png differ
diff --git a/fossee/fir_filter/ngspicecmd.png b/fossee/fir_filter/ngspicecmd.png
new file mode 100644
index 000000000..588f871bd
Binary files /dev/null and b/fossee/fir_filter/ngspicecmd.png differ
diff --git a/fossee/fir_filter/waveforms.png b/fossee/fir_filter/waveforms.png
new file mode 100644
index 000000000..6f2b5485e
Binary files /dev/null and b/fossee/fir_filter/waveforms.png differ
diff --git a/fossee/freq_multiplier/freq_mul/analysis b/fossee/freq_multiplier/freq_mul/analysis
new file mode 100644
index 000000000..bba331247
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/analysis
@@ -0,0 +1 @@
+.tran 1e-09 100e-09 0e-09
\ No newline at end of file
diff --git a/fossee/freq_multiplier/freq_mul/freq_mul-cache.lib b/fossee/freq_multiplier/freq_mul/freq_mul-cache.lib
new file mode 100644
index 000000000..467d85d36
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/freq_mul-cache.lib
@@ -0,0 +1,109 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# freq_mul
+#
+DEF freq_mul U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "freq_mul" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1600 0 1 0 N
+X clk0 1 2150 1900 200 R 50 50 1 1 I
+X rst0 2 2150 1800 200 R 50 50 1 1 I
+X clk2x0 3 3550 1900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# plot_db
+#
+DEF plot_db U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_db" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/fossee/freq_multiplier/freq_mul/freq_mul-rescue.lib b/fossee/freq_multiplier/freq_mul/freq_mul-rescue.lib
new file mode 100644
index 000000000..cf9c8b693
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/freq_mul-rescue.lib
@@ -0,0 +1,19 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# freq_mul-RESCUE-freq_mul
+#
+DEF freq_mul-RESCUE-freq_mul U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "freq_mul-RESCUE-freq_mul" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1600 0 1 0 N
+X clk0 1 2150 1900 200 R 50 50 1 1 I
+X rst0 2 2150 1800 200 R 50 50 1 1 I
+X clk2x0 3 3550 1900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/fossee/freq_multiplier/freq_mul/freq_mul.cir b/fossee/freq_multiplier/freq_mul/freq_mul.cir
new file mode 100644
index 000000000..94c060c09
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/freq_mul.cir
@@ -0,0 +1,18 @@
+* C:\Users\VLSI\eSim-Workspace\freq_mul\freq_mul.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/03/2026 20:29:28
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ freq_mul
+U4 clkout rst0 Net-_U2-Pad1_ Net-_U2-Pad2_ adc_bridge_2
+v1 clkout GND pulse
+v2 rst0 GND pulse
+U5 Net-_U2-Pad3_ clkin dac_bridge_1
+U1 clkout plot_v1
+U3 rst0 plot_v1
+U6 clkin plot_v1
+
+.end
diff --git a/fossee/freq_multiplier/freq_mul/freq_mul.cir.out b/fossee/freq_multiplier/freq_mul/freq_mul.cir.out
new file mode 100644
index 000000000..06229668c
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/freq_mul.cir.out
@@ -0,0 +1,31 @@
+* c:\users\vlsi\esim-workspace\freq_mul\freq_mul.cir
+
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ freq_mul
+* u4 clkout rst0 net-_u2-pad1_ net-_u2-pad2_ adc_bridge_2
+v1 clkout gnd pulse(0 1 0.01ns 0.001ns 0.001ns 10ns 20ns)
+v2 rst0 gnd pulse(0 1 0.01ns 0.001ns 0.001ns 10ns 300ns)
+* u5 net-_u2-pad3_ clkin dac_bridge_1
+* u1 clkout plot_v1
+* u3 rst0 plot_v1
+* u6 clkin plot_v1
+a1 [net-_u2-pad1_ ] [net-_u2-pad2_ ] [net-_u2-pad3_ ] u2
+a2 [clkout rst0 ] [net-_u2-pad1_ net-_u2-pad2_ ] u4
+a3 [net-_u2-pad3_ ] [clkin ] u5
+* Schematic Name: freq_mul, NgSpice Name: freq_mul
+.model u2 freq_mul(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=0.4 in_high=0.6 rise_delay=1e-9 fall_delay=1e-9)
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=1.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 1e-09 300e-09 0e-09
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(clkout)+6 v(rst0)+12 v(clkin)+18
+plot
+plot
+.endc
+.end
diff --git a/fossee/freq_multiplier/freq_mul/freq_mul.pro b/fossee/freq_multiplier/freq_mul/freq_mul.pro
new file mode 100644
index 000000000..d79a6bcf4
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/freq_mul.pro
@@ -0,0 +1,74 @@
+update=03/03/2026 20:26:14
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=freq_mul-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/fossee/freq_multiplier/freq_mul/freq_mul.proj b/fossee/freq_multiplier/freq_mul/freq_mul.proj
new file mode 100644
index 000000000..80add1cc4
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/freq_mul.proj
@@ -0,0 +1 @@
+schematicFile freq_mul.sch
diff --git a/fossee/freq_multiplier/freq_mul/freq_mul.sch b/fossee/freq_multiplier/freq_mul/freq_mul.sch
new file mode 100644
index 000000000..ef4f73f94
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/freq_mul.sch
@@ -0,0 +1,251 @@
+EESchema Schematic File Version 2
+LIBS:freq_mul-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:freq_mul-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L adc_bridge_1 U4
+U 1 1 69A5B907
+P 4100 3350
+F 0 "U4" H 4100 3350 60 0000 C CNN
+F 1 "adc_bridge_1" H 4100 3500 60 0000 C CNN
+F 2 "" H 4100 3350 60 0000 C CNN
+F 3 "" H 4100 3350 60 0000 C CNN
+ 1 4100 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_1 U6
+U 1 1 69A5B9A8
+P 7550 3350
+F 0 "U6" H 7550 3350 60 0000 C CNN
+F 1 "dac_bridge_1" H 7550 3500 60 0000 C CNN
+F 2 "" H 7550 3350 60 0000 C CNN
+F 3 "" H 7550 3350 60 0000 C CNN
+ 1 7550 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v1
+U 1 1 69A5BA13
+P 1950 3350
+F 0 "v1" H 1750 3450 60 0000 C CNN
+F 1 "pulse" H 1750 3300 60 0000 C CNN
+F 2 "R1" H 1650 3350 60 0000 C CNN
+F 3 "" H 1950 3350 60 0000 C CNN
+ 1 1950 3350
+ 0 1 1 0
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 69A5BA88
+P 1300 3650
+F 0 "#PWR01" H 1300 3400 50 0001 C CNN
+F 1 "GND" H 1300 3500 50 0000 C CNN
+F 2 "" H 1300 3650 50 0001 C CNN
+F 3 "" H 1300 3650 50 0001 C CNN
+ 1 1300 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 69A5BAA4
+P 1150 3200
+F 0 "#FLG02" H 1150 3275 50 0001 C CNN
+F 1 "PWR_FLAG" H 1150 3350 50 0000 C CNN
+F 2 "" H 1150 3200 50 0001 C CNN
+F 3 "" H 1150 3200 50 0001 C CNN
+ 1 1150 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1500 3350 1300 3350
+Wire Wire Line
+ 1300 3200 1300 3650
+Wire Wire Line
+ 1150 3200 1300 3200
+Connection ~ 1300 3350
+Wire Wire Line
+ 2400 3350 3500 3350
+Wire Wire Line
+ 3500 3350 3500 3300
+Wire Wire Line
+ 4650 3300 5100 3300
+Wire Wire Line
+ 6500 3300 6950 3300
+$Comp
+L plot_db U7
+U 1 1 69A5BAF2
+P 8800 3450
+F 0 "U7" H 8800 3950 60 0000 C CNN
+F 1 "plot_db" H 9000 3800 60 0000 C CNN
+F 2 "" H 8800 3450 60 0000 C CNN
+F 3 "" H 8800 3450 60 0000 C CNN
+ 1 8800 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_db U1
+U 1 1 69A5BB1D
+P 2800 3400
+F 0 "U1" H 2800 3900 60 0000 C CNN
+F 1 "plot_db" H 3000 3750 60 0000 C CNN
+F 2 "" H 2800 3400 60 0000 C CNN
+F 3 "" H 2800 3400 60 0000 C CNN
+ 1 2800 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2800 3200 2800 3350
+Connection ~ 2800 3350
+Wire Wire Line
+ 8100 3300 8500 3300
+Wire Wire Line
+ 8500 3300 8500 3250
+$Comp
+L freq_mul U2
+U 1 1 69A5BD31
+P 2950 5200
+F 0 "U2" H 5800 7000 60 0000 C CNN
+F 1 "freq_mul" H 5800 7200 60 0000 C CNN
+F 2 "" H 5800 7150 60 0000 C CNN
+F 3 "" H 5800 7150 60 0000 C CNN
+ 1 2950 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_1 U5
+U 1 1 69A5BE69
+P 4450 4400
+F 0 "U5" H 4450 4400 60 0000 C CNN
+F 1 "adc_bridge_1" H 4450 4550 60 0000 C CNN
+F 2 "" H 4450 4400 60 0000 C CNN
+F 3 "" H 4450 4400 60 0000 C CNN
+ 1 4450 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v2
+U 1 1 69A5BE70
+P 2300 4400
+F 0 "v2" H 2100 4500 60 0000 C CNN
+F 1 "pulse" H 2100 4350 60 0000 C CNN
+F 2 "R1" H 2000 4400 60 0000 C CNN
+F 3 "" H 2300 4400 60 0000 C CNN
+ 1 2300 4400
+ 0 1 1 0
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 69A5BE77
+P 1650 4700
+F 0 "#PWR03" H 1650 4450 50 0001 C CNN
+F 1 "GND" H 1650 4550 50 0000 C CNN
+F 2 "" H 1650 4700 50 0001 C CNN
+F 3 "" H 1650 4700 50 0001 C CNN
+ 1 1650 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG04
+U 1 1 69A5BE7D
+P 1500 4250
+F 0 "#FLG04" H 1500 4325 50 0001 C CNN
+F 1 "PWR_FLAG" H 1500 4400 50 0000 C CNN
+F 2 "" H 1500 4250 50 0001 C CNN
+F 3 "" H 1500 4250 50 0001 C CNN
+ 1 1500 4250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1850 4400 1650 4400
+Wire Wire Line
+ 1650 4250 1650 4700
+Wire Wire Line
+ 1500 4250 1650 4250
+Connection ~ 1650 4400
+Wire Wire Line
+ 2750 4400 3850 4400
+Wire Wire Line
+ 3850 4400 3850 4350
+$Comp
+L plot_db U3
+U 1 1 69A5BE89
+P 3150 4450
+F 0 "U3" H 3150 4950 60 0000 C CNN
+F 1 "plot_db" H 3350 4800 60 0000 C CNN
+F 2 "" H 3150 4450 60 0000 C CNN
+F 3 "" H 3150 4450 60 0000 C CNN
+ 1 3150 4450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3150 4250 3150 4400
+Connection ~ 3150 4400
+Wire Wire Line
+ 5000 4350 5000 3450
+Wire Wire Line
+ 5000 3450 5100 3450
+Wire Wire Line
+ 5100 3450 5100 3400
+Text GLabel 3250 3350 1 60 Input ~ 0
+clki
+Text GLabel 3700 4400 1 60 Input ~ 0
+rst0
+Text GLabel 8350 3300 1 60 Input ~ 0
+clkout
+Wire Wire Line
+ 8500 3250 8800 3250
+$EndSCHEMATC
diff --git a/fossee/freq_multiplier/freq_mul/freq_mul.v b/fossee/freq_multiplier/freq_mul/freq_mul.v
new file mode 100644
index 000000000..fa9732576
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/freq_mul.v
@@ -0,0 +1,13 @@
+`timescale 1ns/1ps
+
+module freq_x2 (
+ input wire clk,
+ output reg clk2z
+);
+
+initial clk2z = 1'b0;
+
+always @(posedge clk or negedge clk)
+ clk2z <= ~clk2z;
+
+endmodule
\ No newline at end of file
diff --git a/fossee/freq_multiplier/freq_mul/freq_mul_Previous_Values.xml b/fossee/freq_multiplier/freq_mul/freq_mul_Previous_Values.xml
new file mode 100644
index 000000000..c1096a243
--- /dev/null
+++ b/fossee/freq_multiplier/freq_mul/freq_mul_Previous_Values.xml
@@ -0,0 +1 @@
+pulse010.01ns0.001ns0.001ns10ns20nspulse010.01ns0.001ns0.001ns10ns100nsfreq_muladc_bridgedac_bridgeadc_bridgedac_bridgeadc_bridgedac_bridgetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01100nsnsns
\ No newline at end of file
diff --git a/fossee/freq_multiplier/freq_mul_ckt.png b/fossee/freq_multiplier/freq_mul_ckt.png
new file mode 100644
index 000000000..5b941884b
Binary files /dev/null and b/fossee/freq_multiplier/freq_mul_ckt.png differ
diff --git a/fossee/freq_multiplier/freq_mul_esim.png b/fossee/freq_multiplier/freq_mul_esim.png
new file mode 100644
index 000000000..e584a686a
Binary files /dev/null and b/fossee/freq_multiplier/freq_mul_esim.png differ
diff --git a/fossee/freq_multiplier/freq_mul_module.png b/fossee/freq_multiplier/freq_mul_module.png
new file mode 100644
index 000000000..245e16149
Binary files /dev/null and b/fossee/freq_multiplier/freq_mul_module.png differ
diff --git a/fossee/freq_multiplier/freq_mul_vivado.png b/fossee/freq_multiplier/freq_mul_vivado.png
new file mode 100644
index 000000000..937e976f7
Binary files /dev/null and b/fossee/freq_multiplier/freq_mul_vivado.png differ
diff --git a/fossee/freq_multiplier/freq_mul_wavefor,sa.png b/fossee/freq_multiplier/freq_mul_wavefor,sa.png
new file mode 100644
index 000000000..b7fdae2d8
Binary files /dev/null and b/fossee/freq_multiplier/freq_mul_wavefor,sa.png differ
diff --git a/fossee/freq_multiplier/frq_mul_schematic.png b/fossee/freq_multiplier/frq_mul_schematic.png
new file mode 100644
index 000000000..e117ab0fc
Binary files /dev/null and b/fossee/freq_multiplier/frq_mul_schematic.png differ
diff --git a/fossee/freq_multiplier/mul.v b/fossee/freq_multiplier/mul.v
new file mode 100644
index 000000000..c35b4f1ef
--- /dev/null
+++ b/fossee/freq_multiplier/mul.v
@@ -0,0 +1,16 @@
+`timescale 1ns/1ps
+
+module freq_div2 (
+ input wire clk,
+ input wire rst,
+ output reg clk_div2
+);
+
+always @(posedge clk or posedge rst) begin
+ if (rst)
+ clk_div2 <= 0;
+ else
+ clk_div2 <= ~clk_div2;
+end
+
+endmodule
\ No newline at end of file
diff --git a/fossee/freq_multiplier/tb.v b/fossee/freq_multiplier/tb.v
new file mode 100644
index 000000000..7a2151eef
--- /dev/null
+++ b/fossee/freq_multiplier/tb.v
@@ -0,0 +1,79 @@
+`timescale 1ns/1ps
+
+module tb_freq_div2;
+
+reg clk;
+reg rst;
+wire clk_div2;
+
+real t1_in, t2_in, period_in;
+real t1_out, t2_out, period_out;
+real freq_in, freq_out;
+
+freq_div2 DUT (
+ .clk(clk),
+ .rst(rst),
+ .clk_div2(clk_div2)
+);
+
+//
+// Generate 100 MHz clock (10 ns period)
+//
+initial begin
+ clk = 0;
+ forever #5 clk = ~clk;
+end
+
+//
+// Reset
+//
+initial begin
+ rst = 1;
+ #20;
+ rst = 0;
+end
+
+//
+// Measure INPUT frequency
+//
+initial begin
+ @(posedge clk);
+ t1_in = $realtime;
+ @(posedge clk);
+ t2_in = $realtime;
+
+ period_in = t2_in - t1_in;
+ freq_in = 1000.0 / period_in;
+
+ $display("INPUT CLOCK:");
+ $display("Period = %0.2f ns", period_in);
+ $display("Frequency = %0.2f MHz\n", freq_in);
+end
+
+//
+// Measure OUTPUT frequency
+//
+initial begin
+ @(negedge rst); // wait reset release
+ @(posedge clk_div2);
+ t1_out = $realtime;
+ @(posedge clk_div2);
+ t2_out = $realtime;
+
+ period_out = t2_out - t1_out;
+ freq_out = 1000.0 / period_out;
+
+ $display("OUTPUT CLOCK (DIV2):");
+ $display("Period = %0.2f ns", period_out);
+ $display("Frequency = %0.2f MHz\n", freq_out);
+end
+
+//
+// Finish
+//
+initial begin
+ #200;
+ $finish;
+end
+
+endmodule
\ No newline at end of file
diff --git a/fossee/gcd/gcd_a.png b/fossee/gcd/gcd_a.png
new file mode 100644
index 000000000..8efe2fbd9
Binary files /dev/null and b/fossee/gcd/gcd_a.png differ
diff --git a/fossee/gcd/gcd_b.png b/fossee/gcd/gcd_b.png
new file mode 100644
index 000000000..64eadee83
Binary files /dev/null and b/fossee/gcd/gcd_b.png differ
diff --git a/fossee/gcd/gcd_clk.png b/fossee/gcd/gcd_clk.png
new file mode 100644
index 000000000..a4e093317
Binary files /dev/null and b/fossee/gcd/gcd_clk.png differ
diff --git a/fossee/gcd/gcd_cmd.png b/fossee/gcd/gcd_cmd.png
new file mode 100644
index 000000000..0888a7cd2
Binary files /dev/null and b/fossee/gcd/gcd_cmd.png differ
diff --git a/fossee/gcd/gcd_ip.png b/fossee/gcd/gcd_ip.png
new file mode 100644
index 000000000..b78679714
Binary files /dev/null and b/fossee/gcd/gcd_ip.png differ
diff --git a/fossee/gcd/gcd_op.png b/fossee/gcd/gcd_op.png
new file mode 100644
index 000000000..9ba74f2a2
Binary files /dev/null and b/fossee/gcd/gcd_op.png differ
diff --git a/fossee/gcd/gcd_schematic .png b/fossee/gcd/gcd_schematic .png
new file mode 100644
index 000000000..ba7a7345c
Binary files /dev/null and b/fossee/gcd/gcd_schematic .png differ
diff --git a/fossee/gcd/gcd_seq/analysis b/fossee/gcd/gcd_seq/analysis
new file mode 100644
index 000000000..5426862f8
--- /dev/null
+++ b/fossee/gcd/gcd_seq/analysis
@@ -0,0 +1 @@
+.tran 1e-09 250e-09 0e-00
\ No newline at end of file
diff --git a/fossee/gcd/gcd_seq/gcd_seq-cache.lib b/fossee/gcd/gcd_seq/gcd_seq-cache.lib
new file mode 100644
index 000000000..65214381c
--- /dev/null
+++ b/fossee/gcd/gcd_seq/gcd_seq-cache.lib
@@ -0,0 +1,211 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_3
+#
+DEF adc_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# gcd_seq
+#
+DEF gcd_seq U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "gcd_seq" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 -100 0 1 0 N
+X clk0 1 2150 1900 200 R 50 50 1 1 I
+X rst0 2 2150 1800 200 R 50 50 1 1 I
+X start0 3 2150 1700 200 R 50 50 1 1 I
+X a7 4 2150 1600 200 R 50 50 1 1 I
+X a6 5 2150 1500 200 R 50 50 1 1 I
+X a5 6 2150 1400 200 R 50 50 1 1 I
+X a4 7 2150 1300 200 R 50 50 1 1 I
+X a3 8 2150 1200 200 R 50 50 1 1 I
+X a2 9 2150 1100 200 R 50 50 1 1 I
+X a1 10 2150 1000 200 R 50 50 1 1 I
+X gcd7 20 3550 1900 200 L 50 50 1 1 O
+X a0 11 2150 900 200 R 50 50 1 1 I
+X gcd6 21 3550 1800 200 L 50 50 1 1 O
+X b7 12 2150 800 200 R 50 50 1 1 I
+X gcd5 22 3550 1700 200 L 50 50 1 1 O
+X b6 13 2150 700 200 R 50 50 1 1 I
+X gcd4 23 3550 1600 200 L 50 50 1 1 O
+X b5 14 2150 600 200 R 50 50 1 1 I
+X gcd3 24 3550 1500 200 L 50 50 1 1 O
+X b4 15 2150 500 200 R 50 50 1 1 I
+X gcd2 25 3550 1400 200 L 50 50 1 1 O
+X b3 16 2150 400 200 R 50 50 1 1 I
+X gcd1 26 3550 1300 200 L 50 50 1 1 O
+X b2 17 2150 300 200 R 50 50 1 1 I
+X gcd0 27 3550 1200 200 L 50 50 1 1 O
+X b1 18 2150 200 200 R 50 50 1 1 I
+X done0 28 3550 1100 200 L 50 50 1 1 O
+X b0 19 2150 100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/fossee/gcd/gcd_seq/gcd_seq.cir b/fossee/gcd/gcd_seq/gcd_seq.cir
new file mode 100644
index 000000000..a87c127c2
--- /dev/null
+++ b/fossee/gcd/gcd_seq/gcd_seq.cir
@@ -0,0 +1,64 @@
+* C:\Users\srinu\eSim-Workspace\gcd_seq\gcd_seq.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/21/26 01:12:16
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ Net-_U19-Pad4_ Net-_U19-Pad5_ Net-_U19-Pad6_ Net-_U19-Pad7_ Net-_U19-Pad8_ Net-_U19-Pad9_ Net-_U19-Pad10_ Net-_U19-Pad11_ Net-_U19-Pad12_ Net-_U19-Pad13_ Net-_U19-Pad14_ Net-_U19-Pad15_ Net-_U19-Pad16_ Net-_U19-Pad17_ Net-_U19-Pad18_ Net-_U19-Pad19_ Net-_U19-Pad20_ Net-_U19-Pad21_ Net-_U19-Pad22_ Net-_U19-Pad23_ Net-_U19-Pad24_ Net-_U19-Pad25_ Net-_U19-Pad26_ Net-_U19-Pad27_ Net-_U19-Pad28_ gcd_seq
+v1 clk GND pulse
+v2 rst GND pulse
+v3 start GND pulse
+v12 a7 GND DC
+v13 a6 GND DC
+v14 a5 GND DC
+v15 a4 GND DC
+v16 a3 GND DC
+v17 a2 GND DC
+v18 a1 GND DC
+v19 a0 GND DC
+v4 b7 GND DC
+v5 b6 GND DC
+v6 b5 GND DC
+v7 b4 GND DC
+v8 b3 GND DC
+v9 b2 GND DC
+v10 b1 GND DC
+v11 b0 GND DC
+U24 b7 b6 b5 b4 b3 b2 b1 b0 Net-_U19-Pad12_ Net-_U19-Pad13_ Net-_U19-Pad14_ Net-_U19-Pad15_ Net-_U19-Pad16_ Net-_U19-Pad17_ Net-_U19-Pad18_ Net-_U19-Pad19_ adc_bridge_8
+U23 a7 a6 a5 a4 a3 a2 a1 a0 Net-_U19-Pad4_ Net-_U19-Pad5_ Net-_U19-Pad6_ Net-_U19-Pad7_ Net-_U19-Pad8_ Net-_U19-Pad9_ Net-_U19-Pad10_ Net-_U19-Pad11_ adc_bridge_8
+U22 clk rst start Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ adc_bridge_3
+U25 Net-_U19-Pad20_ Net-_U19-Pad21_ Net-_U19-Pad22_ Net-_U19-Pad23_ Net-_U19-Pad24_ Net-_U19-Pad25_ Net-_U19-Pad26_ Net-_U19-Pad27_ g7 g6 g5 g4 g3 g2 g1 g0 dac_bridge_8
+U26 Net-_U19-Pad28_ done dac_bridge_1
+U27 g7 plot_v1
+U28 g6 plot_v1
+U31 g5 plot_v1
+U29 g4 plot_v1
+U32 g3 plot_v1
+U34 g2 plot_v1
+U30 g1 plot_v1
+U33 g0 plot_v1
+U35 done plot_v1
+U13 clk plot_v1
+U18 rst plot_v1
+U21 start plot_v1
+U5 a7 plot_v1
+U7 a6 plot_v1
+U10 a5 plot_v1
+U12 a4 plot_v1
+U16 a3 plot_v1
+U14 a2 plot_v1
+U9 a1 plot_v1
+U8 a0 plot_v1
+U1 b7 plot_v1
+U2 b6 plot_v1
+U3 b6 plot_v1
+U4 b5 plot_v1
+U6 b4 plot_v1
+U11 b3 plot_v1
+U15 b2 plot_v1
+U17 b1 plot_v1
+U20 b0 plot_v1
+
+.end
diff --git a/fossee/gcd/gcd_seq/gcd_seq.cir.out b/fossee/gcd/gcd_seq/gcd_seq.cir.out
new file mode 100644
index 000000000..a8217367b
--- /dev/null
+++ b/fossee/gcd/gcd_seq/gcd_seq.cir.out
@@ -0,0 +1,88 @@
+* c:\users\srinu\esim-workspace\gcd_seq\gcd_seq.cir
+
+* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ net-_u19-pad4_ net-_u19-pad5_ net-_u19-pad6_ net-_u19-pad7_ net-_u19-pad8_ net-_u19-pad9_ net-_u19-pad10_ net-_u19-pad11_ net-_u19-pad12_ net-_u19-pad13_ net-_u19-pad14_ net-_u19-pad15_ net-_u19-pad16_ net-_u19-pad17_ net-_u19-pad18_ net-_u19-pad19_ net-_u19-pad20_ net-_u19-pad21_ net-_u19-pad22_ net-_u19-pad23_ net-_u19-pad24_ net-_u19-pad25_ net-_u19-pad26_ net-_u19-pad27_ net-_u19-pad28_ gcd_seq
+v1 clk gnd pulse(0 1 0.01ns 0.01ns 0.01ns 10ns 20ns)
+v2 rst gnd pulse(0 1 0.01ns 0.01ns 0.01ns 10ns 200ns)
+v3 start gnd pulse(0 1 0.01ns 0.01ns 0.01ns 10ns 100ns)
+v12 a7 gnd dc 0
+v13 a6 gnd dc 0
+v14 a5 gnd dc 0
+v15 a4 gnd dc 0
+v16 a3 gnd dc 5
+v17 a2 gnd dc 0
+v18 a1 gnd dc 0
+v19 a0 gnd dc 5
+v4 b7 gnd dc 0
+v5 b6 gnd dc 0
+v6 b5 gnd dc 0
+v7 b4 gnd dc 0
+v8 b3 gnd dc 0
+v9 b2 gnd dc 0
+v10 b1 gnd dc 5
+v11 b0 gnd dc 5
+* u24 b7 b6 b5 b4 b3 b2 b1 b0 net-_u19-pad12_ net-_u19-pad13_ net-_u19-pad14_ net-_u19-pad15_ net-_u19-pad16_ net-_u19-pad17_ net-_u19-pad18_ net-_u19-pad19_ adc_bridge_8
+* u23 a7 a6 a5 a4 a3 a2 a1 a0 net-_u19-pad4_ net-_u19-pad5_ net-_u19-pad6_ net-_u19-pad7_ net-_u19-pad8_ net-_u19-pad9_ net-_u19-pad10_ net-_u19-pad11_ adc_bridge_8
+* u22 clk rst start net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ adc_bridge_3
+* u25 net-_u19-pad20_ net-_u19-pad21_ net-_u19-pad22_ net-_u19-pad23_ net-_u19-pad24_ net-_u19-pad25_ net-_u19-pad26_ net-_u19-pad27_ g7 g6 g5 g4 g3 g2 g1 g0 dac_bridge_8
+* u26 net-_u19-pad28_ done dac_bridge_1
+* u27 g7 plot_v1
+* u28 g6 plot_v1
+* u31 g5 plot_v1
+* u29 g4 plot_v1
+* u32 g3 plot_v1
+* u34 g2 plot_v1
+* u30 g1 plot_v1
+* u33 g0 plot_v1
+* u35 done plot_v1
+* u13 clk plot_v1
+* u18 rst plot_v1
+* u21 start plot_v1
+* u5 a7 plot_v1
+* u7 a6 plot_v1
+* u10 a5 plot_v1
+* u12 a4 plot_v1
+* u16 a3 plot_v1
+* u14 a2 plot_v1
+* u9 a1 plot_v1
+* u8 a0 plot_v1
+* u1 b7 plot_v1
+* u2 b6 plot_v1
+* u3 b6 plot_v1
+* u4 b5 plot_v1
+* u6 b4 plot_v1
+* u11 b3 plot_v1
+* u15 b2 plot_v1
+* u17 b1 plot_v1
+* u20 b0 plot_v1
+a1 [net-_u19-pad1_ ] [net-_u19-pad2_ ] [net-_u19-pad3_ ] [net-_u19-pad4_ net-_u19-pad5_ net-_u19-pad6_ net-_u19-pad7_ net-_u19-pad8_ net-_u19-pad9_ net-_u19-pad10_ net-_u19-pad11_ ] [net-_u19-pad12_ net-_u19-pad13_ net-_u19-pad14_ net-_u19-pad15_ net-_u19-pad16_ net-_u19-pad17_ net-_u19-pad18_ net-_u19-pad19_ ] [net-_u19-pad20_ net-_u19-pad21_ net-_u19-pad22_ net-_u19-pad23_ net-_u19-pad24_ net-_u19-pad25_ net-_u19-pad26_ net-_u19-pad27_ ] [net-_u19-pad28_ ] u19
+a2 [b7 b6 b5 b4 b3 b2 b1 b0 ] [net-_u19-pad12_ net-_u19-pad13_ net-_u19-pad14_ net-_u19-pad15_ net-_u19-pad16_ net-_u19-pad17_ net-_u19-pad18_ net-_u19-pad19_ ] u24
+a3 [a7 a6 a5 a4 a3 a2 a1 a0 ] [net-_u19-pad4_ net-_u19-pad5_ net-_u19-pad6_ net-_u19-pad7_ net-_u19-pad8_ net-_u19-pad9_ net-_u19-pad10_ net-_u19-pad11_ ] u23
+a4 [clk rst start ] [net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ ] u22
+a5 [net-_u19-pad20_ net-_u19-pad21_ net-_u19-pad22_ net-_u19-pad23_ net-_u19-pad24_ net-_u19-pad25_ net-_u19-pad26_ net-_u19-pad27_ ] [g7 g6 g5 g4 g3 g2 g1 g0 ] u25
+a6 [net-_u19-pad28_ ] [done ] u26
+* Schematic Name: gcd_seq, NgSpice Name: gcd_seq
+.model u19 gcd_seq(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u24 adc_bridge(in_low=0.8 in_high=1.2 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u23 adc_bridge(in_low=0.8 in_high=1.2 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u22 adc_bridge(in_low=0.8 in_high=1.2 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
+.model u25 dac_bridge(out_low=0.0 out_high=3.3 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u26 dac_bridge(out_low=0.0 out_high=3.3 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 1e-09 250e-09 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+set xbrushwidth=2
+plot v(done)+6 v(start)+12 v(rst)+18 v(clk)+24
+plot v(b0)+6v(b1)+12v(b2)+18v(b3)+24v(b4)+30v(b5)+36v(b6)+42v(b7)+48
+plot v(a0)+6v(a1)+12v(a2)+18v(a3)+24v(a4)+30v(a5)+36v(a6)+42v(a7)+48
+plot v(g0)+6v(g1)+12v(g2)+18v(g3)+24v(g4)+30v(g5)+36v(g6)+42v(g7)+48
+.endc
+.end
diff --git a/fossee/gcd/gcd_seq/gcd_seq.pro b/fossee/gcd/gcd_seq/gcd_seq.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/fossee/gcd/gcd_seq/gcd_seq.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/fossee/gcd/gcd_seq/gcd_seq.proj b/fossee/gcd/gcd_seq/gcd_seq.proj
new file mode 100644
index 000000000..e83e084bc
--- /dev/null
+++ b/fossee/gcd/gcd_seq/gcd_seq.proj
@@ -0,0 +1 @@
+schematicFile gcd_seq.sch
diff --git a/fossee/gcd/gcd_seq/gcd_seq.sch b/fossee/gcd/gcd_seq/gcd_seq.sch
new file mode 100644
index 000000000..60cfc468c
--- /dev/null
+++ b/fossee/gcd/gcd_seq/gcd_seq.sch
@@ -0,0 +1,1172 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L gcd_seq U19
+U 1 1 69BD9D5D
+P 3100 4650
+F 0 "U19" H 5950 6450 60 0000 C CNN
+F 1 "gcd_seq" H 5950 6650 60 0000 C CNN
+F 2 "" H 5950 6600 60 0000 C CNN
+F 3 "" H 5950 6600 60 0000 C CNN
+ 1 3100 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v1
+U 1 1 69BD9EA3
+P 1350 950
+F 0 "v1" H 1150 1050 60 0000 C CNN
+F 1 "pulse" H 1150 900 60 0000 C CNN
+F 2 "R1" H 1050 950 60 0000 C CNN
+F 3 "" H 1350 950 60 0000 C CNN
+ 1 1350 950
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v2
+U 1 1 69BD9F64
+P 1350 1300
+F 0 "v2" H 1150 1400 60 0000 C CNN
+F 1 "pulse" H 1150 1250 60 0000 C CNN
+F 2 "R1" H 1050 1300 60 0000 C CNN
+F 3 "" H 1350 1300 60 0000 C CNN
+ 1 1350 1300
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v3
+U 1 1 69BD9FB1
+P 1350 1700
+F 0 "v3" H 1150 1800 60 0000 C CNN
+F 1 "pulse" H 1150 1650 60 0000 C CNN
+F 2 "R1" H 1050 1700 60 0000 C CNN
+F 3 "" H 1350 1700 60 0000 C CNN
+ 1 1350 1700
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v12
+U 1 1 69BD9FF4
+P 1750 2200
+F 0 "v12" H 1550 2300 60 0000 C CNN
+F 1 "DC" H 1550 2150 60 0000 C CNN
+F 2 "R1" H 1450 2200 60 0000 C CNN
+F 3 "" H 1750 2200 60 0000 C CNN
+ 1 1750 2200
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v13
+U 1 1 69BDA0D0
+P 1750 2550
+F 0 "v13" H 1550 2650 60 0000 C CNN
+F 1 "DC" H 1550 2500 60 0000 C CNN
+F 2 "R1" H 1450 2550 60 0000 C CNN
+F 3 "" H 1750 2550 60 0000 C CNN
+ 1 1750 2550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v14
+U 1 1 69BDA25F
+P 1750 2900
+F 0 "v14" H 1550 3000 60 0000 C CNN
+F 1 "DC" H 1550 2850 60 0000 C CNN
+F 2 "R1" H 1450 2900 60 0000 C CNN
+F 3 "" H 1750 2900 60 0000 C CNN
+ 1 1750 2900
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v15
+U 1 1 69BDA266
+P 1750 3250
+F 0 "v15" H 1550 3350 60 0000 C CNN
+F 1 "DC" H 1550 3200 60 0000 C CNN
+F 2 "R1" H 1450 3250 60 0000 C CNN
+F 3 "" H 1750 3250 60 0000 C CNN
+ 1 1750 3250
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v16
+U 1 1 69BDAAD9
+P 1750 3650
+F 0 "v16" H 1550 3750 60 0000 C CNN
+F 1 "DC" H 1550 3600 60 0000 C CNN
+F 2 "R1" H 1450 3650 60 0000 C CNN
+F 3 "" H 1750 3650 60 0000 C CNN
+ 1 1750 3650
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v17
+U 1 1 69BDAAE0
+P 1750 4000
+F 0 "v17" H 1550 4100 60 0000 C CNN
+F 1 "DC" H 1550 3950 60 0000 C CNN
+F 2 "R1" H 1450 4000 60 0000 C CNN
+F 3 "" H 1750 4000 60 0000 C CNN
+ 1 1750 4000
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v18
+U 1 1 69BDAAE7
+P 1750 4350
+F 0 "v18" H 1550 4450 60 0000 C CNN
+F 1 "DC" H 1550 4300 60 0000 C CNN
+F 2 "R1" H 1450 4350 60 0000 C CNN
+F 3 "" H 1750 4350 60 0000 C CNN
+ 1 1750 4350
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v19
+U 1 1 69BDAAEE
+P 1750 4700
+F 0 "v19" H 1550 4800 60 0000 C CNN
+F 1 "DC" H 1550 4650 60 0000 C CNN
+F 2 "R1" H 1450 4700 60 0000 C CNN
+F 3 "" H 1750 4700 60 0000 C CNN
+ 1 1750 4700
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v4
+U 1 1 69BDAE45
+P 1350 5100
+F 0 "v4" H 1150 5200 60 0000 C CNN
+F 1 "DC" H 1150 5050 60 0000 C CNN
+F 2 "R1" H 1050 5100 60 0000 C CNN
+F 3 "" H 1350 5100 60 0000 C CNN
+ 1 1350 5100
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v5
+U 1 1 69BDAE4C
+P 1350 5450
+F 0 "v5" H 1150 5550 60 0000 C CNN
+F 1 "DC" H 1150 5400 60 0000 C CNN
+F 2 "R1" H 1050 5450 60 0000 C CNN
+F 3 "" H 1350 5450 60 0000 C CNN
+ 1 1350 5450
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v6
+U 1 1 69BDAE53
+P 1350 5800
+F 0 "v6" H 1150 5900 60 0000 C CNN
+F 1 "DC" H 1150 5750 60 0000 C CNN
+F 2 "R1" H 1050 5800 60 0000 C CNN
+F 3 "" H 1350 5800 60 0000 C CNN
+ 1 1350 5800
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v7
+U 1 1 69BDAE5A
+P 1350 6150
+F 0 "v7" H 1150 6250 60 0000 C CNN
+F 1 "DC" H 1150 6100 60 0000 C CNN
+F 2 "R1" H 1050 6150 60 0000 C CNN
+F 3 "" H 1350 6150 60 0000 C CNN
+ 1 1350 6150
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v8
+U 1 1 69BDAE61
+P 1350 6550
+F 0 "v8" H 1150 6650 60 0000 C CNN
+F 1 "DC" H 1150 6500 60 0000 C CNN
+F 2 "R1" H 1050 6550 60 0000 C CNN
+F 3 "" H 1350 6550 60 0000 C CNN
+ 1 1350 6550
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v9
+U 1 1 69BDAE68
+P 1350 6900
+F 0 "v9" H 1150 7000 60 0000 C CNN
+F 1 "DC" H 1150 6850 60 0000 C CNN
+F 2 "R1" H 1050 6900 60 0000 C CNN
+F 3 "" H 1350 6900 60 0000 C CNN
+ 1 1350 6900
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v10
+U 1 1 69BDAE6F
+P 1350 7250
+F 0 "v10" H 1150 7350 60 0000 C CNN
+F 1 "DC" H 1150 7200 60 0000 C CNN
+F 2 "R1" H 1050 7250 60 0000 C CNN
+F 3 "" H 1350 7250 60 0000 C CNN
+ 1 1350 7250
+ 0 1 1 0
+$EndComp
+$Comp
+L DC v11
+U 1 1 69BDAE76
+P 1350 7600
+F 0 "v11" H 1150 7700 60 0000 C CNN
+F 1 "DC" H 1150 7550 60 0000 C CNN
+F 2 "R1" H 1050 7600 60 0000 C CNN
+F 3 "" H 1350 7600 60 0000 C CNN
+ 1 1350 7600
+ 0 1 1 0
+$EndComp
+$Comp
+L adc_bridge_8 U24
+U 1 1 69BDE1C1
+P 4700 3900
+F 0 "U24" H 4700 3900 60 0000 C CNN
+F 1 "adc_bridge_8" H 4700 4050 60 0000 C CNN
+F 2 "" H 4700 3900 60 0000 C CNN
+F 3 "" H 4700 3900 60 0000 C CNN
+ 1 4700 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_8 U23
+U 1 1 69BDE28B
+P 4700 3100
+F 0 "U23" H 4700 3100 60 0000 C CNN
+F 1 "adc_bridge_8" H 4700 3250 60 0000 C CNN
+F 2 "" H 4700 3100 60 0000 C CNN
+F 3 "" H 4700 3100 60 0000 C CNN
+ 1 4700 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_3 U22
+U 1 1 69BDE736
+P 4700 2800
+F 0 "U22" H 4700 2800 60 0000 C CNN
+F 1 "adc_bridge_3" H 4700 2950 60 0000 C CNN
+F 2 "" H 4700 2800 60 0000 C CNN
+F 3 "" H 4700 2800 60 0000 C CNN
+ 1 4700 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_8 U25
+U 1 1 69BDE7DD
+P 7250 2800
+F 0 "U25" H 7250 2800 60 0000 C CNN
+F 1 "dac_bridge_8" H 7250 2950 60 0000 C CNN
+F 2 "" H 7250 2800 60 0000 C CNN
+F 3 "" H 7250 2800 60 0000 C CNN
+ 1 7250 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_1 U26
+U 1 1 69BDE842
+P 7250 3600
+F 0 "U26" H 7250 3600 60 0000 C CNN
+F 1 "dac_bridge_1" H 7250 3750 60 0000 C CNN
+F 2 "" H 7250 3600 60 0000 C CNN
+F 3 "" H 7250 3600 60 0000 C CNN
+ 1 7250 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 69BE178C
+P 700 1000
+F 0 "#PWR01" H 700 750 50 0001 C CNN
+F 1 "GND" H 700 850 50 0000 C CNN
+F 2 "" H 700 1000 50 0001 C CNN
+F 3 "" H 700 1000 50 0001 C CNN
+ 1 700 1000
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 69BE17D2
+P 900 1300
+F 0 "#PWR02" H 900 1050 50 0001 C CNN
+F 1 "GND" H 900 1150 50 0000 C CNN
+F 2 "" H 900 1300 50 0001 C CNN
+F 3 "" H 900 1300 50 0001 C CNN
+ 1 900 1300
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 69BE1818
+P 900 1700
+F 0 "#PWR03" H 900 1450 50 0001 C CNN
+F 1 "GND" H 900 1550 50 0000 C CNN
+F 2 "" H 900 1700 50 0001 C CNN
+F 3 "" H 900 1700 50 0001 C CNN
+ 1 900 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR04
+U 1 1 69BE185E
+P 1300 2200
+F 0 "#PWR04" H 1300 1950 50 0001 C CNN
+F 1 "GND" H 1300 2050 50 0000 C CNN
+F 2 "" H 1300 2200 50 0001 C CNN
+F 3 "" H 1300 2200 50 0001 C CNN
+ 1 1300 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR05
+U 1 1 69BE18A4
+P 1300 2550
+F 0 "#PWR05" H 1300 2300 50 0001 C CNN
+F 1 "GND" H 1300 2400 50 0000 C CNN
+F 2 "" H 1300 2550 50 0001 C CNN
+F 3 "" H 1300 2550 50 0001 C CNN
+ 1 1300 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR06
+U 1 1 69BE18EA
+P 1300 2900
+F 0 "#PWR06" H 1300 2650 50 0001 C CNN
+F 1 "GND" H 1300 2750 50 0000 C CNN
+F 2 "" H 1300 2900 50 0001 C CNN
+F 3 "" H 1300 2900 50 0001 C CNN
+ 1 1300 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR07
+U 1 1 69BE1930
+P 1300 3250
+F 0 "#PWR07" H 1300 3000 50 0001 C CNN
+F 1 "GND" H 1300 3100 50 0000 C CNN
+F 2 "" H 1300 3250 50 0001 C CNN
+F 3 "" H 1300 3250 50 0001 C CNN
+ 1 1300 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR08
+U 1 1 69BE1976
+P 1300 3650
+F 0 "#PWR08" H 1300 3400 50 0001 C CNN
+F 1 "GND" H 1300 3500 50 0000 C CNN
+F 2 "" H 1300 3650 50 0001 C CNN
+F 3 "" H 1300 3650 50 0001 C CNN
+ 1 1300 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR09
+U 1 1 69BE19BC
+P 1300 4000
+F 0 "#PWR09" H 1300 3750 50 0001 C CNN
+F 1 "GND" H 1300 3850 50 0000 C CNN
+F 2 "" H 1300 4000 50 0001 C CNN
+F 3 "" H 1300 4000 50 0001 C CNN
+ 1 1300 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR010
+U 1 1 69BE1A02
+P 1300 4350
+F 0 "#PWR010" H 1300 4100 50 0001 C CNN
+F 1 "GND" H 1300 4200 50 0000 C CNN
+F 2 "" H 1300 4350 50 0001 C CNN
+F 3 "" H 1300 4350 50 0001 C CNN
+ 1 1300 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR011
+U 1 1 69BE201F
+P 1300 4700
+F 0 "#PWR011" H 1300 4450 50 0001 C CNN
+F 1 "GND" H 1300 4550 50 0000 C CNN
+F 2 "" H 1300 4700 50 0001 C CNN
+F 3 "" H 1300 4700 50 0001 C CNN
+ 1 1300 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR012
+U 1 1 69BE2065
+P 900 5100
+F 0 "#PWR012" H 900 4850 50 0001 C CNN
+F 1 "GND" H 900 4950 50 0000 C CNN
+F 2 "" H 900 5100 50 0001 C CNN
+F 3 "" H 900 5100 50 0001 C CNN
+ 1 900 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR013
+U 1 1 69BE20AB
+P 900 5450
+F 0 "#PWR013" H 900 5200 50 0001 C CNN
+F 1 "GND" H 900 5300 50 0000 C CNN
+F 2 "" H 900 5450 50 0001 C CNN
+F 3 "" H 900 5450 50 0001 C CNN
+ 1 900 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR014
+U 1 1 69BE2150
+P 900 5800
+F 0 "#PWR014" H 900 5550 50 0001 C CNN
+F 1 "GND" H 900 5650 50 0000 C CNN
+F 2 "" H 900 5800 50 0001 C CNN
+F 3 "" H 900 5800 50 0001 C CNN
+ 1 900 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR015
+U 1 1 69BE2196
+P 900 6150
+F 0 "#PWR015" H 900 5900 50 0001 C CNN
+F 1 "GND" H 900 6000 50 0000 C CNN
+F 2 "" H 900 6150 50 0001 C CNN
+F 3 "" H 900 6150 50 0001 C CNN
+ 1 900 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR016
+U 1 1 69BE223B
+P 900 6550
+F 0 "#PWR016" H 900 6300 50 0001 C CNN
+F 1 "GND" H 900 6400 50 0000 C CNN
+F 2 "" H 900 6550 50 0001 C CNN
+F 3 "" H 900 6550 50 0001 C CNN
+ 1 900 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR017
+U 1 1 69BE22E0
+P 900 6900
+F 0 "#PWR017" H 900 6650 50 0001 C CNN
+F 1 "GND" H 900 6750 50 0000 C CNN
+F 2 "" H 900 6900 50 0001 C CNN
+F 3 "" H 900 6900 50 0001 C CNN
+ 1 900 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR018
+U 1 1 69BE26C3
+P 900 7250
+F 0 "#PWR018" H 900 7000 50 0001 C CNN
+F 1 "GND" H 900 7100 50 0000 C CNN
+F 2 "" H 900 7250 50 0001 C CNN
+F 3 "" H 900 7250 50 0001 C CNN
+ 1 900 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR019
+U 1 1 69BE274F
+P 900 7600
+F 0 "#PWR019" H 900 7350 50 0001 C CNN
+F 1 "GND" H 900 7450 50 0000 C CNN
+F 2 "" H 900 7600 50 0001 C CNN
+F 3 "" H 900 7600 50 0001 C CNN
+ 1 900 7600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG020
+U 1 1 69BE38DE
+P 800 800
+F 0 "#FLG020" H 800 875 50 0001 C CNN
+F 1 "PWR_FLAG" H 800 950 50 0000 C CNN
+F 2 "" H 800 800 50 0001 C CNN
+F 3 "" H 800 800 50 0001 C CNN
+ 1 800 800
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U27
+U 1 1 69BE674F
+P 9850 900
+F 0 "U27" H 9850 1400 60 0000 C CNN
+F 1 "plot_v1" H 10050 1250 60 0000 C CNN
+F 2 "" H 9850 900 60 0000 C CNN
+F 3 "" H 9850 900 60 0000 C CNN
+ 1 9850 900
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U28
+U 1 1 69BE6834
+P 9900 1350
+F 0 "U28" H 9900 1850 60 0000 C CNN
+F 1 "plot_v1" H 10100 1700 60 0000 C CNN
+F 2 "" H 9900 1350 60 0000 C CNN
+F 3 "" H 9900 1350 60 0000 C CNN
+ 1 9900 1350
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U31
+U 1 1 69BE68BF
+P 9950 1800
+F 0 "U31" H 9950 2300 60 0000 C CNN
+F 1 "plot_v1" H 10150 2150 60 0000 C CNN
+F 2 "" H 9950 1800 60 0000 C CNN
+F 3 "" H 9950 1800 60 0000 C CNN
+ 1 9950 1800
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U29
+U 1 1 69BE6A79
+P 9900 2300
+F 0 "U29" H 9900 2800 60 0000 C CNN
+F 1 "plot_v1" H 10100 2650 60 0000 C CNN
+F 2 "" H 9900 2300 60 0000 C CNN
+F 3 "" H 9900 2300 60 0000 C CNN
+ 1 9900 2300
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U32
+U 1 1 69BE6A80
+P 9950 2750
+F 0 "U32" H 9950 3250 60 0000 C CNN
+F 1 "plot_v1" H 10150 3100 60 0000 C CNN
+F 2 "" H 9950 2750 60 0000 C CNN
+F 3 "" H 9950 2750 60 0000 C CNN
+ 1 9950 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U34
+U 1 1 69BE6A87
+P 10000 3200
+F 0 "U34" H 10000 3700 60 0000 C CNN
+F 1 "plot_v1" H 10200 3550 60 0000 C CNN
+F 2 "" H 10000 3200 60 0000 C CNN
+F 3 "" H 10000 3200 60 0000 C CNN
+ 1 10000 3200
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U30
+U 1 1 69BE6C12
+P 9900 3700
+F 0 "U30" H 9900 4200 60 0000 C CNN
+F 1 "plot_v1" H 10100 4050 60 0000 C CNN
+F 2 "" H 9900 3700 60 0000 C CNN
+F 3 "" H 9900 3700 60 0000 C CNN
+ 1 9900 3700
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U33
+U 1 1 69BE6C19
+P 9950 4150
+F 0 "U33" H 9950 4650 60 0000 C CNN
+F 1 "plot_v1" H 10150 4500 60 0000 C CNN
+F 2 "" H 9950 4150 60 0000 C CNN
+F 3 "" H 9950 4150 60 0000 C CNN
+ 1 9950 4150
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U35
+U 1 1 69BE759D
+P 10050 4700
+F 0 "U35" H 10050 5200 60 0000 C CNN
+F 1 "plot_v1" H 10250 5050 60 0000 C CNN
+F 2 "" H 10050 4700 60 0000 C CNN
+F 3 "" H 10050 4700 60 0000 C CNN
+ 1 10050 4700
+ 0 1 1 0
+$EndComp
+Text GLabel 8550 900 1 60 Input ~ 0
+g7
+Text GLabel 8650 1350 1 60 Input ~ 0
+g6
+Text GLabel 8600 1800 1 60 Input ~ 0
+g5
+Text GLabel 9050 2300 1 60 Input ~ 0
+g4
+Text GLabel 9050 2750 1 60 Input ~ 0
+g3
+Text GLabel 9200 3200 1 60 Input ~ 0
+g2
+Text GLabel 9200 3700 1 60 Input ~ 0
+g1
+Text GLabel 9350 4150 1 60 Input ~ 0
+g0
+Text GLabel 9600 4700 1 60 Input ~ 0
+done
+Text GLabel 3750 950 1 60 Input ~ 0
+clk
+Text GLabel 3550 1300 1 60 Input ~ 0
+rst
+Text GLabel 3600 1700 1 60 Input ~ 0
+start
+Text GLabel 3550 2200 1 60 Input ~ 0
+a7
+Text GLabel 3600 2550 1 60 Input ~ 0
+a6
+Text GLabel 3450 2900 1 60 Input ~ 0
+a5
+Text GLabel 3500 3250 1 60 Input ~ 0
+a4
+Text GLabel 3500 3450 1 60 Input ~ 0
+a3
+Text GLabel 3450 3700 1 60 Input ~ 0
+a2
+Text GLabel 3500 3800 1 60 Input ~ 0
+a1
+Text GLabel 3300 3850 1 60 Input ~ 0
+a0
+Text GLabel 3900 3850 1 60 Input ~ 0
+b7
+Text GLabel 3750 3950 1 60 Input ~ 0
+b6
+Text GLabel 3900 4050 1 60 Input ~ 0
+b5
+Text GLabel 3750 4150 1 60 Input ~ 0
+b4
+Text GLabel 3950 4250 1 60 Input ~ 0
+b3
+Text GLabel 3900 4350 1 60 Input ~ 0
+b2
+Text GLabel 3800 4450 1 60 Input ~ 0
+b1
+Text GLabel 4000 4550 1 60 Input ~ 0
+b0
+$Comp
+L plot_v1 U13
+U 1 1 69BEAD9F
+P 2800 1050
+F 0 "U13" H 2800 1550 60 0000 C CNN
+F 1 "plot_v1" H 3000 1400 60 0000 C CNN
+F 2 "" H 2800 1050 60 0000 C CNN
+F 3 "" H 2800 1050 60 0000 C CNN
+ 1 2800 1050
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U18
+U 1 1 69BEAE0A
+P 3050 1350
+F 0 "U18" H 3050 1850 60 0000 C CNN
+F 1 "plot_v1" H 3250 1700 60 0000 C CNN
+F 2 "" H 3050 1350 60 0000 C CNN
+F 3 "" H 3050 1350 60 0000 C CNN
+ 1 3050 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U21
+U 1 1 69BEAE7B
+P 3200 1700
+F 0 "U21" H 3200 2200 60 0000 C CNN
+F 1 "plot_v1" H 3400 2050 60 0000 C CNN
+F 2 "" H 3200 1700 60 0000 C CNN
+F 3 "" H 3200 1700 60 0000 C CNN
+ 1 3200 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 69BEB975
+P 2350 2350
+F 0 "U5" H 2350 2850 60 0000 C CNN
+F 1 "plot_v1" H 2550 2700 60 0000 C CNN
+F 2 "" H 2350 2350 60 0000 C CNN
+F 3 "" H 2350 2350 60 0000 C CNN
+ 1 2350 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U7
+U 1 1 69BEB9FC
+P 2450 2650
+F 0 "U7" H 2450 3150 60 0000 C CNN
+F 1 "plot_v1" H 2650 3000 60 0000 C CNN
+F 2 "" H 2450 2650 60 0000 C CNN
+F 3 "" H 2450 2650 60 0000 C CNN
+ 1 2450 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U10
+U 1 1 69BEBA77
+P 2550 3000
+F 0 "U10" H 2550 3500 60 0000 C CNN
+F 1 "plot_v1" H 2750 3350 60 0000 C CNN
+F 2 "" H 2550 3000 60 0000 C CNN
+F 3 "" H 2550 3000 60 0000 C CNN
+ 1 2550 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U12
+U 1 1 69BEBAF6
+P 2700 3250
+F 0 "U12" H 2700 3750 60 0000 C CNN
+F 1 "plot_v1" H 2900 3600 60 0000 C CNN
+F 2 "" H 2700 3250 60 0000 C CNN
+F 3 "" H 2700 3250 60 0000 C CNN
+ 1 2700 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U16
+U 1 1 69BEBB6B
+P 2950 3600
+F 0 "U16" H 2950 4100 60 0000 C CNN
+F 1 "plot_v1" H 3150 3950 60 0000 C CNN
+F 2 "" H 2950 3600 60 0000 C CNN
+F 3 "" H 2950 3600 60 0000 C CNN
+ 1 2950 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U14
+U 1 1 69BEBC04
+P 2800 4100
+F 0 "U14" H 2800 4600 60 0000 C CNN
+F 1 "plot_v1" H 3000 4450 60 0000 C CNN
+F 2 "" H 2800 4100 60 0000 C CNN
+F 3 "" H 2800 4100 60 0000 C CNN
+ 1 2800 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U9
+U 1 1 69BEBC85
+P 2500 4500
+F 0 "U9" H 2500 5000 60 0000 C CNN
+F 1 "plot_v1" H 2700 4850 60 0000 C CNN
+F 2 "" H 2500 4500 60 0000 C CNN
+F 3 "" H 2500 4500 60 0000 C CNN
+ 1 2500 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U8
+U 1 1 69BEBD08
+P 2450 4850
+F 0 "U8" H 2450 5350 60 0000 C CNN
+F 1 "plot_v1" H 2650 5200 60 0000 C CNN
+F 2 "" H 2450 4850 60 0000 C CNN
+F 3 "" H 2450 4850 60 0000 C CNN
+ 1 2450 4850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3350 3450 4100 3450
+Wire Wire Line
+ 3350 3650 3350 3450
+Wire Wire Line
+ 2200 3650 3350 3650
+Wire Wire Line
+ 3550 3350 4100 3350
+Wire Wire Line
+ 3550 3250 3550 3350
+Wire Wire Line
+ 2200 3250 3550 3250
+Wire Wire Line
+ 3600 3250 4100 3250
+Wire Wire Line
+ 3600 2900 3600 3250
+Wire Wire Line
+ 2200 2900 3600 2900
+Wire Wire Line
+ 3650 3150 4100 3150
+Wire Wire Line
+ 3650 2550 3650 3150
+Wire Wire Line
+ 2200 2550 3650 2550
+Wire Wire Line
+ 3800 3050 4100 3050
+Wire Wire Line
+ 3800 2200 3800 3050
+Wire Wire Line
+ 2200 2200 3800 2200
+Wire Wire Line
+ 3900 2950 4100 2950
+Wire Wire Line
+ 3900 1700 3900 2950
+Wire Wire Line
+ 1800 1700 3900 1700
+Wire Wire Line
+ 4000 2850 4100 2850
+Wire Wire Line
+ 4000 1300 4000 2850
+Wire Wire Line
+ 1800 1300 4000 1300
+Wire Wire Line
+ 4100 950 4100 2750
+Wire Wire Line
+ 1800 950 4100 950
+Wire Wire Line
+ 2200 4000 2900 4000
+Wire Wire Line
+ 2900 4000 2900 3700
+Wire Wire Line
+ 2900 3700 3450 3700
+Wire Wire Line
+ 3450 3700 3450 3550
+Wire Wire Line
+ 3450 3550 4100 3550
+Wire Wire Line
+ 2200 4350 3050 4350
+Wire Wire Line
+ 3050 4350 3050 3800
+Wire Wire Line
+ 3050 3800 3550 3800
+Wire Wire Line
+ 3550 3800 3550 3650
+Wire Wire Line
+ 3550 3650 4100 3650
+Wire Wire Line
+ 2200 4700 3150 4700
+Wire Wire Line
+ 3150 4700 3150 3850
+Wire Wire Line
+ 3150 3850 3650 3850
+Wire Wire Line
+ 3650 3850 3650 3750
+Wire Wire Line
+ 3650 3750 4100 3750
+Wire Wire Line
+ 1800 5100 3350 5100
+Wire Wire Line
+ 3350 5100 3350 3900
+Wire Wire Line
+ 3350 3900 3800 3900
+Wire Wire Line
+ 3800 3900 3800 3850
+Wire Wire Line
+ 3800 3850 4100 3850
+Wire Wire Line
+ 1800 5450 3400 5450
+Wire Wire Line
+ 3400 5450 3400 3950
+Wire Wire Line
+ 3400 3950 4100 3950
+Wire Wire Line
+ 1800 5800 3500 5800
+Wire Wire Line
+ 3500 5800 3500 4050
+Wire Wire Line
+ 3500 4050 4100 4050
+Wire Wire Line
+ 1800 6150 3550 6150
+Wire Wire Line
+ 3550 6150 3550 4150
+Wire Wire Line
+ 3550 4150 4100 4150
+Wire Wire Line
+ 1800 6550 3600 6550
+Wire Wire Line
+ 3600 6550 3600 4250
+Wire Wire Line
+ 3600 4250 4100 4250
+Wire Wire Line
+ 1800 6900 3650 6900
+Wire Wire Line
+ 3650 6900 3650 4350
+Wire Wire Line
+ 3650 4350 4100 4350
+Wire Wire Line
+ 1800 7250 3750 7250
+Wire Wire Line
+ 3750 7250 3750 4450
+Wire Wire Line
+ 3750 4450 4100 4450
+Wire Wire Line
+ 1800 7600 3850 7600
+Wire Wire Line
+ 3850 7600 3850 4550
+Wire Wire Line
+ 3850 4550 4100 4550
+Wire Wire Line
+ 900 950 700 950
+Wire Wire Line
+ 700 950 700 1000
+Wire Wire Line
+ 800 800 800 950
+Connection ~ 800 950
+Wire Wire Line
+ 10050 900 7800 900
+Wire Wire Line
+ 7800 900 7800 2750
+Wire Wire Line
+ 10100 1350 7950 1350
+Wire Wire Line
+ 7950 1350 7950 2850
+Wire Wire Line
+ 7950 2850 7800 2850
+Wire Wire Line
+ 10150 1800 8200 1800
+Wire Wire Line
+ 8200 1800 8200 2950
+Wire Wire Line
+ 8200 2950 7800 2950
+Wire Wire Line
+ 10100 2300 8400 2300
+Wire Wire Line
+ 8400 2300 8400 3050
+Wire Wire Line
+ 8400 3050 7800 3050
+Wire Wire Line
+ 7800 3150 8650 3150
+Wire Wire Line
+ 8650 3150 8650 2750
+Wire Wire Line
+ 8650 2750 10150 2750
+Wire Wire Line
+ 10200 3200 7800 3200
+Wire Wire Line
+ 7800 3200 7800 3250
+Wire Wire Line
+ 10100 3700 8650 3700
+Wire Wire Line
+ 8650 3700 8650 3350
+Wire Wire Line
+ 8650 3350 7800 3350
+Wire Wire Line
+ 10150 4150 8250 4150
+Wire Wire Line
+ 8250 4150 8250 3450
+Wire Wire Line
+ 8250 3450 7800 3450
+Wire Wire Line
+ 10250 4700 7850 4700
+Wire Wire Line
+ 7850 4700 7850 3550
+Wire Wire Line
+ 7850 3550 7800 3550
+Wire Wire Line
+ 2800 850 2800 950
+Connection ~ 2800 950
+Wire Wire Line
+ 3050 1150 3050 1300
+Wire Wire Line
+ 3050 1300 3000 1300
+Connection ~ 3000 1300
+Wire Wire Line
+ 3200 1500 3200 1700
+Connection ~ 3200 1700
+Wire Wire Line
+ 2350 2150 2350 2200
+Connection ~ 2350 2200
+Wire Wire Line
+ 2450 2450 2450 2550
+Connection ~ 2450 2550
+Wire Wire Line
+ 2550 2800 2550 2900
+Connection ~ 2550 2900
+Wire Wire Line
+ 2700 3050 2700 3250
+Connection ~ 2700 3250
+Wire Wire Line
+ 2950 3400 2950 3650
+Connection ~ 2950 3650
+Wire Wire Line
+ 2800 3900 2800 4000
+Connection ~ 2800 4000
+Wire Wire Line
+ 2500 4300 2500 4350
+Connection ~ 2500 4350
+Wire Wire Line
+ 2450 4650 2450 4700
+Connection ~ 2450 4700
+$Comp
+L plot_v1 U1
+U 1 1 69BED981
+P 1900 5200
+F 0 "U1" H 1900 5700 60 0000 C CNN
+F 1 "plot_v1" H 2100 5550 60 0000 C CNN
+F 2 "" H 1900 5200 60 0000 C CNN
+F 3 "" H 1900 5200 60 0000 C CNN
+ 1 1900 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U2
+U 1 1 69BEDA18
+P 2050 5600
+F 0 "U2" H 2050 6100 60 0000 C CNN
+F 1 "plot_v1" H 2250 5950 60 0000 C CNN
+F 2 "" H 2050 5600 60 0000 C CNN
+F 3 "" H 2050 5600 60 0000 C CNN
+ 1 2050 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U3
+U 1 1 69BEDA95
+P 2050 5600
+F 0 "U3" H 2050 6100 60 0000 C CNN
+F 1 "plot_v1" H 2250 5950 60 0000 C CNN
+F 2 "" H 2050 5600 60 0000 C CNN
+F 3 "" H 2050 5600 60 0000 C CNN
+ 1 2050 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 69BEDB0A
+P 2250 5950
+F 0 "U4" H 2250 6450 60 0000 C CNN
+F 1 "plot_v1" H 2450 6300 60 0000 C CNN
+F 2 "" H 2250 5950 60 0000 C CNN
+F 3 "" H 2250 5950 60 0000 C CNN
+ 1 2250 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 69BEDBA5
+P 2400 6250
+F 0 "U6" H 2400 6750 60 0000 C CNN
+F 1 "plot_v1" H 2600 6600 60 0000 C CNN
+F 2 "" H 2400 6250 60 0000 C CNN
+F 3 "" H 2400 6250 60 0000 C CNN
+ 1 2400 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U11
+U 1 1 69BEDC34
+P 2600 6650
+F 0 "U11" H 2600 7150 60 0000 C CNN
+F 1 "plot_v1" H 2800 7000 60 0000 C CNN
+F 2 "" H 2600 6650 60 0000 C CNN
+F 3 "" H 2600 6650 60 0000 C CNN
+ 1 2600 6650
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U15
+U 1 1 69BEE48C
+P 2850 7050
+F 0 "U15" H 2850 7550 60 0000 C CNN
+F 1 "plot_v1" H 3050 7400 60 0000 C CNN
+F 2 "" H 2850 7050 60 0000 C CNN
+F 3 "" H 2850 7050 60 0000 C CNN
+ 1 2850 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U17
+U 1 1 69BEE565
+P 3000 7400
+F 0 "U17" H 3000 7900 60 0000 C CNN
+F 1 "plot_v1" H 3200 7750 60 0000 C CNN
+F 2 "" H 3000 7400 60 0000 C CNN
+F 3 "" H 3000 7400 60 0000 C CNN
+ 1 3000 7400
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U20
+U 1 1 69BEE602
+P 3150 7750
+F 0 "U20" H 3150 8250 60 0000 C CNN
+F 1 "plot_v1" H 3350 8100 60 0000 C CNN
+F 2 "" H 3150 7750 60 0000 C CNN
+F 3 "" H 3150 7750 60 0000 C CNN
+ 1 3150 7750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1900 5000 1900 5100
+Connection ~ 1900 5100
+Wire Wire Line
+ 2050 5400 2050 5450
+Connection ~ 2050 5450
+Wire Wire Line
+ 2250 5750 2250 5800
+Connection ~ 2250 5800
+Wire Wire Line
+ 2400 6050 2400 6150
+Connection ~ 2400 6150
+Wire Wire Line
+ 2600 6450 2600 6550
+Connection ~ 2600 6550
+Wire Wire Line
+ 2850 6850 2850 6900
+Connection ~ 2850 6900
+Wire Wire Line
+ 3000 7200 3000 7250
+Connection ~ 3000 7250
+Wire Wire Line
+ 3150 7550 3150 7600
+Wire Wire Line
+ 3150 7600 3100 7600
+Connection ~ 3100 7600
+$EndSCHEMATC
diff --git a/fossee/gcd/gcd_seq/gcd_seq_Previous_Values.xml b/fossee/gcd/gcd_seq/gcd_seq_Previous_Values.xml
new file mode 100644
index 000000000..56c72cfab
--- /dev/null
+++ b/fossee/gcd/gcd_seq/gcd_seq_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01200secnsnspulse010.01ns0.01ns0.01ns10ns20nspulse010.01ns0.01ns0.01ns10ns200nspulse010.01ns0.01ns0.01ns15ns100nsdcdcdcdcdcdcdcdcdcdcdcdcdcdcdcdcgcd_seqadc_bridgeadc_bridgeadc_bridgedac_bridgedac_bridge
\ No newline at end of file
diff --git a/fossee/sync_fifo/sync_fif0/analysis b/fossee/sync_fifo/sync_fif0/analysis
new file mode 100644
index 000000000..9b264de7a
--- /dev/null
+++ b/fossee/sync_fifo/sync_fif0/analysis
@@ -0,0 +1 @@
+.tran 1e-09 450e-09 0e-09
\ No newline at end of file
diff --git a/fossee/sync_fifo/sync_fif0/sync_fif0-cache.lib b/fossee/sync_fifo/sync_fif0/sync_fif0-cache.lib
new file mode 100644
index 000000000..1ade33d25
--- /dev/null
+++ b/fossee/sync_fifo/sync_fif0/sync_fif0-cache.lib
@@ -0,0 +1,192 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_8
+#
+DEF adc_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sync_fifo
+#
+DEF sync_fifo U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "sync_fifo" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 600 0 1 0 N
+X clk0 1 2150 1900 200 R 50 50 1 1 I
+X rst0 2 2150 1800 200 R 50 50 1 1 I
+X wr_en0 3 2150 1700 200 R 50 50 1 1 I
+X rd_en0 4 2150 1600 200 R 50 50 1 1 I
+X din7 5 2150 1500 200 R 50 50 1 1 I
+X din6 6 2150 1400 200 R 50 50 1 1 I
+X din5 7 2150 1300 200 R 50 50 1 1 I
+X din4 8 2150 1200 200 R 50 50 1 1 I
+X din3 9 2150 1100 200 R 50 50 1 1 I
+X din2 10 2150 1000 200 R 50 50 1 1 I
+X dout0 20 3550 1200 200 L 50 50 1 1 O
+X din1 11 2150 900 200 R 50 50 1 1 I
+X full0 21 3550 1100 200 L 50 50 1 1 O
+X din0 12 2150 800 200 R 50 50 1 1 I
+X empty0 22 3550 1000 200 L 50 50 1 1 O
+X dout7 13 3550 1900 200 L 50 50 1 1 O
+X dout6 14 3550 1800 200 L 50 50 1 1 O
+X dout5 15 3550 1700 200 L 50 50 1 1 O
+X dout4 16 3550 1600 200 L 50 50 1 1 O
+X dout3 17 3550 1500 200 L 50 50 1 1 O
+X dout2 18 3550 1400 200 L 50 50 1 1 O
+X dout1 19 3550 1300 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/fossee/sync_fifo/sync_fif0/sync_fif0.cir b/fossee/sync_fifo/sync_fif0/sync_fif0.cir
new file mode 100644
index 000000000..95fc3dad8
--- /dev/null
+++ b/fossee/sync_fifo/sync_fif0/sync_fif0.cir
@@ -0,0 +1,49 @@
+* C:\Users\VLSI\eSim-Workspace\sync_fif0\sync_fif0.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/03/2026 21:27:29
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ Net-_U12-Pad4_ Net-_U12-Pad5_ Net-_U12-Pad6_ Net-_U12-Pad7_ Net-_U12-Pad8_ Net-_U12-Pad9_ Net-_U12-Pad10_ Net-_U12-Pad11_ Net-_U12-Pad12_ Net-_U12-Pad13_ Net-_U12-Pad14_ Net-_U12-Pad15_ Net-_U12-Pad16_ Net-_U12-Pad17_ Net-_U12-Pad18_ Net-_U12-Pad19_ Net-_U12-Pad20_ Net-_U12-Pad21_ Net-_U12-Pad22_ sync_fifo
+U15 d7 d6 d5 d4 d3 d2 d1 d0 Net-_U12-Pad5_ Net-_U12-Pad6_ Net-_U12-Pad7_ Net-_U12-Pad8_ Net-_U12-Pad9_ Net-_U12-Pad10_ Net-_U12-Pad11_ Net-_U12-Pad12_ adc_bridge_8
+U14 clk0 rst0 wr_en0 rd_en0 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ Net-_U12-Pad4_ adc_bridge_4
+U16 Net-_U12-Pad13_ Net-_U12-Pad14_ Net-_U12-Pad15_ Net-_U12-Pad16_ Net-_U12-Pad17_ Net-_U12-Pad18_ Net-_U12-Pad19_ Net-_U12-Pad20_ q7 q6 q5 q4 q3 q2 q1 q0 dac_bridge_8
+U17 Net-_U12-Pad21_ Net-_U12-Pad22_ full0 empty0 dac_bridge_2
+v1 clk0 GND pulse
+v2 rst0 GND pulse
+v3 wr_en0 GND pulse
+v4 rd_en0 GND pulse
+v5 d7 GND pulse
+v6 d6 GND pulse
+v7 d5 GND pulse
+v8 d4 GND pulse
+v9 d3 GND pulse
+v10 d2 GND pulse
+v11 d1 GND pulse
+v12 d0 GND pulse
+U2 clk0 plot_v1
+U4 rst0 plot_v1
+U6 wr_en0 plot_v1
+U8 rd_en0 plot_v1
+U3 d6 plot_v1
+U5 d5 plot_v1
+U7 d4 plot_v1
+U9 d3 plot_v1
+U10 d2 plot_v1
+U11 d1 plot_v1
+U13 d0 plot_v1
+U1 d7 plot_v1
+U18 q7 plot_v1
+U19 q6 plot_v1
+U20 q5 plot_v1
+U21 q4 plot_v1
+U22 q3 plot_v1
+U23 q2 plot_v1
+U24 q1 plot_v1
+U25 q0 plot_v1
+U26 full0 plot_v1
+U27 empty0 plot_v1
+
+.end
diff --git a/fossee/sync_fifo/sync_fif0/sync_fif0.cir.out b/fossee/sync_fifo/sync_fif0/sync_fif0.cir.out
new file mode 100644
index 000000000..959e91d18
--- /dev/null
+++ b/fossee/sync_fifo/sync_fif0/sync_fif0.cir.out
@@ -0,0 +1,68 @@
+* c:\users\vlsi\esim-workspace\sync_fif0\sync_fif0.cir
+
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u12-pad5_ net-_u12-pad6_ net-_u12-pad7_ net-_u12-pad8_ net-_u12-pad9_ net-_u12-pad10_ net-_u12-pad11_ net-_u12-pad12_ net-_u12-pad13_ net-_u12-pad14_ net-_u12-pad15_ net-_u12-pad16_ net-_u12-pad17_ net-_u12-pad18_ net-_u12-pad19_ net-_u12-pad20_ net-_u12-pad21_ net-_u12-pad22_ sync_fifo
+* u15 d7 d6 d5 d4 d3 d2 d1 d0 net-_u12-pad5_ net-_u12-pad6_ net-_u12-pad7_ net-_u12-pad8_ net-_u12-pad9_ net-_u12-pad10_ net-_u12-pad11_ net-_u12-pad12_ adc_bridge_8
+* u14 clk0 rst0 wr_en0 rd_en0 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ adc_bridge_4
+* u16 net-_u12-pad13_ net-_u12-pad14_ net-_u12-pad15_ net-_u12-pad16_ net-_u12-pad17_ net-_u12-pad18_ net-_u12-pad19_ net-_u12-pad20_ q7 q6 q5 q4 q3 q2 q1 q0 dac_bridge_8
+* u17 net-_u12-pad21_ net-_u12-pad22_ full0 empty0 dac_bridge_2
+v1 clk0 gnd pulse(0 1 0.01ns 0.001ns 0.001ns 10ns 20ns)
+v2 rst0 gnd pulse(0 1 40n 1n 1n 1000n 2000n)
+v3 wr_en0 gnd pulse(0 1 60n 1n 1n 120n 240n)
+v4 rd_en0 gnd pulse(0 1 200n 1n 1n 120n 240n)
+v12 d0 gnd pulse(0 1 60n 1n 1n 20n 40n)
+v11 d1 gnd pulse(0 1 80n 1n 1n 40n 80n)
+v10 d2 gnd pulse(0 1 120n 1n 1n 80n 160n)
+v9 d3 gnd pulse(0 0 0 0 0 0 0)
+v8 d4 gnd pulse(0 0 0 0 0 0 0)
+v7 d5 gnd pulse(0 0 0 0 0 0 0)
+v6 d6 gnd pulse(0 0 0 0 0 0 0)
+v5 d7 gnd pulse(0 0 0 0 0 0 0)
+
+
+* u2 clk0 plot_v1
+* u4 rst0 plot_v1
+* u6 wr_en0 plot_v1
+* u8 rd_en0 plot_v1
+* u3 d6 plot_v1
+* u5 d5 plot_v1
+* u7 d4 plot_v1
+* u9 d3 plot_v1
+* u10 d2 plot_v1
+* u11 d1 plot_v1
+* u13 d0 plot_v1
+* u1 d7 plot_v1
+* u18 q7 plot_v1
+* u19 q6 plot_v1
+* u20 q5 plot_v1
+* u21 q4 plot_v1
+* u22 q3 plot_v1
+* u23 q2 plot_v1
+* u24 q1 plot_v1
+* u25 q0 plot_v1
+* u26 full0 plot_v1
+* u27 empty0 plot_v1
+a1 [net-_u12-pad1_ ] [net-_u12-pad2_ ] [net-_u12-pad3_ ] [net-_u12-pad4_ ] [net-_u12-pad5_ net-_u12-pad6_ net-_u12-pad7_ net-_u12-pad8_ net-_u12-pad9_ net-_u12-pad10_ net-_u12-pad11_ net-_u12-pad12_ ] [net-_u12-pad13_ net-_u12-pad14_ net-_u12-pad15_ net-_u12-pad16_ net-_u12-pad17_ net-_u12-pad18_ net-_u12-pad19_ net-_u12-pad20_ ] [net-_u12-pad21_ ] [net-_u12-pad22_ ] u12
+a2 [d7 d6 d5 d4 d3 d2 d1 d0 ] [net-_u12-pad5_ net-_u12-pad6_ net-_u12-pad7_ net-_u12-pad8_ net-_u12-pad9_ net-_u12-pad10_ net-_u12-pad11_ net-_u12-pad12_ ] u15
+a3 [clk0 rst0 wr_en0 rd_en0 ] [net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ ] u14
+a4 [net-_u12-pad13_ net-_u12-pad14_ net-_u12-pad15_ net-_u12-pad16_ net-_u12-pad17_ net-_u12-pad18_ net-_u12-pad19_ net-_u12-pad20_ ] [q7 q6 q5 q4 q3 q2 q1 q0 ] u16
+a5 [net-_u12-pad21_ net-_u12-pad22_ ] [full0 empty0 ] u17
+* Schematic Name: sync_fifo, NgSpice Name: sync_fifo
+.model u12 sync_fifo(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge
+.model u15 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u14 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 1e-09 450e-09 0e-09
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(q0)+6 v(q1)+12 v(q2)+18 v(q3)+24 v(q4)+30 v(q5)+36 v(q6)+42 v(q7)+48 v(full0)+54 v(empty0)+60 v(d0)+66 v(d1)+72 v(d2)+78 v(d3)+84 v(d4)+90 v(d5)+96 v(d6)+102 v(d7)+108 v(wr_en0)+114 v(rd_en0)+120 v(rst0)+126 v(clk0)+132
+.endc
+.end
diff --git a/fossee/sync_fifo/sync_fif0/sync_fif0.pro b/fossee/sync_fifo/sync_fif0/sync_fif0.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/fossee/sync_fifo/sync_fif0/sync_fif0.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/fossee/sync_fifo/sync_fif0/sync_fif0.proj b/fossee/sync_fifo/sync_fif0/sync_fif0.proj
new file mode 100644
index 000000000..86bfa7ac6
--- /dev/null
+++ b/fossee/sync_fifo/sync_fif0/sync_fif0.proj
@@ -0,0 +1 @@
+schematicFile sync_fif0.sch
diff --git a/fossee/sync_fifo/sync_fif0/sync_fif0.sch b/fossee/sync_fifo/sync_fif0/sync_fif0.sch
new file mode 100644
index 000000000..660e8ef68
--- /dev/null
+++ b/fossee/sync_fifo/sync_fif0/sync_fif0.sch
@@ -0,0 +1,873 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sync_fifo U?
+U 1 1 69A5B0B5
+P 3000 4750
+F 0 "U?" H 5850 6550 60 0000 C CNN
+F 1 "sync_fifo" H 5850 6750 60 0000 C CNN
+F 2 "" H 5850 6700 60 0000 C CNN
+F 3 "" H 5850 6700 60 0000 C CNN
+ 1 3000 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_8 U?
+U 1 1 69A5B0FC
+P 4600 3300
+F 0 "U?" H 4600 3300 60 0000 C CNN
+F 1 "adc_bridge_8" H 4600 3450 60 0000 C CNN
+F 2 "" H 4600 3300 60 0000 C CNN
+F 3 "" H 4600 3300 60 0000 C CNN
+ 1 4600 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_4 U?
+U 1 1 69A5B15F
+P 4000 2350
+F 0 "U?" H 4000 2350 60 0000 C CNN
+F 1 "adc_bridge_4" H 4000 2650 60 0000 C CNN
+F 2 "" H 4000 2350 60 0000 C CNN
+F 3 "" H 4000 2350 60 0000 C CNN
+ 1 4000 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_8 U?
+U 1 1 69A5B1EE
+P 7150 2900
+F 0 "U?" H 7150 2900 60 0000 C CNN
+F 1 "dac_bridge_8" H 7150 3050 60 0000 C CNN
+F 2 "" H 7150 2900 60 0000 C CNN
+F 3 "" H 7150 2900 60 0000 C CNN
+ 1 7150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_2 U?
+U 1 1 69A5B249
+P 7150 3950
+F 0 "U?" H 7150 3950 60 0000 C CNN
+F 1 "dac_bridge_2" H 7200 4100 60 0000 C CNN
+F 2 "" H 7150 3950 60 0000 C CNN
+F 3 "" H 7150 3950 60 0000 C CNN
+ 1 7150 3950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4550 2150 5150 2150
+Wire Wire Line
+ 5150 2150 5150 2850
+Wire Wire Line
+ 4550 2250 5100 2250
+Wire Wire Line
+ 5100 2250 5100 2950
+Wire Wire Line
+ 5100 2950 5150 2950
+Wire Wire Line
+ 4550 2350 5050 2350
+Wire Wire Line
+ 5050 2350 5050 3000
+Wire Wire Line
+ 5050 3000 5150 3000
+Wire Wire Line
+ 5150 3000 5150 3050
+Wire Wire Line
+ 4550 2450 5000 2450
+Wire Wire Line
+ 5000 2450 5000 3150
+Wire Wire Line
+ 5000 3150 5150 3150
+Wire Wire Line
+ 6550 3650 6700 3650
+Wire Wire Line
+ 6700 3650 6700 3900
+Wire Wire Line
+ 6550 3750 6650 3750
+Wire Wire Line
+ 6650 3750 6650 4000
+Wire Wire Line
+ 6650 4000 6700 4000
+$Comp
+L pulse v?
+U 1 1 69A5B5A1
+P 1200 1450
+F 0 "v?" H 1000 1550 60 0000 C CNN
+F 1 "pulse" H 1000 1400 60 0000 C CNN
+F 2 "R1" H 900 1450 60 0000 C CNN
+F 3 "" H 1200 1450 60 0000 C CNN
+ 1 1200 1450
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B5E0
+P 1200 1800
+F 0 "v?" H 1000 1900 60 0000 C CNN
+F 1 "pulse" H 1000 1750 60 0000 C CNN
+F 2 "R1" H 900 1800 60 0000 C CNN
+F 3 "" H 1200 1800 60 0000 C CNN
+ 1 1200 1800
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B61D
+P 1200 2150
+F 0 "v?" H 1000 2250 60 0000 C CNN
+F 1 "pulse" H 1000 2100 60 0000 C CNN
+F 2 "R1" H 900 2150 60 0000 C CNN
+F 3 "" H 1200 2150 60 0000 C CNN
+ 1 1200 2150
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B660
+P 1200 2500
+F 0 "v?" H 1000 2600 60 0000 C CNN
+F 1 "pulse" H 1000 2450 60 0000 C CNN
+F 2 "R1" H 900 2500 60 0000 C CNN
+F 3 "" H 1200 2500 60 0000 C CNN
+ 1 1200 2500
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B704
+P 1200 3150
+F 0 "v?" H 1000 3250 60 0000 C CNN
+F 1 "pulse" H 1000 3100 60 0000 C CNN
+F 2 "R1" H 900 3150 60 0000 C CNN
+F 3 "" H 1200 3150 60 0000 C CNN
+ 1 1200 3150
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B70B
+P 1200 3500
+F 0 "v?" H 1000 3600 60 0000 C CNN
+F 1 "pulse" H 1000 3450 60 0000 C CNN
+F 2 "R1" H 900 3500 60 0000 C CNN
+F 3 "" H 1200 3500 60 0000 C CNN
+ 1 1200 3500
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B712
+P 1200 3850
+F 0 "v?" H 1000 3950 60 0000 C CNN
+F 1 "pulse" H 1000 3800 60 0000 C CNN
+F 2 "R1" H 900 3850 60 0000 C CNN
+F 3 "" H 1200 3850 60 0000 C CNN
+ 1 1200 3850
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B719
+P 1200 4200
+F 0 "v?" H 1000 4300 60 0000 C CNN
+F 1 "pulse" H 1000 4150 60 0000 C CNN
+F 2 "R1" H 900 4200 60 0000 C CNN
+F 3 "" H 1200 4200 60 0000 C CNN
+ 1 1200 4200
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B9A1
+P 1200 4550
+F 0 "v?" H 1000 4650 60 0000 C CNN
+F 1 "pulse" H 1000 4500 60 0000 C CNN
+F 2 "R1" H 900 4550 60 0000 C CNN
+F 3 "" H 1200 4550 60 0000 C CNN
+ 1 1200 4550
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B9A8
+P 1200 4900
+F 0 "v?" H 1000 5000 60 0000 C CNN
+F 1 "pulse" H 1000 4850 60 0000 C CNN
+F 2 "R1" H 900 4900 60 0000 C CNN
+F 3 "" H 1200 4900 60 0000 C CNN
+ 1 1200 4900
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B9AF
+P 1200 5250
+F 0 "v?" H 1000 5350 60 0000 C CNN
+F 1 "pulse" H 1000 5200 60 0000 C CNN
+F 2 "R1" H 900 5250 60 0000 C CNN
+F 3 "" H 1200 5250 60 0000 C CNN
+ 1 1200 5250
+ 0 1 1 0
+$EndComp
+$Comp
+L pulse v?
+U 1 1 69A5B9B6
+P 1200 5600
+F 0 "v?" H 1000 5700 60 0000 C CNN
+F 1 "pulse" H 1000 5550 60 0000 C CNN
+F 2 "R1" H 900 5600 60 0000 C CNN
+F 3 "" H 1200 5600 60 0000 C CNN
+ 1 1200 5600
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 1650 1450 3450 1450
+Wire Wire Line
+ 3450 1450 3450 2150
+Wire Wire Line
+ 1650 1800 3350 1800
+Wire Wire Line
+ 3350 1800 3350 2250
+Wire Wire Line
+ 3350 2250 3450 2250
+Wire Wire Line
+ 1650 2150 3300 2150
+Wire Wire Line
+ 3300 2150 3300 2350
+Wire Wire Line
+ 3300 2350 3450 2350
+Wire Wire Line
+ 1650 2500 3450 2500
+Wire Wire Line
+ 3450 2500 3450 2450
+Wire Wire Line
+ 1650 3150 4000 3150
+Wire Wire Line
+ 4000 3150 4000 3250
+Wire Wire Line
+ 1650 3500 1700 3500
+Wire Wire Line
+ 1700 3500 1700 3350
+Wire Wire Line
+ 1700 3350 4000 3350
+Wire Wire Line
+ 1650 3850 1750 3850
+Wire Wire Line
+ 1750 3850 1750 3450
+Wire Wire Line
+ 1750 3450 4000 3450
+Wire Wire Line
+ 1650 4200 2250 4200
+Wire Wire Line
+ 2250 4200 2250 3550
+Wire Wire Line
+ 2250 3550 4000 3550
+Wire Wire Line
+ 1650 4550 2400 4550
+Wire Wire Line
+ 2400 4550 2400 3650
+Wire Wire Line
+ 2400 3650 4000 3650
+Wire Wire Line
+ 1650 4900 2550 4900
+Wire Wire Line
+ 2550 4900 2550 3750
+Wire Wire Line
+ 2550 3750 4000 3750
+Wire Wire Line
+ 1650 5250 2850 5250
+Wire Wire Line
+ 2850 5250 2850 3850
+Wire Wire Line
+ 2850 3850 4000 3850
+Wire Wire Line
+ 1650 5600 3100 5600
+Wire Wire Line
+ 3100 5600 3100 3950
+Wire Wire Line
+ 3100 3950 4000 3950
+$Comp
+L GND #PWR?
+U 1 1 69A5C651
+P 550 1350
+F 0 "#PWR?" H 550 1100 50 0001 C CNN
+F 1 "GND" H 550 1200 50 0000 C CNN
+F 2 "" H 550 1350 50 0001 C CNN
+F 3 "" H 550 1350 50 0001 C CNN
+ 1 550 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5C687
+P 750 1800
+F 0 "#PWR?" H 750 1550 50 0001 C CNN
+F 1 "GND" H 750 1650 50 0000 C CNN
+F 2 "" H 750 1800 50 0001 C CNN
+F 3 "" H 750 1800 50 0001 C CNN
+ 1 750 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5C6BD
+P 750 2150
+F 0 "#PWR?" H 750 1900 50 0001 C CNN
+F 1 "GND" H 750 2000 50 0000 C CNN
+F 2 "" H 750 2150 50 0001 C CNN
+F 3 "" H 750 2150 50 0001 C CNN
+ 1 750 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5C6F3
+P 750 2500
+F 0 "#PWR?" H 750 2250 50 0001 C CNN
+F 1 "GND" H 750 2350 50 0000 C CNN
+F 2 "" H 750 2500 50 0001 C CNN
+F 3 "" H 750 2500 50 0001 C CNN
+ 1 750 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5C729
+P 750 3150
+F 0 "#PWR?" H 750 2900 50 0001 C CNN
+F 1 "GND" H 750 3000 50 0000 C CNN
+F 2 "" H 750 3150 50 0001 C CNN
+F 3 "" H 750 3150 50 0001 C CNN
+ 1 750 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5CA4B
+P 750 3500
+F 0 "#PWR?" H 750 3250 50 0001 C CNN
+F 1 "GND" H 750 3350 50 0000 C CNN
+F 2 "" H 750 3500 50 0001 C CNN
+F 3 "" H 750 3500 50 0001 C CNN
+ 1 750 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5CA81
+P 750 3850
+F 0 "#PWR?" H 750 3600 50 0001 C CNN
+F 1 "GND" H 750 3700 50 0000 C CNN
+F 2 "" H 750 3850 50 0001 C CNN
+F 3 "" H 750 3850 50 0001 C CNN
+ 1 750 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5CAFE
+P 750 4200
+F 0 "#PWR?" H 750 3950 50 0001 C CNN
+F 1 "GND" H 750 4050 50 0000 C CNN
+F 2 "" H 750 4200 50 0001 C CNN
+F 3 "" H 750 4200 50 0001 C CNN
+ 1 750 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5CB34
+P 750 4550
+F 0 "#PWR?" H 750 4300 50 0001 C CNN
+F 1 "GND" H 750 4400 50 0000 C CNN
+F 2 "" H 750 4550 50 0001 C CNN
+F 3 "" H 750 4550 50 0001 C CNN
+ 1 750 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5CEAB
+P 750 4900
+F 0 "#PWR?" H 750 4650 50 0001 C CNN
+F 1 "GND" H 750 4750 50 0000 C CNN
+F 2 "" H 750 4900 50 0001 C CNN
+F 3 "" H 750 4900 50 0001 C CNN
+ 1 750 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5CEE1
+P 750 5250
+F 0 "#PWR?" H 750 5000 50 0001 C CNN
+F 1 "GND" H 750 5100 50 0000 C CNN
+F 2 "" H 750 5250 50 0001 C CNN
+F 3 "" H 750 5250 50 0001 C CNN
+ 1 750 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 69A5CF17
+P 750 5600
+F 0 "#PWR?" H 750 5350 50 0001 C CNN
+F 1 "GND" H 750 5450 50 0000 C CNN
+F 2 "" H 750 5600 50 0001 C CNN
+F 3 "" H 750 5600 50 0001 C CNN
+ 1 750 5600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 550 1350 750 1350
+Wire Wire Line
+ 750 1350 750 1450
+$Comp
+L PWR_FLAG #FLG?
+U 1 1 69A5D504
+P 650 1200
+F 0 "#FLG?" H 650 1275 50 0001 C CNN
+F 1 "PWR_FLAG" H 650 1350 50 0000 C CNN
+F 2 "" H 650 1200 50 0001 C CNN
+F 3 "" H 650 1200 50 0001 C CNN
+ 1 650 1200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 650 1200 650 1350
+Wire Wire Line
+ 650 1350 700 1350
+Connection ~ 700 1350
+Text GLabel 2800 1450 1 60 Input ~ 0
+clk0
+Text GLabel 3150 1800 1 60 Input ~ 0
+rst0
+Text GLabel 3050 2150 1 60 Input ~ 0
+wr_en0
+Text GLabel 3200 2500 1 60 Input ~ 0
+rd_en0
+Text GLabel 3650 3150 1 60 Input ~ 0
+d7
+Text GLabel 3700 3350 1 60 Input ~ 0
+d6
+Text GLabel 3700 3450 1 60 Input ~ 0
+d5
+Text GLabel 3600 3550 1 60 Input ~ 0
+d4
+Text GLabel 3950 3650 1 60 Input ~ 0
+d3
+Text GLabel 3850 3750 1 60 Input ~ 0
+d2
+Text GLabel 3750 3850 1 60 Input ~ 0
+d1
+Text GLabel 3550 3950 1 60 Input ~ 0
+d0
+$Comp
+L plot_v1 U?
+U 1 1 69A5F1FE
+P 1800 1550
+F 0 "U?" H 1800 2050 60 0000 C CNN
+F 1 "plot_v1" H 2000 1900 60 0000 C CNN
+F 2 "" H 1800 1550 60 0000 C CNN
+F 3 "" H 1800 1550 60 0000 C CNN
+ 1 1800 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5F295
+P 2100 1800
+F 0 "U?" H 2100 2300 60 0000 C CNN
+F 1 "plot_v1" H 2300 2150 60 0000 C CNN
+F 2 "" H 2100 1800 60 0000 C CNN
+F 3 "" H 2100 1800 60 0000 C CNN
+ 1 2100 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5F2D8
+P 2300 2100
+F 0 "U?" H 2300 2600 60 0000 C CNN
+F 1 "plot_v1" H 2500 2450 60 0000 C CNN
+F 2 "" H 2300 2100 60 0000 C CNN
+F 3 "" H 2300 2100 60 0000 C CNN
+ 1 2300 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5F321
+P 2550 2400
+F 0 "U?" H 2550 2900 60 0000 C CNN
+F 1 "plot_v1" H 2750 2750 60 0000 C CNN
+F 2 "" H 2550 2400 60 0000 C CNN
+F 3 "" H 2550 2400 60 0000 C CNN
+ 1 2550 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5F907
+P 1900 3500
+F 0 "U?" H 1900 4000 60 0000 C CNN
+F 1 "plot_v1" H 2100 3850 60 0000 C CNN
+F 2 "" H 1900 3500 60 0000 C CNN
+F 3 "" H 1900 3500 60 0000 C CNN
+ 1 1900 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5F956
+P 2150 3600
+F 0 "U?" H 2150 4100 60 0000 C CNN
+F 1 "plot_v1" H 2350 3950 60 0000 C CNN
+F 2 "" H 2150 3600 60 0000 C CNN
+F 3 "" H 2150 3600 60 0000 C CNN
+ 1 2150 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5F9AF
+P 2350 3700
+F 0 "U?" H 2350 4200 60 0000 C CNN
+F 1 "plot_v1" H 2550 4050 60 0000 C CNN
+F 2 "" H 2350 3700 60 0000 C CNN
+F 3 "" H 2350 3700 60 0000 C CNN
+ 1 2350 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5FA0A
+P 2550 3800
+F 0 "U?" H 2550 4300 60 0000 C CNN
+F 1 "plot_v1" H 2750 4150 60 0000 C CNN
+F 2 "" H 2550 3800 60 0000 C CNN
+F 3 "" H 2550 3800 60 0000 C CNN
+ 1 2550 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5FA67
+P 2750 3900
+F 0 "U?" H 2750 4400 60 0000 C CNN
+F 1 "plot_v1" H 2950 4250 60 0000 C CNN
+F 2 "" H 2750 3900 60 0000 C CNN
+F 3 "" H 2750 3900 60 0000 C CNN
+ 1 2750 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5FAC2
+P 2950 4000
+F 0 "U?" H 2950 4500 60 0000 C CNN
+F 1 "plot_v1" H 3150 4350 60 0000 C CNN
+F 2 "" H 2950 4000 60 0000 C CNN
+F 3 "" H 2950 4000 60 0000 C CNN
+ 1 2950 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A5FB27
+P 3200 4100
+F 0 "U?" H 3200 4600 60 0000 C CNN
+F 1 "plot_v1" H 3400 4450 60 0000 C CNN
+F 2 "" H 3200 4100 60 0000 C CNN
+F 3 "" H 3200 4100 60 0000 C CNN
+ 1 3200 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1800 1350 1800 1450
+Connection ~ 1800 1450
+Wire Wire Line
+ 2100 1600 2100 1800
+Connection ~ 2100 1800
+Wire Wire Line
+ 2300 1900 2300 2150
+Connection ~ 2300 2150
+Wire Wire Line
+ 2550 2200 2550 2500
+Connection ~ 2550 2500
+Wire Wire Line
+ 1900 3300 1900 3350
+Connection ~ 1900 3350
+Wire Wire Line
+ 2150 3400 2150 3450
+Connection ~ 2150 3450
+Wire Wire Line
+ 2350 3500 2350 3550
+Connection ~ 2350 3550
+Wire Wire Line
+ 2550 3600 2550 3650
+Connection ~ 2550 3650
+Wire Wire Line
+ 2750 3700 2750 3750
+Connection ~ 2750 3750
+Wire Wire Line
+ 2950 3800 2950 3850
+Connection ~ 2950 3850
+Wire Wire Line
+ 3200 3900 3200 3950
+Connection ~ 3200 3950
+$Comp
+L plot_v1 U?
+U 1 1 69A60089
+P 1600 3200
+F 0 "U?" H 1600 3700 60 0000 C CNN
+F 1 "plot_v1" H 1800 3550 60 0000 C CNN
+F 2 "" H 1600 3200 60 0000 C CNN
+F 3 "" H 1600 3200 60 0000 C CNN
+ 1 1600 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1600 3000 1750 3000
+Wire Wire Line
+ 1750 3000 1750 3150
+Connection ~ 1750 3150
+$Comp
+L plot_v1 U?
+U 1 1 69A60E49
+P 9600 1650
+F 0 "U?" H 9600 2150 60 0000 C CNN
+F 1 "plot_v1" H 9800 2000 60 0000 C CNN
+F 2 "" H 9600 1650 60 0000 C CNN
+F 3 "" H 9600 1650 60 0000 C CNN
+ 1 9600 1650
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A60F21
+P 9600 1950
+F 0 "U?" H 9600 2450 60 0000 C CNN
+F 1 "plot_v1" H 9800 2300 60 0000 C CNN
+F 2 "" H 9600 1950 60 0000 C CNN
+F 3 "" H 9600 1950 60 0000 C CNN
+ 1 9600 1950
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A60FE2
+P 9600 2250
+F 0 "U?" H 9600 2750 60 0000 C CNN
+F 1 "plot_v1" H 9800 2600 60 0000 C CNN
+F 2 "" H 9600 2250 60 0000 C CNN
+F 3 "" H 9600 2250 60 0000 C CNN
+ 1 9600 2250
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A61055
+P 9600 2500
+F 0 "U?" H 9600 3000 60 0000 C CNN
+F 1 "plot_v1" H 9800 2850 60 0000 C CNN
+F 2 "" H 9600 2500 60 0000 C CNN
+F 3 "" H 9600 2500 60 0000 C CNN
+ 1 9600 2500
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A6114A
+P 9600 2750
+F 0 "U?" H 9600 3250 60 0000 C CNN
+F 1 "plot_v1" H 9800 3100 60 0000 C CNN
+F 2 "" H 9600 2750 60 0000 C CNN
+F 3 "" H 9600 2750 60 0000 C CNN
+ 1 9600 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A61151
+P 9600 3050
+F 0 "U?" H 9600 3550 60 0000 C CNN
+F 1 "plot_v1" H 9800 3400 60 0000 C CNN
+F 2 "" H 9600 3050 60 0000 C CNN
+F 3 "" H 9600 3050 60 0000 C CNN
+ 1 9600 3050
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A61158
+P 9600 3350
+F 0 "U?" H 9600 3850 60 0000 C CNN
+F 1 "plot_v1" H 9800 3700 60 0000 C CNN
+F 2 "" H 9600 3350 60 0000 C CNN
+F 3 "" H 9600 3350 60 0000 C CNN
+ 1 9600 3350
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A6115F
+P 9600 3600
+F 0 "U?" H 9600 4100 60 0000 C CNN
+F 1 "plot_v1" H 9800 3950 60 0000 C CNN
+F 2 "" H 9600 3600 60 0000 C CNN
+F 3 "" H 9600 3600 60 0000 C CNN
+ 1 9600 3600
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A6122E
+P 9650 4300
+F 0 "U?" H 9650 4800 60 0000 C CNN
+F 1 "plot_v1" H 9850 4650 60 0000 C CNN
+F 2 "" H 9650 4300 60 0000 C CNN
+F 3 "" H 9650 4300 60 0000 C CNN
+ 1 9650 4300
+ 0 1 1 0
+$EndComp
+$Comp
+L plot_v1 U?
+U 1 1 69A61235
+P 9650 4550
+F 0 "U?" H 9650 5050 60 0000 C CNN
+F 1 "plot_v1" H 9850 4900 60 0000 C CNN
+F 2 "" H 9650 4550 60 0000 C CNN
+F 3 "" H 9650 4550 60 0000 C CNN
+ 1 9650 4550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 7700 2850 7700 1650
+Wire Wire Line
+ 7700 1650 9800 1650
+Wire Wire Line
+ 7700 2950 7850 2950
+Wire Wire Line
+ 7850 2950 7850 1950
+Wire Wire Line
+ 7850 1950 9800 1950
+Wire Wire Line
+ 7700 3050 7950 3050
+Wire Wire Line
+ 7950 3050 7950 2250
+Wire Wire Line
+ 7950 2250 9800 2250
+Wire Wire Line
+ 7700 3150 8050 3150
+Wire Wire Line
+ 8050 3150 8050 2500
+Wire Wire Line
+ 8050 2500 9800 2500
+Wire Wire Line
+ 7700 3250 8150 3250
+Wire Wire Line
+ 8150 3250 8150 2750
+Wire Wire Line
+ 8150 2750 9800 2750
+Wire Wire Line
+ 7700 3350 8250 3350
+Wire Wire Line
+ 8250 3350 8250 3050
+Wire Wire Line
+ 8250 3050 9800 3050
+Wire Wire Line
+ 7700 3450 8350 3450
+Wire Wire Line
+ 8350 3450 8350 3350
+Wire Wire Line
+ 8350 3350 9800 3350
+Wire Wire Line
+ 7700 3550 9800 3550
+Wire Wire Line
+ 9800 3550 9800 3600
+Wire Wire Line
+ 7700 3900 9850 3900
+Wire Wire Line
+ 9850 3900 9850 4300
+Wire Wire Line
+ 7700 4000 9700 4000
+Wire Wire Line
+ 9700 4000 9700 4550
+Wire Wire Line
+ 9700 4550 9850 4550
+Text GLabel 8800 1650 1 60 Input ~ 0
+q7
+Text GLabel 9250 1950 1 60 Input ~ 0
+q6
+Text GLabel 9300 2250 1 60 Input ~ 0
+q5
+Text GLabel 9200 2500 1 60 Input ~ 0
+q4
+Text GLabel 9250 2750 1 60 Input ~ 0
+q3
+Text GLabel 9250 3050 1 60 Input ~ 0
+q2
+Text GLabel 9300 3350 1 60 Input ~ 0
+q1
+Text GLabel 9450 3550 1 60 Input ~ 0
+q0
+Text GLabel 8750 4000 1 60 Input ~ 0
+empty0
+Text GLabel 9150 3900 1 60 Input ~ 0
+full0
+$EndSCHEMATC
diff --git a/fossee/sync_fifo/sync_fif0/sync_fif0_Previous_Values.xml b/fossee/sync_fifo/sync_fif0/sync_fif0_Previous_Values.xml
new file mode 100644
index 000000000..d92d30f48
--- /dev/null
+++ b/fossee/sync_fifo/sync_fif0/sync_fif0_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01450nsnsnspulse010.01ns0.001ns0.001ns10ns20nspulsepulsepulsepulsepulsepulsepulsepulsepulsepulsepulsesync_fifoadc_bridgeadc_bridgedac_bridgedac_bridge
\ No newline at end of file
diff --git a/fossee/sync_fifo/sync_fif0/sync_fifo.v b/fossee/sync_fifo/sync_fif0/sync_fifo.v
new file mode 100644
index 000000000..6ebcf053a
--- /dev/null
+++ b/fossee/sync_fifo/sync_fif0/sync_fifo.v
@@ -0,0 +1,47 @@
+module sync_fifo (
+ input wire clk,
+ input wire rst,
+ input wire wr_en,
+ input wire rd_en,
+ input wire [7:0] din,
+ output reg [7:0] dout,
+ output wire full,
+ output wire empty
+);
+
+ parameter DEPTH = 8;
+ parameter ADDR = 3; // log2(8)
+
+ reg [7:0] mem [0:DEPTH-1];
+
+ reg [ADDR:0] wptr;
+ reg [ADDR:0] rptr;
+
+ // WRITE
+ always @(posedge clk or posedge rst) begin
+ if (rst)
+ wptr <= 0;
+ else if (wr_en && !full) begin
+ mem[wptr[ADDR-1:0]] <= din;
+ wptr <= wptr + 1;
+ end
+ end
+
+ // READ
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ rptr <= 0;
+ dout <= 0;
+ end
+ else if (rd_en && !empty) begin
+ dout <= mem[rptr[ADDR-1:0]];
+ rptr <= rptr + 1;
+ end
+ end
+
+ assign empty = (wptr == rptr);
+
+ assign full = (wptr[ADDR-1:0] == rptr[ADDR-1:0]) &&
+ (wptr[ADDR] != rptr[ADDR]);
+
+endmodule
\ No newline at end of file
diff --git a/fossee/sync_fifo/sync_fif0/sync_fifo.v.txt b/fossee/sync_fifo/sync_fif0/sync_fifo.v.txt
new file mode 100644
index 000000000..e69de29bb
diff --git a/fossee/sync_fifo/sync_fifo.v b/fossee/sync_fifo/sync_fifo.v
new file mode 100644
index 000000000..a00f5fb70
--- /dev/null
+++ b/fossee/sync_fifo/sync_fifo.v
@@ -0,0 +1,69 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 02.03.2026 21:11:15
+// Design Name:
+// Module Name: sync_fifo
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module sync_fifo (
+ input wire clk,
+ input wire rst,
+ input wire wr_en,
+ input wire rd_en,
+ input wire [7:0] din,
+ output reg [7:0] dout,
+ output wire full,
+ output wire empty
+);
+
+ parameter DEPTH = 8;
+ parameter ADDR = 3; // log2(8)
+
+ reg [7:0] mem [0:DEPTH-1];
+
+ reg [ADDR:0] wptr;
+ reg [ADDR:0] rptr;
+
+ // WRITE
+ always @(posedge clk or posedge rst) begin
+ if (rst)
+ wptr <= 0;
+ else if (wr_en && !full) begin
+ mem[wptr[ADDR-1:0]] <= din;
+ wptr <= wptr + 1;
+ end
+ end
+
+ // READ
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ rptr <= 0;
+ dout <= 0;
+ end
+ else if (rd_en && !empty) begin
+ dout <= mem[rptr[ADDR-1:0]];
+ rptr <= rptr + 1;
+ end
+ end
+
+ assign empty = (wptr == rptr);
+
+ assign full = (wptr[ADDR-1:0] == rptr[ADDR-1:0]) &&
+ (wptr[ADDR] != rptr[ADDR]);
+
+endmodule
\ No newline at end of file
diff --git a/fossee/sync_fifo/sync_fifo_block_diagram.png b/fossee/sync_fifo/sync_fifo_block_diagram.png
new file mode 100644
index 000000000..526b87374
Binary files /dev/null and b/fossee/sync_fifo/sync_fifo_block_diagram.png differ
diff --git a/fossee/sync_fifo/sync_fifo_module.png b/fossee/sync_fifo/sync_fifo_module.png
new file mode 100644
index 000000000..b05d0f243
Binary files /dev/null and b/fossee/sync_fifo/sync_fifo_module.png differ
diff --git a/fossee/sync_fifo/sync_fifo_schematic.png b/fossee/sync_fifo/sync_fifo_schematic.png
new file mode 100644
index 000000000..735ca1b2a
Binary files /dev/null and b/fossee/sync_fifo/sync_fifo_schematic.png differ
diff --git a/fossee/sync_fifo/sync_fifo_waves.png b/fossee/sync_fifo/sync_fifo_waves.png
new file mode 100644
index 000000000..0dbbc545b
Binary files /dev/null and b/fossee/sync_fifo/sync_fifo_waves.png differ
diff --git a/fossee/sync_fifo/tb.v b/fossee/sync_fifo/tb.v
new file mode 100644
index 000000000..cdc57ae3a
--- /dev/null
+++ b/fossee/sync_fifo/tb.v
@@ -0,0 +1,86 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 02.03.2026 21:11:33
+// Design Name:
+// Module Name: tb
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module sync_fifo_tb;
+
+ reg clk;
+ reg rst;
+ reg wr_en;
+ reg rd_en;
+ reg [7:0] din;
+
+ wire [7:0] dout;
+ wire full;
+ wire empty;
+
+ // DUT
+ sync_fifo uut (
+ .clk(clk),
+ .rst(rst),
+ .wr_en(wr_en),
+ .rd_en(rd_en),
+ .din(din),
+ .dout(dout),
+ .full(full),
+ .empty(empty)
+ );
+
+ // clock
+ always begin
+ clk = 0; #5;
+ clk = 1; #5;
+ end
+
+ integer i;
+
+ initial begin
+ rst = 1;
+ wr_en = 0;
+ rd_en = 0;
+ din = 0;
+
+ #20;
+ rst = 0;
+
+ // WRITE 8 values
+ for (i=0; i<8; i=i+1) begin
+ @(posedge clk);
+ wr_en = 1;
+ din = i;
+ end
+
+ @(posedge clk);
+ wr_en = 0;
+
+ // READ 8 values
+ for (i=0; i<8; i=i+1) begin
+ @(posedge clk);
+ rd_en = 1;
+ end
+
+ @(posedge clk);
+ rd_en = 0;
+
+ #50;
+ $finish;
+ end
+
+endmodule
\ No newline at end of file