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author
Matthias Koefferlein
committed
Updating test data
1 parent 4af2662 commit f127ec9

2 files changed

Lines changed: 70 additions & 70 deletions

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‎testdata/python/dbLayoutToNetlist.py‎

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -105,15 +105,15 @@ def test_2_ShapesFromNet(self):
105105
end;
106106
circuit RINGO ();
107107
subcircuit INV2 $1 (OUT='FB,OSC',$2=VSS,$3=VDD);
108-
subcircuit INV2 $2 (OUT=$I20,$2=VSS,$3=VDD);
109-
subcircuit INV2 $3 (OUT=$I19,$2=VSS,$3=VDD);
110-
subcircuit INV2 $4 (OUT=$I21,$2=VSS,$3=VDD);
111-
subcircuit INV2 $5 (OUT=$I22,$2=VSS,$3=VDD);
108+
subcircuit INV2 $2 (OUT=$I27,$2=VSS,$3=VDD);
109+
subcircuit INV2 $3 (OUT=$I26,$2=VSS,$3=VDD);
110+
subcircuit INV2 $4 (OUT=$I25,$2=VSS,$3=VDD);
111+
subcircuit INV2 $5 (OUT=$I24,$2=VSS,$3=VDD);
112112
subcircuit INV2 $6 (OUT=$I23,$2=VSS,$3=VDD);
113-
subcircuit INV2 $7 (OUT=$I24,$2=VSS,$3=VDD);
114-
subcircuit INV2 $8 (OUT=$I25,$2=VSS,$3=VDD);
115-
subcircuit INV2 $9 (OUT=$I26,$2=VSS,$3=VDD);
116-
subcircuit INV2 $10 (OUT=$I27,$2=VSS,$3=VDD);
113+
subcircuit INV2 $7 (OUT=$I22,$2=VSS,$3=VDD);
114+
subcircuit INV2 $8 (OUT=$I21,$2=VSS,$3=VDD);
115+
subcircuit INV2 $9 (OUT=$I20,$2=VSS,$3=VDD);
116+
subcircuit INV2 $10 (OUT=$I19,$2=VSS,$3=VDD);
117117
end;
118118
""")
119119

@@ -134,7 +134,7 @@ def test_2_ShapesFromNet(self):
134134
for sc in sc_path:
135135
a.append(sc.expanded_name())
136136
t = t * sc.trans
137-
self.assertEqual(",".join(a), "$2")
137+
self.assertEqual(",".join(a), "$9")
138138
self.assertEqual(str(t), "r0 *1 2.64,0")
139139

140140
self.assertEqual(str(l2n.shapes_of_net(n, rmetal1, True)),
@@ -206,16 +206,16 @@ def test_10_LayoutToNetlistExtractionWithoutDevices(self):
206206
subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);
207207
end;
208208
circuit RINGO ();
209-
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
209+
subcircuit INV2 $1 (IN=$I18,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
210210
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
211-
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
212-
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
213-
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
214-
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
215-
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
216-
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
217-
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
218-
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
211+
subcircuit INV2 $3 (IN=$I17,$2=$I46,OUT=$I18,$4=VSS,$5=VDD);
212+
subcircuit INV2 $4 (IN=$I16,$2=$I45,OUT=$I17,$4=VSS,$5=VDD);
213+
subcircuit INV2 $5 (IN=$I15,$2=$I44,OUT=$I16,$4=VSS,$5=VDD);
214+
subcircuit INV2 $6 (IN=$I14,$2=$I43,OUT=$I15,$4=VSS,$5=VDD);
215+
subcircuit INV2 $7 (IN=$I13,$2=$I42,OUT=$I14,$4=VSS,$5=VDD);
216+
subcircuit INV2 $8 (IN=$I12,$2=$I41,OUT=$I13,$4=VSS,$5=VDD);
217+
subcircuit INV2 $9 (IN=$I11,$2=$I40,OUT=$I12,$4=VSS,$5=VDD);
218+
subcircuit INV2 $10 (IN=$I19,$2=$I39,OUT=$I11,$4=VSS,$5=VDD);
219219
end;
220220
""")
221221

@@ -287,16 +287,16 @@ def test_11_LayoutToNetlistExtractionWithDevices(self):
287287
l2n.extract_netlist()
288288

289289
self.assertEqual(str(l2n.netlist()), """circuit RINGO ();
290-
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
290+
subcircuit INV2 $1 (IN=$I18,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
291291
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
292-
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
293-
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
294-
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
295-
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
296-
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
297-
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
298-
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
299-
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
292+
subcircuit INV2 $3 (IN=$I17,$2=$I46,OUT=$I18,$4=VSS,$5=VDD);
293+
subcircuit INV2 $4 (IN=$I16,$2=$I45,OUT=$I17,$4=VSS,$5=VDD);
294+
subcircuit INV2 $5 (IN=$I15,$2=$I44,OUT=$I16,$4=VSS,$5=VDD);
295+
subcircuit INV2 $6 (IN=$I14,$2=$I43,OUT=$I15,$4=VSS,$5=VDD);
296+
subcircuit INV2 $7 (IN=$I13,$2=$I42,OUT=$I14,$4=VSS,$5=VDD);
297+
subcircuit INV2 $8 (IN=$I12,$2=$I41,OUT=$I13,$4=VSS,$5=VDD);
298+
subcircuit INV2 $9 (IN=$I11,$2=$I40,OUT=$I12,$4=VSS,$5=VDD);
299+
subcircuit INV2 $10 (IN=$I19,$2=$I39,OUT=$I11,$4=VSS,$5=VDD);
300300
end;
301301
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
302302
device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
@@ -402,11 +402,11 @@ def test_12_LayoutToNetlistExtractionWithDevicesAndGlobalNets(self):
402402
l2n.extract_netlist()
403403

404404
self.assertEqual(str(l2n.netlist()), """circuit RINGO ();
405-
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
405+
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I16,$6=OSC,$7=VDD);
406406
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
407-
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
408-
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
409-
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
407+
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I15,$6=$I16,$7=VDD);
408+
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I14,$6=$I15,$7=VDD);
409+
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I14,$7=VDD);
410410
end;
411411
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
412412
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
@@ -431,11 +431,11 @@ def test_12_LayoutToNetlistExtractionWithDevicesAndGlobalNets(self):
431431
l2n.netlist().purge()
432432

433433
self.assertEqual(str(l2n.netlist()), """circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
434-
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
434+
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I16,$6=OSC,$7=VDD);
435435
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
436-
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
437-
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
438-
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
436+
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I15,$6=$I16,$7=VDD);
437+
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I14,$6=$I15,$7=VDD);
438+
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I14,$7=VDD);
439439
end;
440440
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
441441
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);

‎testdata/ruby/dbLayoutToNetlist.rb‎

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -182,15 +182,15 @@ def test_2_ShapesFromNet
182182
end;
183183
circuit RINGO ();
184184
subcircuit INV2 $1 (OUT='FB,OSC',$2=VSS,$3=VDD);
185-
subcircuit INV2 $2 (OUT=$I20,$2=VSS,$3=VDD);
186-
subcircuit INV2 $3 (OUT=$I19,$2=VSS,$3=VDD);
187-
subcircuit INV2 $4 (OUT=$I21,$2=VSS,$3=VDD);
188-
subcircuit INV2 $5 (OUT=$I22,$2=VSS,$3=VDD);
185+
subcircuit INV2 $2 (OUT=$I27,$2=VSS,$3=VDD);
186+
subcircuit INV2 $3 (OUT=$I26,$2=VSS,$3=VDD);
187+
subcircuit INV2 $4 (OUT=$I25,$2=VSS,$3=VDD);
188+
subcircuit INV2 $5 (OUT=$I24,$2=VSS,$3=VDD);
189189
subcircuit INV2 $6 (OUT=$I23,$2=VSS,$3=VDD);
190-
subcircuit INV2 $7 (OUT=$I24,$2=VSS,$3=VDD);
191-
subcircuit INV2 $8 (OUT=$I25,$2=VSS,$3=VDD);
192-
subcircuit INV2 $9 (OUT=$I26,$2=VSS,$3=VDD);
193-
subcircuit INV2 $10 (OUT=$I27,$2=VSS,$3=VDD);
190+
subcircuit INV2 $7 (OUT=$I22,$2=VSS,$3=VDD);
191+
subcircuit INV2 $8 (OUT=$I21,$2=VSS,$3=VDD);
192+
subcircuit INV2 $9 (OUT=$I20,$2=VSS,$3=VDD);
193+
subcircuit INV2 $10 (OUT=$I19,$2=VSS,$3=VDD);
194194
end;
195195
END
196196

@@ -206,7 +206,7 @@ def test_2_ShapesFromNet
206206
n = l2n.probe_net(rmetal1, RBA::Point::new(2600, 1000), sc_path)
207207
assert_equal(n.to_s, "INV2:$2")
208208
assert_equal(sc_path.size, 1)
209-
assert_equal(sc_path.collect(&:expanded_name).join(","), "$2")
209+
assert_equal(sc_path.collect(&:expanded_name).join(","), "$9")
210210
assert_equal(sc_path.collect(&:trans).inject(&:*).to_s, "r0 *1 2.64,0")
211211

212212
assert_equal(l2n.shapes_of_net(n, rmetal1, true).to_s,
@@ -287,16 +287,16 @@ def test_10_LayoutToNetlistExtractionWithoutDevices
287287
subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);
288288
end;
289289
circuit RINGO ();
290-
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
290+
subcircuit INV2 $1 (IN=$I18,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
291291
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
292-
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
293-
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
294-
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
295-
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
296-
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
297-
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
298-
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
299-
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
292+
subcircuit INV2 $3 (IN=$I17,$2=$I46,OUT=$I18,$4=VSS,$5=VDD);
293+
subcircuit INV2 $4 (IN=$I16,$2=$I45,OUT=$I17,$4=VSS,$5=VDD);
294+
subcircuit INV2 $5 (IN=$I15,$2=$I44,OUT=$I16,$4=VSS,$5=VDD);
295+
subcircuit INV2 $6 (IN=$I14,$2=$I43,OUT=$I15,$4=VSS,$5=VDD);
296+
subcircuit INV2 $7 (IN=$I13,$2=$I42,OUT=$I14,$4=VSS,$5=VDD);
297+
subcircuit INV2 $8 (IN=$I12,$2=$I41,OUT=$I13,$4=VSS,$5=VDD);
298+
subcircuit INV2 $9 (IN=$I11,$2=$I40,OUT=$I12,$4=VSS,$5=VDD);
299+
subcircuit INV2 $10 (IN=$I19,$2=$I39,OUT=$I11,$4=VSS,$5=VDD);
300300
end;
301301
END
302302

@@ -369,16 +369,16 @@ def test_11_LayoutToNetlistExtractionWithDevices
369369

370370
assert_equal(l2n.netlist.to_s, <<END)
371371
circuit RINGO ();
372-
subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
372+
subcircuit INV2 $1 (IN=$I18,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
373373
subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
374-
subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
375-
subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
376-
subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
377-
subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
378-
subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
379-
subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
380-
subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
381-
subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
374+
subcircuit INV2 $3 (IN=$I17,$2=$I46,OUT=$I18,$4=VSS,$5=VDD);
375+
subcircuit INV2 $4 (IN=$I16,$2=$I45,OUT=$I17,$4=VSS,$5=VDD);
376+
subcircuit INV2 $5 (IN=$I15,$2=$I44,OUT=$I16,$4=VSS,$5=VDD);
377+
subcircuit INV2 $6 (IN=$I14,$2=$I43,OUT=$I15,$4=VSS,$5=VDD);
378+
subcircuit INV2 $7 (IN=$I13,$2=$I42,OUT=$I14,$4=VSS,$5=VDD);
379+
subcircuit INV2 $8 (IN=$I12,$2=$I41,OUT=$I13,$4=VSS,$5=VDD);
380+
subcircuit INV2 $9 (IN=$I11,$2=$I40,OUT=$I12,$4=VSS,$5=VDD);
381+
subcircuit INV2 $10 (IN=$I19,$2=$I39,OUT=$I11,$4=VSS,$5=VDD);
382382
end;
383383
circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
384384
device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
@@ -485,11 +485,11 @@ def test_12_LayoutToNetlistExtractionWithDevicesAndGlobalNets
485485

486486
assert_equal(l2n.netlist.to_s, <<END)
487487
circuit RINGO ();
488-
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
488+
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I16,$6=OSC,$7=VDD);
489489
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
490-
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
491-
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
492-
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
490+
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I15,$6=$I16,$7=VDD);
491+
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I14,$6=$I15,$7=VDD);
492+
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I14,$7=VDD);
493493
end;
494494
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
495495
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
@@ -515,11 +515,11 @@ def test_12_LayoutToNetlistExtractionWithDevicesAndGlobalNets
515515

516516
assert_equal(l2n.netlist.to_s, <<END)
517517
circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
518-
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
518+
subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I16,$6=OSC,$7=VDD);
519519
subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
520-
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
521-
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
522-
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
520+
subcircuit INV2PAIR $3 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I15,$6=$I16,$7=VDD);
521+
subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I14,$6=$I15,$7=VDD);
522+
subcircuit INV2PAIR $5 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I14,$7=VDD);
523523
end;
524524
circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
525525
subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);

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