Importing a circuit into our system is fast but not free; with the increased scaling potential of the rest of the system, we start facing slowdowns caused by this loading pipeline.
The system works with Verilog (.v) files and GraphViz (.gv, .dot) files during the loading pipeline, starting from a Verilog containing the circuit description (as Boolean or integer expressions), then elaborating it as a GraphViz, ending in the loaded circuit as a graph.
Each of these steps has the potential for improvements, and the pipeline can be restructured as a whole by interfacing new libraries (aigverse) with our system; in this project we aim to deliver a more responsive and scalable loading pipeline.
An expansion on this work is the architectural improvement of the circuit module in the system; the plan is to use an architectural pattern similar to the Entity Component System pattern (mainly used in video games), that would give us better modularity and expandability of the circuit module.
Importing a circuit into our system is fast but not free; with the increased scaling potential of the rest of the system, we start facing slowdowns caused by this loading pipeline.
The system works with Verilog (.v) files and GraphViz (.gv, .dot) files during the loading pipeline, starting from a Verilog containing the circuit description (as Boolean or integer expressions), then elaborating it as a GraphViz, ending in the loaded circuit as a graph.
Each of these steps has the potential for improvements, and the pipeline can be restructured as a whole by interfacing new libraries (aigverse) with our system; in this project we aim to deliver a more responsive and scalable loading pipeline.
An expansion on this work is the architectural improvement of the circuit module in the system; the plan is to use an architectural pattern similar to the Entity Component System pattern (mainly used in video games), that would give us better modularity and expandability of the circuit module.