Add Oneshot module

Author: pcw-mesa

docs/man/man9/hostmot2.9

@@ -114,6 +114,7 @@ The valid entries in the format string are:
  [num_resolvers=\fIN\fB]
  [num_pwmgens=\fIN\fB]
  [num_3pwmgens=\fIN\fB]
+ [num_oneshots=\fIN\fB]
  [num_rcpwmgens=\fIN\fB]
  [num_stepgens=\fIN\fB]
  [stepgen_width=\fIN\fB]
@@ -967,6 +968,94 @@ that affects all instances:
 Sets the master PWM frequency. Maximum is approx 48 kHz, minimum
 is 1 kHz. Defaults to 20 kHz.
 
+.SS oneshot
+The oneshot is a hardware one-shot device suitable for various timing, delay, 
+signal conditioning and watchdog functions. The oneshot module includes 2 timers
+to allow variable pulse delays for applications like phase control.
+Trigger sources can be software, external inputs, the DPLL timer, a built in 
+rate generator or the other timer.
+Oneshots have names like "hm2_\fI<BoardType>\fR.\fI<BoardNum>\fR.oneshot.\fI<Instance>\fR"
+where <Instance> is a 2-digit number. There will be num_oneshots instances,
+starting at 00. Each instance allocates up to two input and two output pins.
+
+Pins:
+
+.TP
+(float rw) width1
+Sets the pulse width of timer1 in ms. Default is 1 ms (1/1000 s).
+
+.TP
+(float rw) width2 
+Sets the pulse width of timer2 in ms. Default is 1 ms (1/1000 s).
+
+.TP
+(float rw) filter1
+Sets digital filter time constant for timer1's external trigger input
+Filter time is in ms. Default filter time constant time is 0.1 ms.
+External trigger response will be delayed by the filter time setting
+
+.TP
+(float rw) filter2
+Sets digital filter time constant for timer1's external trigger input
+Filter time is in ms. Default filter time constant time is 0.1 ms.
+External trigger response will be delayed by the filter time setting
+
+.TP
+(float rw) rate
+Sets the frequency of the built in rate generator (in Hz)
+
+.TP
+(u32 rw) trigger_select1,trigger_select2 
+Sets the trigger source for timer1,timer2 respectively.
+Trigger sources are:
+.nf
+0 Trigger disabled
+1 Software trigger: triggered when hal pin swtrigger1 is true
+2 External hardware: trigger
+3 DPLL trigger: triggered by selected DPLL timer
+4 Rate trigger: triggered by build in rate generator.
+5 Timer1 trigger: triggered by timer1 output
+6 Timer2 trigger: triggered by timer2 output
+
+.TP
+(bit rw) trigger_on_rise1,trigger_on_rise2
+When true,trigger timer1,timer2 respectively on the
+rising edge of the trigger source.
+
+.TP
+(bit rw) trigger_on_fall1,trigger_on_fall2
+When true, trigger timer1,timer2 respectively on the
+falling edge of the trigger source.
+
+.TP
+(bit rw) retriggerable1,retriggerable2
+When true, the associated timer is retriggerable, meaning
+the timer will reset to full time on a trigger event
+even durin the output pulse period.
+When false the timer is not retriggerable, meaning
+it will ignore trigger events during the output 
+pulse period.
+ 
+.TP
+(bit rw) enable1,enable2
+trigger enable for timer1 and timer2 respectively
+True to enable.
+
+.TP
+(bit rw) reset1,reset2
+If true, resets timer1,timer2 respectively,
+aborting any pulse in progress.
+
+.TP
+(bit ro) out1,out2
+Pulse output status bit for timer 1,timer2
+
+.TP
+(bit ro) exttrigger1,exttrigger2
+External trigger input status bits for timer 1,timer2.
+These monitor the filtered inputs.
+
+
 .SS rcpwmgen
 The rcpwmgen is a simple PWM generator optimized for use with standard RC servos
 that use pulse width to determine position.
@@ -999,7 +1088,6 @@ Sets the per channel pulse width scaling, for example, setting the scale to 90
 and the offset to 1.5 mS would result in a position range of +-45 degrees
 scale in degrees for 1-2 mS servos with a full motion range of 90 degrees
 
-
 .SS stepgen
 
 stepgens have names like

src/Makefile

@@ -1009,6 +1009,7 @@ hostmot2-objs :=			  \
     hal/drivers/mesa-hostmot2/pins.o	  \
     hal/drivers/mesa-hostmot2/pktuart.o   \
     hal/drivers/mesa-hostmot2/pwmgen.o	  \
+    hal/drivers/mesa-hostmot2/oneshot.o	  \
     hal/drivers/mesa-hostmot2/raw.o	  \
     hal/drivers/mesa-hostmot2/rcpwmgen.o  \
     hal/drivers/mesa-hostmot2/resolver.o  \

src/hal/drivers/mesa-hostmot2/hostmot2.c

@@ -114,6 +114,7 @@ static void hm2_read(void *void_hm2, long period) {
     hm2_sserial_process_tram_read(hm2, period);
     hm2_bspi_process_tram_read(hm2, period);
     hm2_absenc_process_tram_read(hm2, period);
+    hm2_oneshot_process_tram_read(hm2);
     //UARTS PktUARTS need to be explicitly handled by an external component
 
     hm2_tp_pwmgen_process_read(hm2); // check the status of the fault bit
@@ -135,6 +136,7 @@ static void hm2_write(void *void_hm2, long period) {
     hm2_watchdog_prepare_tram_write(hm2);
     hm2_ioport_gpio_prepare_tram_write(hm2);
     hm2_pwmgen_prepare_tram_write(hm2);
+    hm2_oneshot_prepare_tram_write(hm2);
     hm2_rcpwmgen_prepare_tram_write(hm2);
     hm2_inmux_prepare_tram_write(hm2);
     hm2_inm_prepare_tram_write(hm2);
@@ -152,6 +154,7 @@ static void hm2_write(void *void_hm2, long period) {
     hm2_ioport_write(hm2);    // handles gpio.is_output but not gpio.out (that's done in tram_write() above)
     hm2_watchdog_write(hm2, period);  // in case the user has written to the watchdog.timeout_ns param
     hm2_pwmgen_write(hm2);    // update pwmgen registers if needed
+    hm2_oneshot_write(hm2);   // update oneshot registers if needed
     hm2_rcpwmgen_write(hm2);  // update rcpwmgen registers if needed
     hm2_inmux_write(hm2);     // update inmux control register if needed
     hm2_inm_write(hm2);       // update inm control register if needed
@@ -317,6 +320,8 @@ const char *hm2_get_general_function_name(int gtag) {
         case HM2_GTAG_XY2MOD:          return "xy2mod Galvo interface";
         case HM2_GTAG_DPAINTER:        return "Data Painter";
         case HM2_GTAG_SSR:             return "SSR";
+        case HM2_GTAG_ONESHOT:         return "OneShot";
+
         default: {
             static char unknown[100];
             rtapi_snprintf(unknown, 100, "(unknown-gtag-%d)", gtag);
@@ -394,6 +399,7 @@ static int hm2_parse_config_string(hostmot2_t *hm2, char *config_string) {
     hm2->config.num_leds = -1;
     hm2->config.num_ssrs = -1;
     hm2->config.num_outms = -1;
+    hm2->config.num_oneshots = -1;
     hm2->config.enable_raw = 0;
     hm2->config.firmware = NULL;
 
@@ -452,6 +458,10 @@ static int hm2_parse_config_string(hostmot2_t *hm2, char *config_string) {
             token += 10;
             hm2->config.num_outms = simple_strtol(token, NULL, 0);
 
+        } else if (strncmp(token, "num_oneshots=", 13) == 0) {
+            token += 10;
+            hm2->config.num_oneshots = simple_strtol(token, NULL, 0);
+
         } else if (strncmp(token, "num_ssrs=", 9) == 0) {
             token += 9;
             hm2->config.num_ssrs = simple_strtol(token, NULL, 0);
@@ -547,6 +557,7 @@ static int hm2_parse_config_string(hostmot2_t *hm2, char *config_string) {
     HM2_DBG("    num_inmuxs=%d\n",  hm2->config.num_inmuxs);
     HM2_DBG("    num_inms=%d\n",  hm2->config.num_inms);
     HM2_DBG("    num_outms=%d\n",  hm2->config.num_outms);
+    HM2_DBG("    num_oneshots=%d\n",  hm2->config.num_oneshots);
     HM2_DBG("    num_ssrs=%d\n",  hm2->config.num_ssrs);
     HM2_DBG("    num_xy2mods=%d\n",  hm2->config.num_xy2mods);
     HM2_DBG("    num_3pwmgens=%d\n", hm2->config.num_tp_pwmgens);
@@ -1046,6 +1057,10 @@ static int hm2_parse_module_descriptors(hostmot2_t *hm2) {
             case HM2_GTAG_OUTM:
                 md_accepted = hm2_outm_parse_md(hm2, md_index);
                 break;
+
+            case HM2_GTAG_ONESHOT:
+                md_accepted = hm2_oneshot_parse_md(hm2, md_index);
+                break;
 
           case HM2_GTAG_RCPWMGEN:
                 md_accepted = hm2_rcpwmgen_parse_md(hm2, md_index);
@@ -1124,6 +1139,7 @@ static void hm2_cleanup(hostmot2_t *hm2) {
     hm2_bspi_cleanup(hm2);
     hm2_ssr_cleanup(hm2);
     hm2_outm_cleanup(hm2);
+    hm2_oneshot_cleanup(hm2);
     hm2_rcpwmgen_cleanup(hm2);
 
     // free all the tram entries
@@ -1145,6 +1161,7 @@ void hm2_print_modules(hostmot2_t *hm2) {
     hm2_ioport_print_module(hm2);
     hm2_ssr_print_module(hm2);
     hm2_outm_print_module(hm2);
+    hm2_oneshot_print_module(hm2);
     hm2_watchdog_print_module(hm2);
     hm2_inmux_print_module(hm2);
     hm2_inm_print_module(hm2);
@@ -1806,6 +1823,7 @@ void hm2_force_write(hostmot2_t *hm2) {
     hm2_inmux_force_write(hm2);
     hm2_inm_force_write(hm2);
     hm2_xy2mod_force_write(hm2);
+    hm2_oneshot_force_write(hm2);
 
     // NOTE: It's important that the SSR is written *after* the
     // ioport is written.  Initialization of the SSR requires that

src/hal/drivers/mesa-hostmot2/hostmot2.h

@@ -132,6 +132,7 @@
 #define HM2_GTAG_TWIDDLER          (194) // Not supported
 #define HM2_GTAG_SSR               (195)
 #define HM2_GTAG_SMARTSERIALB      (198) // smart-serial with 224 data bits
+#define HM2_GTAG_ONESHOT           (199) // One shot
 
 
 //
@@ -575,6 +576,79 @@ typedef struct {
     rtapi_u32 enable_reg;  // one register for the whole Function
 } hm2_pwmgen_t;
 
+//
+// oneshot
+// 
+
+
+typedef struct {
+
+    struct {
+
+        struct {
+            hal_float_t *width1;
+            hal_float_t *width2; 
+            hal_float_t *filter1;
+            hal_float_t *filter2;
+            hal_float_t *rate;
+            hal_u32_t *trigselect1;
+            hal_u32_t *trigselect2;
+            hal_bit_t *trigrise1;
+            hal_bit_t *trigrise2;
+            hal_bit_t *trigfall1;
+            hal_bit_t *trigfall2;
+            hal_bit_t *retrig1;
+            hal_bit_t *retrig2;
+            hal_bit_t *enable1;
+            hal_bit_t *enable2;
+            hal_bit_t *reset1;
+            hal_bit_t *reset2;
+            hal_bit_t *swtrig1;
+            hal_bit_t *swtrig2;
+            hal_bit_t *exttrig1;
+            hal_bit_t *exttrig2;
+            hal_bit_t *out1;
+            hal_bit_t *out2;
+            
+            hal_s32_t *dpll_timer_num;
+        } pin;
+
+    } hal;
+
+} hm2_oneshot_instance_t;
+
+
+
+typedef struct {
+    int num_instances;
+    hm2_oneshot_instance_t *instance;
+
+    rtapi_u32 clock_frequency;
+    rtapi_u8 version;
+
+    rtapi_u32 width1_addr;
+    rtapi_u32 *width1_reg;
+
+    rtapi_u32 width2_addr;
+    rtapi_u32 *width2_reg;
+
+    rtapi_u32 filter1_addr;
+    rtapi_u32 *filter1_reg;
+
+    rtapi_u32 filter2_addr;
+    rtapi_u32 *filter2_reg;
+
+    rtapi_u32 rate_addr;
+    rtapi_u32 *rate_reg;
+
+    rtapi_u32 control_addr;
+    rtapi_u32 *control_reg;
+
+    rtapi_u32 control_read_addr;
+    rtapi_u32 *control_read_reg;
+
+} hm2_oneshot_t;
+
 //
 // rcpwmgen pwmgen optimized for RC servos
 // 
@@ -1489,6 +1563,7 @@ typedef struct {
         int num_xy2mods;
         int num_ssrs;
         int num_outms;
+        int num_oneshots;
         char sserial_modes[4][8];
         int enable_raw;
         char *firmware;
@@ -1538,6 +1613,7 @@ typedef struct {
     hm2_led_t led;
     hm2_ssr_t ssr;
     hm2_outm_t outm;
+    hm2_oneshot_t oneshot;
 
     hm2_raw_t *raw;
 
@@ -1686,6 +1762,18 @@ void hm2_pwmgen_write(hostmot2_t *hm2);
 void hm2_pwmgen_force_write(hostmot2_t *hm2);
 void hm2_pwmgen_prepare_tram_write(hostmot2_t *hm2);
 
+//
+// oneshot functions
+//
+
+int hm2_oneshot_parse_md(hostmot2_t *hm2, int md_index);
+void hm2_oneshot_print_module(hostmot2_t *hm2);
+void hm2_oneshot_cleanup(hostmot2_t *hm2);
+void hm2_oneshot_write(hostmot2_t *hm2);
+void hm2_oneshot_force_write(hostmot2_t *hm2);
+void hm2_oneshot_prepare_tram_write(hostmot2_t *hm2);
+void hm2_oneshot_process_tram_read(hostmot2_t *hm2);
+
 //
 // rcpwmgen functions
 //
@@ -1891,6 +1979,16 @@ void hm2_outm_force_write(hostmot2_t *hm2);
 void hm2_outm_prepare_tram_write(hostmot2_t *hm2);
 void hm2_outm_print_module(hostmot2_t *hm2);
 
+//
+// ONESHOT functions
+//
+
+int hm2_oneshot_parse_md(hostmot2_t *hm2, int md_index);
+void hm2_oneshot_cleanup(hostmot2_t *hm2);
+void hm2_oneshot_force_write(hostmot2_t *hm2);
+void hm2_oneshot_prepare_tram_write(hostmot2_t *hm2);
+void hm2_oneshot_print_module(hostmot2_t *hm2);
+
 
 //
 // the raw interface lets you peek and poke the hostmot2 instance from HAL