Updated documentation

Author: LucAce

doc/Device Registers.md

@@ -121,7 +121,7 @@ Notes:
 Bits       | Type       | Reset      | Description
 ---------- | ---------- | ---------- | -----------
 7:3        | RO         | 5'h00      | Reserved
-2:0        | RW         | 3'h3       | FIFO Almost Empty Register Value bits 10-8
+2:0        | RW         | 3'h0       | FIFO Almost Empty Register Value bits 10-8
 
 ```
 Notes:
@@ -134,7 +134,7 @@ Notes:
 
 Bits       | Type       | Reset      | Description
 ---------- | ---------- | ---------- | -----------
-7:0        | RW         | 8'h99      | FIFO Almost Empty Register Value bits 7-0
+7:0        | RW         | 8'h67      | FIFO Almost Empty Register Value bits 7-0
 
 ```
 Notes:
@@ -147,29 +147,29 @@ Notes:
 
 Bits       | Type       | Reset      | Description
 ---------- | ---------- | ---------- | -----------
-7:0        | RW         | 8'h10      | Number of clock cycles a WS2812 “Zero” value will be driven high (1)
+7:0        | RW         | 8'h10      | Number of clock cycles a WS2812B “Zero” value will be driven high (1)
 
 
 ## Offset: 0x08 - Zero Low Timing Register
 
 Bits       | Type       | Reset      | Description
 ---------- | ---------- | ---------- | -----------
-7:0        | RW         | 8'h24      | Number of clock cycles a WS2812 “Zero” value will be driven low (0)
+7:0        | RW         | 8'h24      | Number of clock cycles a WS2812B “Zero” value will be driven low (0)
 
 
 
 ## Offset: 0x09 - One High Timing Register
 
 Bits       | Type       | Reset      | Description
 ---------- | ---------- | ---------- | -----------
-7:0        | RW         | 8'h24      | Number of clock cycles a WS2812 “One” value will be driven high (1)
+7:0        | RW         | 8'h20      | Number of clock cycles a WS2812B “One” value will be driven high (1)
 
 
 ## Offset: 0x0A - One Low Timing Register
 
 Bits       | Type       | Reset      | Description
 ---------- | ---------- | ---------- | -----------
-7:0        | RW         | 8'h20      | Number of clock cycles a WS2812 “One” value will be driven low (0)
+7:0        | RW         | 8'h1B      | Number of clock cycles a WS2812B “One” value will be driven low (0)
 
 
 ## Offset: 0x0B - Reset Cycle Timing Register
@@ -189,7 +189,7 @@ Notes:
 
 Bits       | Type       | Reset      | Description
 ---------- | ---------- | ---------- | -----------
-7:0        | RW         | 8'h18      | Number ofclock cycles time 128 a Reset Code will be driven.  Reset Code is driven between LED updates to signal the end of the shifting.
+7:0        | RW         | 8'h31      | Number of clock cycles times 256 a Reset Code will be driven.  Reset Code is driven between LED updates to signal the end of the shifting.
 
 
 ## Offset: 0x0D - Run Register

doc/Register Worksheet WS2812.md

@@ -1,4 +1,4 @@
-# WS2812 Nominal Timing Register Values
+# WS2812B Nominal Timing Register Values
 
 WS2812 Nominal High+Low Timing: 1.25us +/- 600ns
 
@@ -25,7 +25,7 @@ T1H+T1L | 1300         | 600
 
 Operation  | Minimum (ns) | Tolerance (ns)
 ---------- | ------------ | --------------
-Reset Code | 50000        | -
+Reset Code | 280000       | -
 
 
 ### Oscillator
@@ -57,9 +57,9 @@ T1H+T1L | 57.629  | 59             | 1330.93
 
 Operation  | Divisor  | Register Value | FPGA Timing (ns)
 ---------- | -------- | -------------- | ----------------
-Reset Code | 17.316   | 18             | 51973.83
+Reset Code | 48.48593 | 49             | 282968.64
 
 ```
 Notes:
-1)  The Reset Code register value is multiplied by 128 in system.
+1)  The Reset Code register value is multiplied by 256 in system.
 ```

doc/SPI Commands.md

@@ -17,7 +17,7 @@ Load Reset Code  | 0x07         | -            | -          | 1+
 
 ```
 Notes:
-1) Command fields with "-" indicate they are not present.
+1) Command fields with "-" indicate they are not present for the command.
 2) During Load RGB, Load WRGB, Load Reset Cycle and Load Reset Code commands the
    Status Register value is returned on the MISO. The Status Register has fields
    for the state of the FIFO and can be used for flow control by the Master.