Skip to content

Commit 23f2e0c

Browse files
LucAceLucAce
committed
Added ldf for -6 part
1 parent 6040b1e commit 23f2e0c

2 files changed

Lines changed: 29 additions & 0 deletions

File tree

prj/top/top.ldf renamed to prj/top/top_LCMXO2-1200HC-4SG32C.ldf

File renamed without changes.

‎prj/top/top_LCMXO2-1200HC-6SG32I.ldf‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
<?xml version="1.0" encoding="UTF-8"?>
2+
<BaliProject version="3.2" title="top" device="LCMXO2-1200HC-6SG32I" default_implementation="impl1">
3+
<Options/>
4+
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
5+
<Options def_top="top"/>
6+
<Source name="../../rtl/ctrl.v" type="Verilog" type_short="Verilog">
7+
<Options/>
8+
</Source>
9+
<Source name="../../rtl/fifo_dc_efb.v" type="Verilog" type_short="Verilog">
10+
<Options/>
11+
</Source>
12+
<Source name="../../rtl/regs.v" type="Verilog" type_short="Verilog">
13+
<Options/>
14+
</Source>
15+
<Source name="../../rtl/ser.v" type="Verilog" type_short="Verilog">
16+
<Options/>
17+
</Source>
18+
<Source name="../../rtl/slave_efb.v" type="Verilog" type_short="Verilog">
19+
<Options/>
20+
</Source>
21+
<Source name="../../rtl/top.v" type="Verilog" type_short="Verilog">
22+
<Options top_module="top"/>
23+
</Source>
24+
<Source name="../../syn/machxo2_qfn32.lpf" type="Logic Preference" type_short="LPF">
25+
<Options/>
26+
</Source>
27+
</Implementation>
28+
<Strategy name="Strategy1" file="top1.sty"/>
29+
</BaliProject>

0 commit comments

Comments
 (0)