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1 parent 780ca06 commit 749c16bCopy full SHA for 749c16b
1 file changed
sim/tb/tb_registers.v
@@ -82,22 +82,22 @@ module tb_top;
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cmd_reg_verify(8'h06, 8'h67);
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// Reg 0x07: Zero High Timing
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- cmd_reg_verify(8'h07, 8'h10);
+ cmd_reg_verify(8'h07, 8'h12);
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// Reg 0x08: Zero Low Timing
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- cmd_reg_verify(8'h08, 8'h24);
+ cmd_reg_verify(8'h08, 8'h26);
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// Reg 0x09: One High Timing
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- cmd_reg_verify(8'h09, 8'h20);
+ cmd_reg_verify(8'h09, 8'h26);
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// Reg 0x0A: One Low Timing
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- cmd_reg_verify(8'h0A, 8'h1B);
+ cmd_reg_verify(8'h0A, 8'h12);
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// Reg 0x0B: Reset Cycle Timing
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- cmd_reg_verify(8'h0B, 8'h34);
+ cmd_reg_verify(8'h0B, 8'h38);
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// Reg 0x0C: Reset Code Timing
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- cmd_reg_verify(8'h0C, 8'h12);
+ cmd_reg_verify(8'h0C, 8'h09);
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// Reg 0x0D: Run
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cmd_reg_verify(8'h0D, 8'h01);
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