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Update tb registers to match design
1 parent 780ca06 commit 749c16b

1 file changed

Lines changed: 6 additions & 6 deletions

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sim/tb/tb_registers.v

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -82,22 +82,22 @@ module tb_top;
8282
cmd_reg_verify(8'h06, 8'h67);
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8484
// Reg 0x07: Zero High Timing
85-
cmd_reg_verify(8'h07, 8'h10);
85+
cmd_reg_verify(8'h07, 8'h12);
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8787
// Reg 0x08: Zero Low Timing
88-
cmd_reg_verify(8'h08, 8'h24);
88+
cmd_reg_verify(8'h08, 8'h26);
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// Reg 0x09: One High Timing
91-
cmd_reg_verify(8'h09, 8'h20);
91+
cmd_reg_verify(8'h09, 8'h26);
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// Reg 0x0A: One Low Timing
94-
cmd_reg_verify(8'h0A, 8'h1B);
94+
cmd_reg_verify(8'h0A, 8'h12);
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9696
// Reg 0x0B: Reset Cycle Timing
97-
cmd_reg_verify(8'h0B, 8'h34);
97+
cmd_reg_verify(8'h0B, 8'h38);
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9999
// Reg 0x0C: Reset Code Timing
100-
cmd_reg_verify(8'h0C, 8'h12);
100+
cmd_reg_verify(8'h0C, 8'h09);
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102102
// Reg 0x0D: Run
103103
cmd_reg_verify(8'h0D, 8'h01);

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