Porting guidance for altera cyclone

[linhz0hz]

Hello,
Thank you for sharing this controller. However I have some trouble porting it to altera cyclone parts.
Specifically, IDELAY is used in the rx path. However it seems altera part do not have such capability.
I am not very experienced in this, some guidance or suggestion would be highly appreciated.

[MJoergen]

Hi!

I did some quick searching and found the following link: Cyclone II Device Family Data Sheet. I think what you want to search for is "input delay" or "delay chain".

A second option is to look at how Altera devices handle DDR memory, because in those situations they need a similar input delay on the DQS signal.

[linhz0hz]

I think on Cyclone Iv / 10 that I checked, such input delay is not exposed to the user / I have not found it. So I cannot instantiate something like you did for Xilinx devices, which sets a fixed delay parameter.
In Cyclone IV DDR memory driver, they seem to ignore DQS in read phase but uses a another clock shifted from the memory clock with a phase. (A 0 deg, 90 deg for write DQS, and another phase for read, possibly live calibrated?)
Maybe adding another phase could work for HyperRAM as well? But this might be quite different from what you are currently doing?

[linhz0hz]

Maybe a hacky way is logic delay lines? As suggested by https://community.altera.com/discussions/fpga-device/source-synchronous-interface-on-cyclone-iii-without-pll/81512

[MJoergen]

Your last link includes the following comment:
"Instead of explicitly adding lcells, one may also try to specify delays in the timming constrains (set_min_delay and set_max_delay) and see if Quartus is able to produce decent results."
That might be a route to go. However, I don't have much experience, whether this method will actually work. But it's worth a try, and requires very little modification.

Another option is what you yourself suggested: Adding a second clock with a 90 degrees phase shift. The way I would use it is to have all the output signals to the HyperRAM (both clock and data) use a delayed clock (just for this purpose). In that way, the received data will be similarly delayed. Then in the receive path use the internal (not delayed) clock to sample the data.