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Merge branch 'main' into feature/iif_upgrades
2 parents 9f0f140 + d921fe4 commit 2875f35

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Lines changed: 930 additions & 150 deletions

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‎.github/workflows/ci-compile.yml‎

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This file was deleted.

‎.github/workflows/ci.yml‎

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name: CI
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on:
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workflow_dispatch:
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push:
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paths:
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- '**.hpp'
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- '**.cpp'
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- '**.h'
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- '**.c'
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- '**.S'
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- '**CMakeLists.txt'
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- '.github/workflows/**'
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- 'conanfile.py'
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pull_request:
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paths:
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- '**.hpp'
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- '**.cpp'
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- '**.h'
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- '**.c'
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- '**.S'
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- '**CMakeLists.txt'
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- '.github/workflows/**'
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- 'conanfile.py'
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jobs:
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cpp-compliance:
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name: C++ Std Compliance (C++${{ matrix.cpp_std }})
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runs-on: ubuntu-24.04
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strategy:
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matrix:
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cpp_std: [17, 20]
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steps:
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- uses: actions/checkout@v4
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- name: Update submodules
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run: git submodule update --init --recursive
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- name: Cache Conan
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uses: actions/cache@v4
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with:
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path: ~/.conan2
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key: conan-${{ runner.os }}-unit-cpp${{ matrix.cpp_std }}-${{ hashFiles('conanfile.py') }}
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- name: Install dependencies
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run: |
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sudo apt-get install -y g++ python3-pip cmake llvm-19-dev
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pip3 install conan
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cmake --version
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- name: Configure
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run: cmake --preset Release -B build -DCMAKE_CXX_STANDARD=${{ matrix.cpp_std }} -DWITH_LLVM=ON -DWITH_SYSTEM_LLVM=ON
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- name: Build
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run: cmake --build build -j
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- name: Smoke test
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run: ./build/riscv-sim -h
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# NOTE: .so filename is tied to VERSION in top-level CMakeLists.txt - update both together
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- name: Upload binary
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if: matrix.cpp_std == 20
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uses: actions/upload-artifact@v4
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with:
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name: riscv-sim
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path: |
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build/riscv-sim
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build/libdbt-rise-riscv.so.2.1.0
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pmp-tests:
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name: PMP Functional Tests
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runs-on: ubuntu-24.04
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needs: cpp-compliance
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steps:
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- uses: actions/checkout@v4
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- name: Install RISC-V toolchain
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run: sudo apt-get install -y gcc-riscv64-unknown-elf
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- name: Download riscv-sim binary
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uses: actions/download-artifact@v4
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with:
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name: riscv-sim
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- name: Make binary executable
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run: chmod +x riscv-sim
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- name: Build PMP CSR test firmware
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run: |
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riscv64-unknown-elf-gcc -nostdlib -march=rv64gc -mabi=lp64 \
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-Wl,-Ttext=0x10000,--no-dynamic-linker \
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-o pmp_csr_test \
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contrib/fw/pmp-csr-test/pmp_csr_test.S
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- name: rv64gc_m CSR test - interp (no PMP, expect exit 2)
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run: |
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LD_LIBRARY_PATH=. ./riscv-sim -f pmp_csr_test --isa rv64gc_m --backend interp || rc=$?
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[ "${rc:-0}" -eq 2 ]
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- name: rv64gc_mp CSR test - interp (with PMP)
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run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_csr_test --isa rv64gc_mp --backend interp
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- name: Build PMP enforcement test firmware
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run: |
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riscv64-unknown-elf-gcc -nostdlib -march=rv64gc -mabi=lp64 \
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-Wl,-Ttext=0x10000,--no-dynamic-linker \
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-o pmp_enforce_test \
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contrib/fw/pmp-enforce-test/pmp_enforce_test.S
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- name: rv64gc_mp enforcement test - interp
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run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_enforce_test --isa rv64gc_mp --backend interp
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- name: Build PMP shift test firmware
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run: |
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riscv64-unknown-elf-gcc -nostdlib -march=rv64gc -mabi=lp64 \
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-Wl,-Ttext=0x10000,--no-dynamic-linker \
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-o pmp_shift_test \
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contrib/fw/pmp-shift-test/pmp_shift_test.S
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- name: rv64gc_mp shift test - interp
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run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_shift_test --isa rv64gc_mp --backend interp
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- name: Build PMP upper-cfg test firmware
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run: |
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riscv64-unknown-elf-gcc -nostdlib -march=rv64gc -mabi=lp64 \
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-Wl,-Ttext=0x10000,--no-dynamic-linker \
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-o pmp_upper_cfg_test \
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contrib/fw/pmp-upper-cfg-test/pmp_upper_cfg_test.S
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- name: rv64gc_mp upper-cfg test - interp
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run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_upper_cfg_test --isa rv64gc_mp --backend interp
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- name: Build PMP cfg2 test firmware
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run: |
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riscv64-unknown-elf-gcc -nostdlib -march=rv64gc -mabi=lp64 \
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-Wl,-Ttext=0x10000,--no-dynamic-linker \
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-o pmp_cfg2_test \
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contrib/fw/pmp-cfg2-test/pmp_cfg2_test.S
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- name: rv64gc_mp cfg2 test - interp
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run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_cfg2_test --isa rv64gc_mp --backend interp
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- name: Build PMP TOR test firmware
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run: |
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riscv64-unknown-elf-gcc -nostdlib -march=rv64gc -mabi=lp64 \
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-Wl,-Ttext=0x10000,--no-dynamic-linker \
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-o pmp_tor_test \
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contrib/fw/pmp-tor-test/pmp_tor_test.S
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- name: rv64gc_mp TOR test - interp
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run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_tor_test --isa rv64gc_mp --backend interp
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- name: Build PMP 64-entry pmpaddr test firmware
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run: |
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riscv64-unknown-elf-gcc -nostdlib -march=rv64gc -mabi=lp64 \
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-Wl,-Ttext=0x10000,--no-dynamic-linker \
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-o pmp_64entry_addr_test \
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contrib/fw/pmp-64entry-addr-test/pmp_64entry_addr_test.S
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- name: rv64gc_mp 64-entry pmpaddr test - interp
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run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_64entry_addr_test --isa rv64gc_mp --backend interp
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- name: Build PMP 64-entry pmpcfg test firmware
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run: |
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riscv64-unknown-elf-gcc -nostdlib -march=rv64gc -mabi=lp64 \
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-Wl,-Ttext=0x10000,--no-dynamic-linker \
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-o pmp_64entry_cfg_test \
168+
contrib/fw/pmp-64entry-cfg-test/pmp_64entry_cfg_test.S
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- name: rv64gc_mp 64-entry pmpcfg test - interp
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run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_64entry_cfg_test --isa rv64gc_mp --backend interp
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- name: Build PMP 8-entry guard test firmware (VP/S5 model)
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run: |
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riscv64-unknown-elf-gcc -nostdlib -march=rv64gc -mabi=lp64 \
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-Wl,-Ttext=0x10000,--no-dynamic-linker \
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-o pmp_8entry_guard_test \
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contrib/fw/pmp-8entry-guard-test/pmp_8entry_guard_test.S
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- name: rv64gc_mp_8 8-entry enforcement test - interp (VP/S5 model)
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run: LD_LIBRARY_PATH=. ./riscv-sim -f pmp_8entry_guard_test --isa rv64gc_mp_8 --backend interp

‎CMakeLists.txt‎

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@@ -22,20 +22,34 @@ if(OPTIMIZE_FOR_NATIVE AND COMPILER_SUPPORTS_MARCH_NATIVE)
2222
set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native")
2323
endif()
2424

25+
option(WITH_SYSTEM_LLVM "Use system-installed LLVM (llvm-dev from apt) instead of Conan-built" OFF)
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set(LLVM_MAJOR_VERSION "19" CACHE STRING "System LLVM major version when WITH_SYSTEM_LLVM=ON")
27+
if(WITH_SYSTEM_LLVM)
28+
set(LLVM_DIR "/usr/lib/llvm-${LLVM_MAJOR_VERSION}/lib/cmake/llvm" CACHE PATH "" FORCE)
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find_package(LLVM REQUIRED CONFIG BYPASS_PROVIDER)
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message(STATUS "Found system LLVM ${LLVM_VERSION}")
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if(NOT TARGET llvm-core::llvm-core)
32+
add_library(llvm-core::llvm-core INTERFACE IMPORTED GLOBAL)
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target_include_directories(llvm-core::llvm-core INTERFACE ${LLVM_INCLUDE_DIRS})
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target_compile_definitions(llvm-core::llvm-core INTERFACE ${LLVM_DEFINITIONS})
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target_link_libraries(llvm-core::llvm-core INTERFACE LLVM-${LLVM_VERSION_MAJOR})
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endif()
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if(NOT WITH_LLVM)
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set(WITH_LLVM ON CACHE BOOL "Build LLVM backend" FORCE)
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endif()
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endif()
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2542
include(FetchContent)
2643
if(NOT TARGET dbt-rise-core)
2744
FetchContent_Declare(
2845
dbt_rise_core_git
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GIT_REPOSITORY "https://github.com/Minres/DBT-RISE-Core.git"
30-
GIT_TAG daa01b423360e7677a30d61f913cfa1bf09a1251
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GIT_TAG 9b571ff9
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GIT_SHALLOW OFF
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UPDATE_DISCONNECTED NOT ${UPDATE_EXTERNAL_PROJECT} # When enabled, this option causes the update step to be skipped.
3350
)
3451
FetchContent_GetProperties(dbt_rise_core_git)
35-
if(NOT dbt_rise_core_git_POPULATED)
36-
FetchContent_Populate(dbt_rise_core_git)
37-
endif()
38-
add_subdirectory(${dbt_rise_core_git_SOURCE_DIR} ${dbt_rise_core_git_BINARY_DIR})
52+
FetchContent_MakeAvailable(dbt_rise_core_git)
3953
endif()
4054
FetchContent_GetProperties(scc_git)
4155
list(APPEND CMAKE_MODULE_PATH ${scc_git_SOURCE_DIR}/cmake)
@@ -73,6 +87,7 @@ set(LIB_SOURCES
7387
src/vm/interp/vm_rv64i.cpp
7488
src/vm/interp/vm_rv64imac.cpp
7589
src/vm/interp/vm_rv64gc.cpp
90+
src/vm/interp/vm_rv64gc_mp.cpp
7691
src/vm/interp/vm_rv64gcv.cpp
7792
src/iss/debugger/csr_names.cpp
7893
src/iss/semihosting/semihosting.cpp
@@ -249,7 +264,7 @@ endif()
249264
###############################################################################
250265
if(TARGET scc-sysc)
251266
project(dbt-rise-riscv_sc VERSION 1.0.0)
252-
set(USE_SC_SIGNAL4IRQ OFF CACHE BOOL "Enable the use of ssc_signals for interrupt delivery")
267+
set(USE_SC_SIGNAL4IRQ OFF CACHE BOOL "Enable the use of sc_signals for interrupt delivery")
253268

254269
set(LIB_SOURCES
255270
src/sysc/core_complex.cpp
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265280
set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
266281

267282
add_library(${PROJECT_NAME}_sig ${LIB_SOURCES})
268-
target_compile_definitions(${PROJECT_NAME}_sig PUBLIC SC_SIGNAL_IF)
269283
target_compile_definitions(${PROJECT_NAME}_sig PUBLIC WITH_SYSTEMC SC_SIGNAL_IF)
270284
target_link_libraries(${PROJECT_NAME}_sig PUBLIC dbt-rise-riscv scc-sysc)
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‎README.md‎

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[![CI C++ Std compliance](https://github.com/Minres/DBT-RISE-RISCV/actions/workflows/ci-compile.yml/badge.svg)](https://github.com/Minres/DBT-RISE-RISCV/actions/workflows/ci-compile.yml)
1+
[![CI](https://github.com/Minres/DBT-RISE-RISCV/actions/workflows/ci.yml/badge.svg)](https://github.com/Minres/DBT-RISE-RISCV/actions/workflows/ci.yml)
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33
# DBT-RISE-RISCV
44
A instruction set simulator based on DBT-RISE implementing the RISC-V ISA.
@@ -63,4 +63,4 @@ make -C build/Firmwares/hello-world/ ISA=imc BOARD=iss
6363
- JIT-backends for higher execution speeds
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- Built-in plugin support to inspect or manipulate architectural state before and after each instruction
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- Full GDB-server
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- Easy integration into SystemC or similar (eg. Platform Architect)
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- Easy integration into SystemC or similar (eg. Platform Architect)

‎conanfile.py‎

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3636
}
3737

3838
def requirements(self):
39-
self.requires("fmt/12.0.0")
40-
self.requires("spdlog/1.16.0")
39+
self.requires("fmt/12.1.0")
40+
self.requires("spdlog/1.17.0")
4141
self.requires("boost/1.85.0")
4242
self.requires("elfio/3.12")
4343
self.requires("lz4/1.10.0")
44-
self.requires("yaml-cpp/0.8.0")
44+
self.requires("yaml-cpp/0.9.0")
4545
self.requires("jsoncpp/1.9.6")
4646
self.requires("zlib/1.3.1")
4747
self.requires("asmjit/cci.20240531")

‎contrib/fw/pmp-64entry-addr-test/pmp_64entry_addr_test.S‎

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// Verify pmpaddr32 (CSR 0x3D0) is accessible - tests 64-entry pmpaddr support.
2+
// Pass: readback matches written sentinel -> j . (exit 0)
3+
// Fail: any trap (unregistered CSR) or readback mismatch -> semihosting SYS_EXIT (exit 2)
4+
5+
.section .text
6+
.globl _start
7+
_start:
8+
la t0, fail
9+
csrw mtvec, t0
10+
11+
li t0, 0xDEAD
12+
csrw 0x3D0, t0 // pmpaddr32
13+
csrr t1, 0x3D0
14+
bne t0, t1, fail
15+
16+
j . // pass
17+
18+
fail:
19+
li a0, 0x18
20+
.option push
21+
.option norvc
22+
slli zero, zero, 0x1f
23+
ebreak
24+
srai zero, zero, 7
25+
.option pop
26+
j .

‎contrib/fw/pmp-64entry-cfg-test/pmp_64entry_cfg_test.S‎

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@@ -0,0 +1,34 @@
1+
// Verify pmpcfg4 (CSR 0x3A4, holds entries 32-39 on RV64) is accessible and persistent.
2+
// Tests 64-entry pmpcfg registration.
3+
// Pass: write 0x9F -> read back 0x9F -> write 0 -> read back 0 -> j . (exit 0)
4+
// Fail: any trap or readback mismatch -> semihosting SYS_EXIT (exit 2)
5+
6+
.section .text
7+
.globl _start
8+
_start:
9+
la t0, fail
10+
csrw mtvec, t0
11+
12+
// Write and verify a non-zero value
13+
li t0, 0x9F
14+
csrw 0x3A4, t0 // pmpcfg4 write
15+
csrr t1, 0x3A4 // pmpcfg4 read
16+
bne t0, t1, fail // must match
17+
18+
// Clear and verify zero
19+
li t0, 0
20+
csrw 0x3A4, t0
21+
csrr t1, 0x3A4
22+
bne t0, t1, fail
23+
24+
j . // pass
25+
26+
fail:
27+
li a0, 0x18
28+
.option push
29+
.option norvc
30+
slli zero, zero, 0x1f
31+
ebreak
32+
srai zero, zero, 7
33+
.option pop
34+
j .

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