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evbarm/am18: basic plaform code
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‎sys/arch/arm/ti/am18xx_platform.c‎

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/* $NetBSD $ */
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/*-
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* Copyright (c) 2026 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Yuri Honegger.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Platform code for the TI AM18XX family of SOCs (AM1808, AM1810). In linux
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* land and in the device trees, this platform is sometimes also called DA830
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* and DA850 (Davinci 8XX) because their silicon has a lot in common.
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*/
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#include "opt_console.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD $");
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#include <uvm/uvm_extern.h>
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#include <dev/fdt/fdt_platform.h>
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#include <dev/fdt/fdtvar.h>
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#include <dev/ic/comreg.h>
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#include <arch/evbarm/fdt/platform.h>
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#include <arm/fdt/arm_fdtvar.h>
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#define AM18XX_IO_VBASE KERNEL_IO_VBASE
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#define AM18XX_IO_PBASE 0x01c00000
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#define AM18XX_IO_SIZE 0x00400000
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#define AM18XX_INTC_VBASE (AM18XX_IO_VBASE + AM18XX_IO_SIZE)
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#define AM18XX_INTC_PBASE 0xfffee000
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#define AM18XX_INTC_SIZE 0x2000
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#define AM18XX_TIMER1_BASE 0x01C21000
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#define AM18XX_TIMER1_SIZE 0x1000
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#define AM18XX_TIMER1_TIM12 0x10
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#define AM18XX_TIMER1_TIM34 0x14
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#define AM18XX_TIMER1_PRD12 0x18
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#define AM18XX_TIMER1_PRD34 0x1C
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#define AM18XX_TIMER1_TCR 0x20
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#define AM18XX_TIMER1_TGCR 0x24
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#define AM18XX_TIMER1_WDTCR 0x28
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#define AM18XX_TIMER_TCR_ENAMODE12_CONTINUOUS 0x80
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#define AM18XX_TIMER_TGCR_TIMMODE32_UNCHAINED 0x4
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#define AM18XX_TIMER_TGCR_TIMMODE64_WATCHDOG 0x8
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#define AM18XX_TIMER_TGCR_TIM12EN 1
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#define AM18XX_TIMER_TGCR_TIM34EN 2
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#define AM18XX_TIMER_WDTCR_WDEN 1
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#define AM18XX_TIMER_WDTCR_KEY0 0xa5c60000
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#define AM18XX_TIMER_WDTCR_KEY1 0xda7e0000
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void am18xx_platform_early_putchar(char);
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extern struct arm32_bus_dma_tag arm_generic_dma_tag;
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extern struct bus_space arm_generic_bs_tag;
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void __noasan
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am18xx_platform_early_putchar(char c)
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{
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#ifdef CONSADDR
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#define CONSADDR_VA (CONSADDR - AM18XX_IO_PBASE + KERNEL_IO_VBASE)
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volatile uint32_t *uartaddr = cpu_earlydevice_va_p()
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? (volatile uint32_t *)CONSADDR_VA
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: (volatile uint32_t *)CONSADDR;
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while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0)
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continue;
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uartaddr[com_data] = htole32(c);
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#endif
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}
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static const struct pmap_devmap *
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am18xx_platform_devmap(void)
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{
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static const struct pmap_devmap devmap[] = {
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/* input/output registers */
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DEVMAP_ENTRY(AM18XX_IO_VBASE,
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AM18XX_IO_PBASE,
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AM18XX_IO_SIZE),
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/* interrupt controller */
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DEVMAP_ENTRY(AM18XX_INTC_VBASE,
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AM18XX_INTC_PBASE,
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AM18XX_INTC_SIZE),
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DEVMAP_ENTRY_END
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};
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return devmap;
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}
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static void
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am18xx_platform_init_attach_args(struct fdt_attach_args *faa)
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{
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faa->faa_bst = &arm_generic_bs_tag;
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faa->faa_dmat = &arm_generic_dma_tag;
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}
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static void
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am18xx_platform_delay(u_int n)
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{
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/* Use Timer1 for delay. Timer0 is used*/
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static bus_space_tag_t bst = &arm_generic_bs_tag;
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static bus_space_handle_t bsh = 0;
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if (bsh == 0) {
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/* map Timer1 */
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bus_space_map(bst, AM18XX_TIMER1_BASE, AM18XX_TIMER1_SIZE,
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0, &bsh);
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/* disable counter to allow changing mode */
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_TCR, 0);
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/* set mode to 32-bit unchained */
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_TGCR,
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AM18XX_TIMER_TGCR_TIMMODE32_UNCHAINED |
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AM18XX_TIMER_TGCR_TIM12EN);
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/* load period registers with maximum period */
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_PRD12, 0xFFFFFFFF);
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/* enable timer */
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_TCR,
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AM18XX_TIMER_TCR_ENAMODE12_CONTINUOUS);
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}
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/*
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* The counter is driven by PLL0_AUXCLK, which is taken from OSCIN.
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* On the EV3, that is 24MHz.
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*
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* n is in microseconds (us)
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*
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* TODO: The frequency is board-dependent and we should get it from the
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* device tree.
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*/
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long ticks = n * (24000000 / 1000000);
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uint32_t prev, cur;
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prev = bus_space_read_4(bst, bsh, AM18XX_TIMER1_TIM12);
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while (ticks > 0) {
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cur = bus_space_read_4(bst, bsh, AM18XX_TIMER1_TIM12);
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if (cur >= prev)
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ticks -= (cur - prev);
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else
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ticks -= (UINT32_MAX - cur + prev);
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prev = cur;
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}
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}
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/*
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* To reset the AM1808, you have to crash the watchdog.
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*/
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static void
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am18xx_platform_reset(void)
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{
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/* map TIMER1 */
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bus_space_tag_t bst = &arm_generic_bs_tag;
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bus_space_handle_t bsh = 0;
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bus_space_map(bst, AM18XX_TIMER1_BASE, AM18XX_TIMER1_SIZE, 0, &bsh);
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/* disable counter to allow changing mode */
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_TCR, 0);
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/* set mode to watchdog unchained */
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_TGCR,
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AM18XX_TIMER_TGCR_TIMMODE64_WATCHDOG |
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AM18XX_TIMER_TGCR_TIM12EN |
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AM18XX_TIMER_TGCR_TIM34EN);
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/* set counter and reload registers */
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_TIM12, 0);
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_TIM34, 0);
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_PRD12, 0);
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_PRD34, 0);
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/* execute the watchdog enable sequence */
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_WDTCR,
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AM18XX_TIMER_WDTCR_KEY0 | AM18XX_TIMER_WDTCR_WDEN);
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_WDTCR,
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AM18XX_TIMER_WDTCR_KEY1 | AM18XX_TIMER_WDTCR_WDEN);
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/* trigger a reset by writing an invalid value to WDTCR*/
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bus_space_write_4(bst, bsh, AM18XX_TIMER1_WDTCR, 0xaffe);
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/* NOTREACHED */
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}
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static const struct fdt_platform am18xx_platform = {
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.fp_devmap = am18xx_platform_devmap,
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.fp_bootstrap = arm_fdt_cpu_bootstrap,
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.fp_init_attach_args = am18xx_platform_init_attach_args,
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.fp_uart_freq = NULL,
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.fp_delay = am18xx_platform_delay,
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.fp_reset = am18xx_platform_reset,
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};
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/* The device tree name for the AM1808 is da850 (davinci 850) */
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FDT_PLATFORM(am18xx, "ti,da850", &am18xx_platform);

‎sys/arch/arm/ti/files.ti‎

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#
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file arch/arm/ti/ti_cpufreq.c soc_ti
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file arch/arm/ti/am18xx_platform.c soc_am18xx
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file arch/arm/ti/am3_platform.c soc_am33xx
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file arch/arm/ti/omap3_platform.c soc_omap3 | soc_omap4
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file arch/arm/ti/omap_smc.S soc_omap4
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# SOC parameters XXX FDT_SYSCON
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defflag opt_soc.h SOC_TI: FDT_SYSCON
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defflag opt_soc.h SOC_AM18XX: SOC_TI
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defflag opt_soc.h SOC_AM33XX: SOC_TI
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defflag opt_soc.h SOC_OMAP3: SOC_TI
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defflag opt_soc.h SOC_OMAP4: SOC_TI

‎sys/arch/evbarm/conf/GENERIC_V5‎

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options CPU_ARM9E
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options SOC_IMX23
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options SOC_AM18XX
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#options DIAGNOSTIC # internal consistency checks
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#options DEBUG
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# EARLYCONS is required for early init messages from VERBOSE_INIT_ARM.
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#options EARLYCONS=imx23, CONSADDR=0x80070000
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#options EARLYCONS=am18xx, CONSADDR=0x01D0C000 # serial1
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# Kernel Undefined Behavior Sanitizer (kUBSan). Use UBSAN_ALWAYS_FATAL
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# if you want panics instead of warnings.

‎sys/arch/evbarm/conf/files.generic_v5‎

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# Add other board files here
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include "arch/arm/imx/files.imx23"
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include "arch/arm/ti/files.ti"
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#
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# Stack-less Just-In-Time compiler

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