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evbarm/am18xx: add pll controller
1 parent 1d64049 commit 6500f5b

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Lines changed: 330 additions & 1 deletion

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‎sys/arch/arm/ti/am18xx_pllc.c‎

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/* $NetBSD $ */
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/*-
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* Copyright (c) 2026 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Yuri Honegger.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PLL Controller for the TI AM18XX SOC.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cdefs.h>
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#include <sys/device.h>
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#include <dev/clk/clk_backend.h>
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#include <dev/fdt/fdtvar.h>
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#include <arm/fdt/arm_fdtvar.h>
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struct am18xx_pllc_softc;
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struct am18xx_pllc_clk {
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struct clk clk_base; /* must be first */
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u_int (*get_rate)(struct am18xx_pllc_softc *, struct am18xx_pllc_clk *);
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u_int clk_index;
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};
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struct am18xx_pllc_config {
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struct am18xx_pllc_clk *sysclks;
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struct am18xx_pllc_clk *auxclk;
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int num_sysclk;
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};
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struct am18xx_pllc_softc {
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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int sc_sysclk_phandle;
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int sc_auxclk_phandle;
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const struct am18xx_pllc_config *sc_config;
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struct clk_domain sc_clkdom;
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struct clk *sc_ref_clk;
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};
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static int am18xx_pllc_match(device_t, cfdata_t, void *);
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static void am18xx_pllc_attach(device_t, device_t, void *);
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static u_int am18xx_pllc_get_sysclk_rate(struct am18xx_pllc_softc *,
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struct am18xx_pllc_clk *);
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static u_int am18xx_pllc_get_auxclk_rate(struct am18xx_pllc_softc *,
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struct am18xx_pllc_clk *);
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static struct clk * am18xx_pllc_decode(device_t, int, const void *, size_t);
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static struct clk * am18xx_pllc_clk_get(void *, const char *);
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static u_int am18xx_pllc_clk_get_rate(void *, struct clk *);
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static struct clk * am18xx_pllc_clk_get_parent(void *, struct clk *);
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CFATTACH_DECL_NEW(am18xxpllc, sizeof(struct am18xx_pllc_softc),
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am18xx_pllc_match, am18xx_pllc_attach, NULL, NULL);
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#define AM18XX_PLLC_PLLCTL 0x100
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#define AM18XX_PLLC_PLLM 0x110
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#define AM18XX_PLLC_PREDIV 0x114
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#define AM18XX_PLLC_PLLDIV1 0x118
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#define AM18XX_PLLC_POSTDIV 0x128
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#define AM18XX_PLLC_PLLDIV4 0x160
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#define AM18XX_PLLC_PLLCTL_PLLEN __BIT(0)
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#define AM18XX_PLLC_PLLCTL_EXTCLKSRC __BIT(9)
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#define AM18XX_PLLC_PLLM_MULTIPLIER __BITS(4,0)
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#define AM18XX_PLLC_PREDIV_RATIO __BITS(4,0)
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#define AM18XX_PLLC_POSTDIV_RATIO __BITS(4,0)
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#define AM18XX_PLLC_PLLDIV_RATIO __BITS(4,0)
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#define PLLC_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg)
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#define PLLC_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val)
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#define PLLC_CLK(_i, _name, _rate) \
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{ \
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.clk_base.name = (_name), \
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.clk_base.flags = 0, \
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.get_rate = (_rate), \
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.clk_index = (_i), \
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}
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static struct am18xx_pllc_clk am18xx_pllc_pll0_auxclk =
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PLLC_CLK(0, "pll0_auxclk", &am18xx_pllc_get_auxclk_rate);
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static struct am18xx_pllc_clk am18xx_pllc_pll0_sysclks[] = {
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PLLC_CLK(0, "pll0_sysclk1", &am18xx_pllc_get_sysclk_rate),
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PLLC_CLK(1, "pll0_sysclk2", &am18xx_pllc_get_sysclk_rate),
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PLLC_CLK(2, "pll0_sysclk3", &am18xx_pllc_get_sysclk_rate),
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PLLC_CLK(3, "pll0_sysclk4", &am18xx_pllc_get_sysclk_rate),
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PLLC_CLK(4, "pll0_sysclk5", &am18xx_pllc_get_sysclk_rate),
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PLLC_CLK(5, "pll0_sysclk6", &am18xx_pllc_get_sysclk_rate),
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PLLC_CLK(6, "pll0_sysclk7", &am18xx_pllc_get_sysclk_rate),
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};
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static const struct am18xx_pllc_config am18xx_pllc_pll0_config = {
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.auxclk = &am18xx_pllc_pll0_auxclk,
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.sysclks = am18xx_pllc_pll0_sysclks,
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.num_sysclk = __arraycount(am18xx_pllc_pll0_sysclks),
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};
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static const struct fdtbus_clock_controller_func am18xx_pllc_clk_fdt_funcs = {
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.decode = am18xx_pllc_decode,
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};
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static const struct clk_funcs am18xx_pllc_clk_funcs = {
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.get = am18xx_pllc_clk_get,
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.get_rate = am18xx_pllc_clk_get_rate,
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.get_parent = am18xx_pllc_clk_get_parent,
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};
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static const struct device_compatible_entry compat_data[] = {
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{ .compat = "ti,da850-pll0", .data = &am18xx_pllc_pll0_config },
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DEVICE_COMPAT_EOL
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};
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static struct clk *
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am18xx_pllc_clk_get(void *priv, const char *name)
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{
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struct am18xx_pllc_softc * const sc = priv;
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/* check if it is the auxclk */
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if (strcmp(sc->sc_config->auxclk->clk_base.name, name) == 0) {
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return &sc->sc_config->auxclk->clk_base;
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}
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/* check if it is a sysclk */
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for (int i = 0; i < sc->sc_config->num_sysclk; i++) {
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if (strcmp(sc->sc_config->sysclks[i].clk_base.name, name) == 0)
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return &sc->sc_config->sysclks[i].clk_base;
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}
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return NULL;
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}
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static u_int
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am18xx_pllc_clk_get_rate(void *priv, struct clk *clkp)
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{
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struct am18xx_pllc_softc * const sc = priv;
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struct am18xx_pllc_clk *clk = (struct am18xx_pllc_clk *)clkp;
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return clk->get_rate(sc, clk);
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}
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static struct clk *
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am18xx_pllc_clk_get_parent(void *priv, struct clk *clkp)
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{
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struct am18xx_pllc_softc * const sc = priv;
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return sc->sc_ref_clk;
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}
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static u_int
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am18xx_pllc_get_sysclk_rate(struct am18xx_pllc_softc *sc,
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struct am18xx_pllc_clk *clk)
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{
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uint32_t pllctl_reg = PLLC_READ(sc, AM18XX_PLLC_PLLCTL);
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uint32_t prediv_reg = PLLC_READ(sc, AM18XX_PLLC_PREDIV);
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uint32_t prediv_ratio = (prediv_reg & AM18XX_PLLC_PREDIV_RATIO) + 1;
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uint32_t pllm_reg = PLLC_READ(sc, AM18XX_PLLC_PLLM);
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uint32_t pllm_multiplier = (pllm_reg & AM18XX_PLLC_PLLM_MULTIPLIER) + 1;
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uint32_t postdiv_reg = PLLC_READ(sc, AM18XX_PLLC_POSTDIV);
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uint32_t postdiv_ratio = (postdiv_reg & AM18XX_PLLC_POSTDIV_RATIO) + 1;
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uint32_t plldiv_regaddr;
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if (clk->clk_index <= 2) {
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plldiv_regaddr = AM18XX_PLLC_PLLDIV1 + 4 * clk->clk_index;
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} else {
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plldiv_regaddr = AM18XX_PLLC_PLLDIV4 + 4 * (clk->clk_index - 3);
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}
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uint32_t plldiv_reg = PLLC_READ(sc, plldiv_regaddr);
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uint32_t plldiv_ratio = (plldiv_reg & AM18XX_PLLC_PLLDIV_RATIO) + 1;
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u_int ref_clk_rate = clk_get_rate(sc->sc_ref_clk);
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if (pllctl_reg & AM18XX_PLLC_PLLCTL_PLLEN) {
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/* PLL enabled */
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ref_clk_rate /= prediv_ratio;
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ref_clk_rate *= pllm_multiplier;
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ref_clk_rate /= postdiv_ratio;
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} else {
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/* bypass mode (ensure we aren't using the other PLL)*/
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KASSERT((pllctl_reg & AM18XX_PLLC_PLLCTL_EXTCLKSRC) == 0);
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}
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ref_clk_rate /= plldiv_ratio;
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return ref_clk_rate;
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}
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static u_int
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am18xx_pllc_get_auxclk_rate(struct am18xx_pllc_softc *sc,
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struct am18xx_pllc_clk *clk)
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{
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return clk_get_rate(sc->sc_ref_clk);
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}
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static struct clk *
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am18xx_pllc_decode(device_t dev, int cc_phandle, const void *data, size_t len)
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{
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struct am18xx_pllc_softc * const sc = device_private(dev);
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const u_int *cells = data;
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if (cc_phandle == sc->sc_sysclk_phandle) {
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if (len != 4)
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return NULL;
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const u_int clock_index = be32toh(cells[0]) - 1;
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if (clock_index >= sc->sc_config->num_sysclk) {
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return NULL;
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}
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return &sc->sc_config->sysclks[clock_index].clk_base;
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} else if (cc_phandle == sc->sc_auxclk_phandle) {
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return &sc->sc_config->auxclk->clk_base;
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}
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return NULL;
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}
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int
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am18xx_pllc_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_compatible_match(faa->faa_phandle, compat_data);
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}
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void
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am18xx_pllc_attach(device_t parent, device_t self, void *aux)
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{
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struct am18xx_pllc_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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bus_addr_t addr;
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bus_size_t size;
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sc->sc_bst = faa->faa_bst;
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sc->sc_config = of_compatible_lookup(phandle, compat_data)->data;
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/* map PSC control registers */
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
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aprint_error(": couldn't map registers\n");
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return;
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}
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/* get parent clock */
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sc->sc_ref_clk = fdtbus_clock_get_index(phandle, 0);
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if (sc->sc_ref_clk == NULL) {
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aprint_error(": couldn't get reference clock\n");
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return;
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}
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/* initialize clock domain */
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sc->sc_clkdom.name = device_xname(self);
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sc->sc_clkdom.funcs = &am18xx_pllc_clk_funcs;
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sc->sc_clkdom.priv = sc;
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/* initialize the clocks */
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sc->sc_config->auxclk->clk_base.domain = &sc->sc_clkdom;
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clk_attach(&sc->sc_config->auxclk->clk_base);
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for (int i = 0; i < sc->sc_config->num_sysclk; i++) {
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sc->sc_config->sysclks[i].clk_base.domain = &sc->sc_clkdom;
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clk_attach(&sc->sc_config->sysclks[i].clk_base);
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}
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/* register auxclk fdt controller*/
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sc->sc_auxclk_phandle = of_find_firstchild_byname(phandle, "auxclk");
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if (sc->sc_auxclk_phandle < 0) {
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aprint_error(": couldn't get pll0_auxclk child\n");
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return;
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}
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fdtbus_register_clock_controller(self, sc->sc_auxclk_phandle,
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&am18xx_pllc_clk_fdt_funcs);
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/* register sysclk fdt controller*/
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sc->sc_sysclk_phandle = of_find_firstchild_byname(phandle, "sysclk");
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if (sc->sc_sysclk_phandle < 0) {
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aprint_error(": couldn't get pll0_sysclk child\n");
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return;
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}
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fdtbus_register_clock_controller(self, sc->sc_sysclk_phandle,
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&am18xx_pllc_clk_fdt_funcs);
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aprint_normal("\n");
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}
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‎sys/arch/arm/ti/files.ti‎

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@@ -75,6 +75,10 @@ device am18xxpsc: fdt_clock
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attach am18xxpsc at fdt
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file arch/arm/ti/am18xx_psc.c am18xxpsc
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device am18xxpllc: fdt_clock
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attach am18xxpllc at fdt
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file arch/arm/ti/am18xx_pllc.c am18xxpllc
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# UART
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attach com at fdt with ti_com: ti_prcm
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file arch/arm/ti/ti_com.c ti_com needs-flag

‎sys/arch/evbarm/conf/GENERIC_V5‎

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@@ -72,7 +72,11 @@ imx23apbdma* at fdt? pass 1 # NXP i.MX23 DMA controller
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# Clock Controllers
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imx23clkctrl* at fdt? pass 1 # i.MX23 clock controller
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am18xxpsc* at fdt? pass 3 # TI AM18XX power&sleep controller
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am18xxpllc* at fdt? pass 2 # TI AM18XX pll controller
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am18xxpsc* at fdt? pass 4 # TI AM18XX power&sleep controller
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# System Controller
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syscon* at fdt? pass 1 # Generic System Controller
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# general FDT devices
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fclock* at fdt? pass 1

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