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evbarm/am18: add psc driver
The PSC is the power and sleep controller.
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‎sys/arch/arm/ti/am18xx_psc.c‎

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/* $NetBSD $ */
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/*-
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* Copyright (c) 2025 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Yuri Honegger.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Power&Sleep Controller for the TI AM18XX SOC.
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*/
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#include <sys/param.h>
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#include <sys/cdefs.h>
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#include <sys/device.h>
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#include <dev/clk/clk_backend.h>
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#include <dev/fdt/fdtvar.h>
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#include <arm/fdt/arm_fdtvar.h>
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#define MAX_PARENT_CLOCKS 5
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struct am18xx_psc_clk {
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struct clk clk_base;
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int clk_index;
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union {
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const char *clk_parent_name;
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struct clk *clk_parent;
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} u;
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};
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struct am18xx_psc_config {
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struct am18xx_psc_clk *clks;
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int clknum;
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};
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struct am18xx_psc_softc {
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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struct clk_domain sc_clkdom;
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struct clk parent_clocks[MAX_PARENT_CLOCKS];
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struct am18xx_psc_clk *sc_clks;
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int sc_clknum;
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};
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static int am18xx_psc_match(device_t, cfdata_t, void *);
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static void am18xx_psc_attach(device_t, device_t, void *);
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static struct clk * am18xx_psc_decode(device_t, int, const void *, size_t);
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static struct clk * am18xx_psc_clk_get(void *, const char *);
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static u_int am18xx_psc_clk_get_rate(void *, struct clk *);
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static int am18xx_psc_clk_enable(void *, struct clk *);
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static int am18xx_psc_clk_disable(void *, struct clk *);
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static struct clk * am18xx_psc_clk_get_parent(void *, struct clk *);
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static void am18xx_psc_clk_transition(struct am18xx_psc_softc *,
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struct am18xx_psc_clk *,
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uint32_t);
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CFATTACH_DECL_NEW(am18xxpsc, sizeof(struct am18xx_psc_softc),
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am18xx_psc_match, am18xx_psc_attach, NULL, NULL);
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#define AM18XX_PSC_PTCMD 0x120
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#define AM18XX_PSC_PTSTAT 0x128
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#define AM18XX_PSC_MDCTL0 0xA00
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#define AM18XX_PSC_PTCMD_GO_ALL 0x3
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#define AM18XX_PSC_PTSTAT_MASK 0x3
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#define AM18XX_PSC_MDCTL_DISABLE 0x2
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#define AM18XX_PSC_MDCTL_ENABLE 0x3
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#define PSC_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg)
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#define PSC_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val)
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#define PSC_CLK(_i, _name, _p) \
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{ \
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.clk_index = (_i), \
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.u.clk_parent_name = (_p), \
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.clk_base.name = (_name), \
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.clk_base.flags = 0, \
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}
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static struct am18xx_psc_clk am18xx_psc0_clks[] = {
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PSC_CLK(0, "edma0_cc0", "pll0_sysclk2"),
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PSC_CLK(1, "edma0_tc0", "pll0_sysclk2"),
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PSC_CLK(2, "edma0_tc1", "pll0_sysclk2"),
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PSC_CLK(3, "emifa", "async1"),
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PSC_CLK(4, "spi0", "pll0_sysclk2"),
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PSC_CLK(5, "sdmmc0", "pll0_sysclk2"),
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PSC_CLK(6, "aintc", "pll0_sysclk4"),
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PSC_CLK(7, "imem", "pll0_sysclk2"),
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PSC_CLK(8, NULL, NULL), /* unused */
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PSC_CLK(9, "uart0", "pll0_sysclk2"),
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PSC_CLK(10, NULL, NULL), /* scr0; purpose and parent clk unclear */
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PSC_CLK(11, NULL, NULL), /* scr1; purpose and parent clk unclear */
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PSC_CLK(12, NULL, NULL), /* scr2; purpose and parent clk unclear */
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PSC_CLK(13, "pru", "pll0_sysclk2"),
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PSC_CLK(14, "arm", "pll0_sysclk6"),
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};
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static struct am18xx_psc_clk am18xx_psc1_clks[] = {
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PSC_CLK(0, "edma1_cc0", "pll0_sysclk2"),
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PSC_CLK(1, "usb2_0", "pll0_sysclk2"),
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PSC_CLK(2, "usb1_1", "pll0_sysclk4"),
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PSC_CLK(3, "gpio", "pll0_sysclk4"),
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PSC_CLK(4, "hpi", "pll0_sysclk2"),
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PSC_CLK(5, "emac", "pll0_sysclk4"),
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PSC_CLK(6, "ddr", "pll0_sysclk2"),
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PSC_CLK(7, "mcasp0", "async3"),
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PSC_CLK(8, "sata", "pll0_sysclk2"),
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PSC_CLK(9, "vpif", "pll0_sysclk2"),
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PSC_CLK(10, "spi1", "async3"),
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PSC_CLK(11, "i2c1", "pll0_sysclk4"),
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PSC_CLK(12, "uart1", "async3"),
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PSC_CLK(13, "uart2", "async3"),
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PSC_CLK(14, "mcbsp0", "async3"),
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PSC_CLK(15, "mcbsp1", "async3"),
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PSC_CLK(16, "lcdc", "pll0_sysclk2"),
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PSC_CLK(17, "ehrpwm", "async3"),
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PSC_CLK(18, "sdmmc1", "pll0_sysclk2"),
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PSC_CLK(19, "upp", "pll0_sysclk2"),
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PSC_CLK(20, "ecap", "async3"),
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PSC_CLK(21, "edma1_tc0", "pll0_sysclk2"),
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};
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static const struct am18xx_psc_config am18xx_psc0_config = {
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.clks = am18xx_psc0_clks,
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.clknum = __arraycount(am18xx_psc0_clks)
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};
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static const struct am18xx_psc_config am18xx_psc1_config = {
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.clks = am18xx_psc1_clks,
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.clknum = __arraycount(am18xx_psc1_clks)
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};
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static const struct device_compatible_entry compat_data[] = {
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{ .compat = "ti,da850-psc0", .data = &am18xx_psc0_config },
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{ .compat = "ti,da850-psc1", .data = &am18xx_psc1_config },
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DEVICE_COMPAT_EOL
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};
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static const struct fdtbus_clock_controller_func am18xx_psc_clk_fdt_funcs = {
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.decode = am18xx_psc_decode,
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};
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static const struct clk_funcs am18xx_psc_clk_funcs = {
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.get = am18xx_psc_clk_get,
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.get_rate = am18xx_psc_clk_get_rate,
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.enable = am18xx_psc_clk_enable,
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.disable = am18xx_psc_clk_disable,
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.get_parent = am18xx_psc_clk_get_parent
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};
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static void
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am18xx_psc_clk_transition(struct am18xx_psc_softc *sc,
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struct am18xx_psc_clk *clk, uint32_t state)
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{
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/* update clock gate state */
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uint32_t mdctl_reg = AM18XX_PSC_MDCTL0 + 4*clk->clk_index;
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PSC_WRITE(sc, mdctl_reg, state);
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PSC_WRITE(sc, AM18XX_PSC_PTCMD, AM18XX_PSC_PTCMD_GO_ALL);
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/* wait for clock state transition to finish */
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while (PSC_READ(sc, AM18XX_PSC_PTSTAT) & AM18XX_PSC_PTSTAT_MASK)
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continue;
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}
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static struct clk *
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am18xx_psc_clk_get(void *priv, const char *name)
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{
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struct am18xx_psc_softc * const sc = priv;
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for (int i = 0; i < sc->sc_clknum; i++) {
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if (strcmp(sc->sc_clks[i].clk_base.name, name) == 0)
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return &sc->sc_clks[i].clk_base;
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}
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return NULL;
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}
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static u_int
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am18xx_psc_clk_get_rate(void *priv, struct clk *clkp)
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{
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struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp;
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/* The PSC is only for clock gates, rates are passed through */
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return clk_get_rate(clk->u.clk_parent);
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}
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static int
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am18xx_psc_clk_enable(void *priv, struct clk *clkp)
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{
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struct am18xx_psc_softc * const sc = priv;
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struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp;
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am18xx_psc_clk_transition(sc, clk, AM18XX_PSC_MDCTL_ENABLE);
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return 0;
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}
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static int
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am18xx_psc_clk_disable(void *priv, struct clk *clkp)
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{
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struct am18xx_psc_softc * const sc = priv;
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struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp;
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am18xx_psc_clk_transition(sc, clk, AM18XX_PSC_MDCTL_DISABLE);
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return 0;
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}
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static struct clk *
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am18xx_psc_clk_get_parent(void *priv, struct clk *clkp)
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{
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struct am18xx_psc_clk *clk = (struct am18xx_psc_clk *)clkp;
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return clk->u.clk_parent;
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}
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static struct clk *
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am18xx_psc_decode(device_t dev, int cc_phandle, const void *data, size_t len)
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{
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struct am18xx_psc_softc * const sc = device_private(dev);
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const u_int *cells = data;
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if (len != 4)
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return NULL;
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const u_int clock_index = be32toh(cells[0]);
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if (clock_index >= sc->sc_clknum)
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return NULL;
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struct am18xx_psc_clk *clk = &sc->sc_clks[clock_index];
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return &clk->clk_base;
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}
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int
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am18xx_psc_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_compatible_match(faa->faa_phandle, compat_data);
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}
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void
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am18xx_psc_attach(device_t parent, device_t self, void *aux)
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{
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struct am18xx_psc_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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bus_addr_t addr;
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bus_size_t size;
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const struct am18xx_psc_config *config;
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sc->sc_bst = faa->faa_bst;
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/* map PSC control registers */
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
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aprint_error(": couldn't map registers\n");
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return;
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}
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/* initialize clock domain */
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sc->sc_clkdom.name = device_xname(self);
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sc->sc_clkdom.funcs = &am18xx_psc_clk_funcs;
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sc->sc_clkdom.priv = sc;
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/* wire up different clock tables depending on if it is psc0 or psc1 */
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config = of_compatible_lookup(phandle, compat_data)->data;
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sc->sc_clks = config->clks;
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sc->sc_clknum = config->clknum;
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/* get parent clock, then attach the clk gate */
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for (int i = 0; i < sc->sc_clknum; i++) {
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/* skip unused clock gates */
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if (sc->sc_clks[i].clk_base.name == NULL)
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continue;
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struct clk *parent_clk =
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fdtbus_clock_get(phandle, sc->sc_clks[i].u.clk_parent_name);
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if (parent_clk == NULL) {
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aprint_error(": couldn't get clock parent for %s\n",
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sc->sc_clks[i].clk_base.name);
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return;
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}
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sc->sc_clks[i].u.clk_parent = parent_clk;
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sc->sc_clks[i].clk_base.domain = &sc->sc_clkdom;
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clk_attach(&sc->sc_clks[i].clk_base);
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}
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/* register it int he fdt subsystem */
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fdtbus_register_clock_controller(self, phandle,
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&am18xx_psc_clk_fdt_funcs);
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aprint_normal("\n");
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}
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‎sys/arch/arm/ti/files.ti‎

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@@ -71,6 +71,10 @@ device ticompclk
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attach ticompclk at fdt with ti_comp_clock
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file arch/arm/ti/ti_comp_clock.c ti_comp_clock
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device am18xxpsc: fdt_clock
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attach am18xxpsc at fdt
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file arch/arm/ti/am18xx_psc.c am18xxpsc
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# UART
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attach com at fdt with ti_com: ti_prcm
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file arch/arm/ti/ti_com.c ti_com needs-flag

‎sys/arch/evbarm/conf/GENERIC_V5‎

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@@ -72,6 +72,7 @@ imx23apbdma* at fdt? pass 1 # NXP i.MX23 DMA controller
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# Clock Controllers
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imx23clkctrl* at fdt? pass 1 # i.MX23 clock controller
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am18xxpsc* at fdt? pass 3 # TI AM18XX power&sleep controller
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# general FDT devices
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fclock* at fdt? pass 1

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