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evbarm/am18: add timer
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‎sys/arch/arm/ti/am18_timer.c‎

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/* $NetBSD $ */
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/*-
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* Copyright (c) 2025 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Yuri Honegger.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Timer Interrupts for the TI AM18XX SOC
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*/
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#include <sys/param.h>
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#include <sys/cdefs.h>
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#include <sys/device.h>
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#include <dev/fdt/fdtvar.h>
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#include <arm/fdt/arm_fdtvar.h>
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struct am18_timer_softc {
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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};
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static int am18_timer_match(device_t, cfdata_t, void *);
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static void am18_timer_attach(device_t, device_t, void *);
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static void am18_timer_cpu_initclocks(void);
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static int am18_timer_irq(void *);
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static struct am18_timer_softc *timer_sc;
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CFATTACH_DECL_NEW(am18timer, sizeof(struct am18_timer_softc),
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am18_timer_match, am18_timer_attach, NULL, NULL);
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#define AM18_TIMER_TIM12 0x10
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#define AM18_TIMER_TIM34 0x14
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#define AM18_TIMER_PRD12 0x18
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#define AM18_TIMER_PRD34 0x1C
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#define AM18_TIMER_TCR 0x20
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#define AM18_TIMER_TGCR 0x24
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#define AM18_TIMER_TCR_ENAMODE12_CONTINUOUS 0x80
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#define AM18_TIMER_TGCR_TIMMODE32_UNCHAINED 0x4
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#define AM18_TIMER_TGCR_TIM12EN 0x1
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#define TIMER_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, reg)
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#define TIMER_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, reg, val)
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static const struct device_compatible_entry compat_data[] = {
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{ .compat = "ti,da830-timer" },
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DEVICE_COMPAT_EOL
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};
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static void
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am18_timer_cpu_initclocks(void)
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{
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struct am18_timer_softc *sc = timer_sc;
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uint32_t timer_interval = 24000000/hz;
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/* disable counter to allow changing mode */
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TIMER_WRITE(sc, AM18_TIMER_TCR, 0);
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/* set mode to 32-bit unchained */
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TIMER_WRITE(sc, AM18_TIMER_TGCR, AM18_TIMER_TGCR_TIMMODE32_UNCHAINED |
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AM18_TIMER_TGCR_TIM12EN);
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/* start counting from zero */
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TIMER_WRITE(sc, AM18_TIMER_TIM12, 0);
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TIMER_WRITE(sc, AM18_TIMER_TIM34, 0);
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/* load period registers with maximum period */
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TIMER_WRITE(sc, AM18_TIMER_PRD12, timer_interval);
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TIMER_WRITE(sc, AM18_TIMER_PRD34, 0);
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/* enable timer */
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TIMER_WRITE(sc, AM18_TIMER_TCR, AM18_TIMER_TCR_ENAMODE12_CONTINUOUS);
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}
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int
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am18_timer_irq(void *frame)
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{
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hardclock(frame);
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return 1;
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}
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int
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am18_timer_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_compatible_match(faa->faa_phandle, compat_data);
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}
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void
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am18_timer_attach(device_t parent, device_t self, void *aux)
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{
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struct am18_timer_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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bus_addr_t addr;
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bus_size_t size;
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char intrstr[128];
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sc->sc_bst = faa->faa_bst;
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timer_sc = sc;
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if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
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aprint_error(": couldn't get registers\n");
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return;
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}
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if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
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aprint_error(": couldn't map registers\n");
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return;
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}
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/* establish interrupt */
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if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
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aprint_error(": failed to decode interrupt\n");
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return;
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}
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void *ih = fdtbus_intr_establish_xname(phandle, 0, IPL_CLOCK, 0,
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am18_timer_irq, NULL,
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device_xname(self));
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if (ih == NULL) {
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aprint_error_dev(self, "couldn't install timer interrupt\n");
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return;
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}
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arm_fdt_timer_register(am18_timer_cpu_initclocks);
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aprint_normal(": timer on %s\n", intrstr);
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}
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‎sys/arch/arm/ti/files.ti‎

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@@ -80,6 +80,10 @@ device omaptimer
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attach omaptimer at fdt
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file arch/arm/ti/ti_omaptimer.c omaptimer
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device am18timer
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attach am18timer at fdt
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file arch/arm/ti/am18_timer.c am18timer
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# GPIO
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device tigpio: fdt_gpio, gpiobus
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attach tigpio at fdt with ti_gpio

‎sys/arch/evbarm/conf/GENERIC_V5‎

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# Timers
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imx23timrot* at fdt? pass 2 # imx23 timer
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am18timer* at fdt? pass 2 # am18 timer
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# DMA controller
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imx23apbdma* at fdt? pass 1 # NXP i.MX23 DMA controller

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