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evbarm/am18xx: add async-clk clkgate driver
1 parent e847e2a commit b047e16

3 files changed

Lines changed: 200 additions & 2 deletions

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‎sys/arch/arm/ti/am18xx_aclk.c‎

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/* $NetBSD $ */
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/*-
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* Copyright (c) 2026 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Yuri Honegger.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Drivers for the async clock gates in the syscfg block of the TI AM1808.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cdefs.h>
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#include <sys/device.h>
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#include <dev/clk/clk_backend.h>
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#include <dev/fdt/fdtvar.h>
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#include <dev/fdt/syscon.h>
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#include <arm/fdt/arm_fdtvar.h>
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struct am18xx_aclk_config {
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struct clk *clk; /* double wrap clk because the config must be const */
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uint32_t mask;
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};
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struct am18xx_aclk_softc {
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struct clk_domain sc_clkdom;
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const struct am18xx_aclk_config *sc_config;
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struct clk *sc_parent_clk;
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};
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static int am18xx_aclk_match(device_t, cfdata_t, void *);
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static void am18xx_aclk_attach(device_t, device_t, void *);
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static struct clk * am18xx_aclk_decode(device_t, int, const void *, size_t);
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static struct clk * am18xx_aclk_clk_get(void *, const char *);
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static u_int am18xx_aclk_clk_get_rate(void *, struct clk *);
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static struct clk * am18xx_aclk_clk_get_parent(void *, struct clk *);
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CFATTACH_DECL_NEW(am18xxaclk, sizeof(struct am18xx_aclk_softc),
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am18xx_aclk_match, am18xx_aclk_attach, NULL, NULL);
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#define AM18XX_ACLK_CFGCHIP3 0xC
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#define AM18XX_ACLK_CFGCHIP3_ASYNC3_CLKSRC __BIT(4)
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#define AM18XX_ACLK_CFGCHIP3_ASYNC1_CLKSRC __BIT(2)
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static struct clk am18xx_aclk_async1_clk = {
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.name = "async1",
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.flags = 0
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};
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static struct clk am18xx_aclk_async3_clk = {
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.name = "async3",
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.flags = 0
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};
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static const struct am18xx_aclk_config am18xx_aclk_async1_config = {
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.clk = &am18xx_aclk_async1_clk,
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.mask = AM18XX_ACLK_CFGCHIP3_ASYNC1_CLKSRC,
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};
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static const struct am18xx_aclk_config am18xx_aclk_async3_config = {
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.clk = &am18xx_aclk_async3_clk,
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.mask = AM18XX_ACLK_CFGCHIP3_ASYNC3_CLKSRC,
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};
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static const struct fdtbus_clock_controller_func am18xx_aclk_clk_fdt_funcs = {
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.decode = am18xx_aclk_decode,
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};
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static const struct clk_funcs am18xx_aclk_clk_funcs = {
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.get = am18xx_aclk_clk_get,
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.get_rate = am18xx_aclk_clk_get_rate,
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.get_parent = am18xx_aclk_clk_get_parent,
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};
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static const struct device_compatible_entry compat_data[] = {
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{ .compat = "ti,da850-async1-clksrc",
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.data = &am18xx_aclk_async1_config },
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{ .compat = "ti,da850-async3-clksrc",
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.data = &am18xx_aclk_async3_config },
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DEVICE_COMPAT_EOL
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};
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static struct clk *
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am18xx_aclk_clk_get(void *priv, const char *name)
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{
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struct am18xx_aclk_softc * const sc = priv;
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if (strcmp(sc->sc_config->clk->name, name) == 0) {
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return sc->sc_config->clk;
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}
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return NULL;
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}
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static u_int
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am18xx_aclk_clk_get_rate(void *priv, struct clk *clkp)
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{
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struct am18xx_aclk_softc * const sc = priv;
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return clk_get_rate(sc->sc_parent_clk);
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}
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static struct clk *
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am18xx_aclk_clk_get_parent(void *priv, struct clk *clkp)
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{
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struct am18xx_aclk_softc * const sc = priv;
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return sc->sc_parent_clk;
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}
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static struct clk *
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am18xx_aclk_decode(device_t dev, int cc_phandle, const void *data, size_t len)
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{
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struct am18xx_aclk_softc * const sc = device_private(dev);
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return sc->sc_config->clk;
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}
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int
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am18xx_aclk_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct fdt_attach_args * const faa = aux;
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return of_compatible_match(faa->faa_phandle, compat_data);
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}
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void
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am18xx_aclk_attach(device_t parent, device_t self, void *aux)
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{
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struct am18xx_aclk_softc * const sc = device_private(self);
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struct fdt_attach_args * const faa = aux;
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const int phandle = faa->faa_phandle;
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sc->sc_config = of_compatible_lookup(phandle, compat_data)->data;
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/* ensure we have a clock parent */
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sc->sc_parent_clk = fdtbus_clock_get_index(phandle, 0);
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if (sc->sc_parent_clk == NULL) {
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aprint_error(": couldn't get parent clock");
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return;
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}
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/* ensure clock gate bits are as expected */
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struct syscon *syscon = fdtbus_syscon_lookup(OF_parent(phandle));
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if (syscon == NULL) {
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aprint_error(": couldn't get syscon registers\n");
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return;
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}
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syscon_lock(syscon);
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uint32_t cfgchip_reg3 = syscon_read_4(syscon, AM18XX_ACLK_CFGCHIP3);
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syscon_unlock(syscon);
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if ((cfgchip_reg3 & sc->sc_config->mask) != 0) {
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aprint_error(": unexpected clock gate bits\n");
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return;
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}
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/* attach a clock controller */
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sc->sc_clkdom.name = device_xname(self);
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sc->sc_clkdom.funcs = &am18xx_aclk_clk_funcs;
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sc->sc_clkdom.priv = sc;
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sc->sc_config->clk->domain = &sc->sc_clkdom;
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clk_attach(sc->sc_config->clk);
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fdtbus_register_clock_controller(self, phandle, &am18xx_aclk_clk_fdt_funcs);
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aprint_normal("\n");
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}

‎sys/arch/arm/ti/files.ti‎

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@@ -79,6 +79,10 @@ device am18xxpllc: fdt_clock
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attach am18xxpllc at fdt
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file arch/arm/ti/am18xx_pllc.c am18xxpllc
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device am18xxaclk: fdt_clock
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attach am18xxaclk at fdt
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file arch/arm/ti/am18xx_aclk.c am18xxaclk
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# UART
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attach com at fdt with ti_com: ti_prcm
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file arch/arm/ti/ti_com.c ti_com needs-flag

‎sys/arch/evbarm/conf/GENERIC_V5‎

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@@ -73,6 +73,7 @@ imx23apbdma* at fdt? pass 1 # NXP i.MX23 DMA controller
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# Clock Controllers
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imx23clkctrl* at fdt? pass 1 # i.MX23 clock controller
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am18xxpllc* at fdt? pass 2 # TI AM18XX pll controller
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am18xxaclk* at fdt? pass 3 # TI AM18XX async-clk clkgates
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am18xxpsc* at fdt? pass 4 # TI AM18XX power&sleep controller
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# System Controller
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gpio* at gpiobus?
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# UART
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com* at fdt? pass 4 # UART
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plcom* at fdt? pass 4 # ARM PL011 UART
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com* at fdt? pass 5 # UART
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plcom* at fdt? pass 5 # ARM PL011 UART
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# Various
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imx23digctl* at fdt? pass 1 # i.MX23 digctl block

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