fpga: m10bmc-sec: support power on image

This patch supports that selects image to be configured of the FPGA
during next boot.

Author: Figo-zhang

Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-secure

@@ -59,3 +59,21 @@ Contact:	Russ Weight <russell.h.weight@intel.com>
 Description:	Read only. Returns number of times the secure update
 		staging area has been flashed.
 		Format: "%u".
+
+What:
+/sys/bus/platform/devices/n3000bmc-secure.*.auto/available_power_on_images
+Date:		January 2021
+KernelVersion:  5.12
+Contact:	Tianfei zhang <tianfei.zhang@intel.com>
+Description:	Read-only. This file returns a space separated list of
+		key words that may be written into the power_on_image file
+		described below. These keywords decribe an default image on
+		next boot-up.
+
+What:           /sys/bus/platform/devices/n3000bmc-secure.*.auto/power_on_image
+Date:		January 2021
+KernelVersion:  5.12
+Contact:	Tianfei zhang <tianfei.zhang@intel.com>
+Description:	Read/Write. A key word may be written to this file to
+		trigger the image which will be configured of the FPGA during next boot.
+		Read this entry will return which image has been configured.

drivers/fpga/fpga-sec-mgr.c

@@ -23,8 +23,6 @@ struct fpga_sec_mgr_devres {
 
 #define WRITE_BLOCK_SIZE 0x4000	/* Update remaining_size every 0x4000 bytes */
 
-#define to_sec_mgr(d) container_of(d, struct fpga_sec_mgr, dev)
-
 static void update_progress(struct fpga_sec_mgr *smgr,
 			    enum fpga_sec_prog new_progress)
 {

drivers/fpga/intel-m10-bmc-secure.c

@@ -20,6 +20,8 @@ struct m10bmc_sec {
 	enum fpga_sec_type type;
 };
 
+static const struct image_load *curr_poc;
+
 /* Root Entry Hash (REH) support */
 #define REH_SHA256_SIZE		32
 #define REH_SHA384_SIZE		48
@@ -150,6 +152,177 @@ static ssize_t flash_count_show(struct device *dev,
 }
 static DEVICE_ATTR_RO(flash_count);
 
+static ssize_t
+available_power_on_images_show(struct device *dev,
+			       struct device_attribute *attr, char *buf)
+{
+	struct fpga_sec_mgr *smgr = to_sec_mgr(dev);
+	const struct image_load *hndlr;
+	ssize_t count = 0;
+
+	for (hndlr = smgr->sops->power_on_image; hndlr->name; hndlr++) {
+		count += scnprintf(buf + count, PAGE_SIZE - count,
+				   "%s ", hndlr->name);
+	}
+
+	buf[count - 1] = '\n';
+
+	return count;
+}
+static DEVICE_ATTR_RO(available_power_on_images);
+
+static ssize_t
+power_on_image_show(struct device *dev,
+		    struct device_attribute *attr, char *buf)
+{
+	ssize_t count = 0;
+
+	if (!curr_poc)
+		return -EINVAL;
+
+	count = scnprintf(buf + count, PAGE_SIZE - count,
+			  "%s ", curr_poc->name);
+	buf[count - 1] = '\n';
+
+	return count;
+}
+
+static ssize_t
+power_on_image_store(struct device *dev,
+		     struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct fpga_sec_mgr *smgr = to_sec_mgr(dev);
+	const struct image_load *hndlr;
+	int ret = -EINVAL;
+
+	for (hndlr = smgr->sops->power_on_image; hndlr->name; hndlr++) {
+		if (sysfs_streq(buf, hndlr->name)) {
+			ret = hndlr->load_image(smgr);
+			curr_poc = hndlr;
+			break;
+		}
+	}
+
+	return ret ? : count;
+}
+static DEVICE_ATTR_RW(power_on_image);
+
+static int pmci_sec_power_on_image(struct fpga_sec_mgr *smgr, unsigned char boot_image)
+{
+	struct m10bmc_sec *sec = smgr->priv;
+	u32 poc = 0;
+	int ret;
+
+	if (boot_image > FPGA_POC_FACTORY_U2) {
+		dev_err(sec->dev, "%s invalid boot image = %d\n", __func__, boot_image);
+		return -EINVAL;
+	}
+
+	switch (boot_image) {
+	case FPGA_POC_USER_IMAGE_1:
+		poc |= FIELD_PREP(PMCI_USER_IMAGE_PAGE, POC_USER_IMAGE_1);
+		break;
+	case FPGA_POC_USER_IMAGE_2:
+		poc |= FIELD_PREP(PMCI_USER_IMAGE_PAGE, POC_USER_IMAGE_2);
+		break;
+	case FPGA_POC_FACTORY_U1:
+		poc |= PMCI_FACTORY_IMAGE_PAGE | FIELD_PREP(PMCI_USER_IMAGE_PAGE,
+							    POC_USER_IMAGE_1);
+		break;
+	case FPGA_POC_FACTORY_U2:
+		poc |= PMCI_FACTORY_IMAGE_PAGE | FIELD_PREP(PMCI_USER_IMAGE_PAGE,
+							    POC_USER_IMAGE_2);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = m10bmc_sys_update_bits(sec->m10bmc,
+				     m10bmc_base(sec->m10bmc) + PMCI_M10BMC_FPGA_POC,
+				     PMCI_FPGA_POC |
+				     PMCI_USER_IMAGE_PAGE |
+				     PMCI_FACTORY_IMAGE_PAGE,
+				     poc | PMCI_FPGA_POC);
+	if (ret)
+		return ret;
+
+	ret = regmap_read_poll_timeout(sec->m10bmc->regmap,
+				       m10bmc_base(sec->m10bmc) + PMCI_M10BMC_FPGA_POC,
+				       poc,
+				       (!(poc & PMCI_FPGA_POC)),
+				       NIOS_HANDSHAKE_INTERVAL_US,
+				       NIOS_HANDSHAKE_TIMEOUT_US);
+	if (ret || (FIELD_GET(PMCI_NIOS_STATUS, poc) != NIOS_STATUS_SUCCESS))
+		return -EIO;
+
+	return 0;
+}
+
+static int pmci_sec_power_on_image_0(struct fpga_sec_mgr *smgr)
+{
+	return pmci_sec_power_on_image(smgr, FPGA_POC_USER_IMAGE_1);
+}
+
+static int pmci_sec_power_on_image_1(struct fpga_sec_mgr *smgr)
+{
+	return pmci_sec_power_on_image(smgr, FPGA_POC_USER_IMAGE_2);
+}
+
+static int pmci_sec_power_on_image_2(struct fpga_sec_mgr *smgr)
+{
+	return pmci_sec_power_on_image(smgr, FPGA_POC_FACTORY_U1);
+}
+
+static int pmci_sec_power_on_image_3(struct fpga_sec_mgr *smgr)
+{
+	return pmci_sec_power_on_image(smgr, FPGA_POC_FACTORY_U2);
+}
+
+static struct image_load pmci_power_on_image_hndlrs[] = {
+	{
+		.name = "fpga_user1",
+		.load_image = pmci_sec_power_on_image_0,
+	},
+	{
+		.name = "fpga_user2",
+		.load_image = pmci_sec_power_on_image_1,
+	},
+	{
+		.name = "fpga_factory",
+		.load_image = pmci_sec_power_on_image_2,
+	},
+	{
+		.name = "fpga_factory_option1",
+		.load_image = pmci_sec_power_on_image_3,
+	},
+	{}
+};
+
+static umode_t
+m10bmc_image_visible(struct kobject *kobj,
+		     struct attribute *attr, int n)
+{
+	struct fpga_sec_mgr *smgr = to_sec_mgr(kobj_to_dev(kobj));
+	struct m10bmc_sec *sec = smgr->priv;
+	enum fpga_sec_type type = sec->m10bmc->type;
+
+	if (type == PMCI_SEC)
+		return attr->mode;
+
+	return 0;
+}
+
+static struct attribute *m10bmc_image_attrs[] = {
+	&dev_attr_power_on_image.attr,
+	&dev_attr_available_power_on_images.attr,
+	NULL,
+};
+
+static struct attribute_group m10bmc_image_attr_group = {
+	.attrs = m10bmc_image_attrs,
+	.is_visible = m10bmc_image_visible,
+};
+
 static struct attribute *m10bmc_security_attrs[] = {
 	&dev_attr_flash_count.attr,
 	&dev_attr_bmc_root_entry_hash.attr,
@@ -168,6 +341,7 @@ static struct attribute_group m10bmc_security_attr_group = {
 
 static const struct attribute_group *m10bmc_sec_attr_groups[] = {
 	&m10bmc_security_attr_group,
+	&m10bmc_image_attr_group,
 	NULL,
 };
 
@@ -922,6 +1096,7 @@ m10bmc_sops_create(struct device *dev, enum fpga_sec_type type)
 	if (type == PMCI_SEC) {
 		sops->write_blk = pmci_sec_write_blk;
 		sops->image_load = pmci_image_load_hndlrs;
+		sops->power_on_image = pmci_power_on_image_hndlrs;
 	} else {
 		sops->write_blk = m10bmc_sec_write_blk;
 	}

include/linux/fpga/fpga-sec-mgr.h

@@ -64,6 +64,10 @@ struct image_load {
  *			    { } member terminated. These structures describe
  *			    image load triggers for BMC, FPGA, or firmware
  *			    images.
+ * @power_on_image:         pointer to array of image_load structures,
+ *			    { } member terminated. These structures describe
+ *			    image setting which be configured of the FPGA during
+ *			    next boot.
  */
 struct fpga_sec_mgr_ops {
 	enum fpga_sec_err (*prepare)(struct fpga_sec_mgr *smgr);
@@ -74,6 +78,7 @@ struct fpga_sec_mgr_ops {
 	void (*cleanup)(struct fpga_sec_mgr *smgr);
 	u64 (*get_hw_errinfo)(struct fpga_sec_mgr *smgr);
 	struct image_load *image_load;	/* terminated with { } member */
+	struct image_load *power_on_image;	/* terminated with { } member */
 };
 
 /* Update progress codes */
@@ -105,6 +110,8 @@ struct fpga_sec_mgr {
 	void *priv;
 };
 
+#define to_sec_mgr(d) container_of(d, struct fpga_sec_mgr, dev)
+
 struct fpga_sec_mgr *
 fpga_sec_mgr_create(struct device *dev, const char *name,
 		    const struct fpga_sec_mgr_ops *sops, void *priv);

include/linux/mfd/intel-m10-bmc.h

@@ -201,6 +201,18 @@ enum m10bmc_type {
 #define PMCI_MAX10_REBOOT_REQ BIT(0)
 #define PMCI_MAX10_REBOOT_PAGE BIT(1)
 
+#define PMCI_M10BMC_FPGA_POC 0xb0
+#define PMCI_FPGA_POC BIT(0)
+#define PMCI_NIOS_REQ_CLEAR BIT(1)
+#define PMCI_NIOS_STATUS GENMASK(5, 4)
+#define NIOS_STATUS_IDLE 0
+#define NIOS_STATUS_SUCCESS 1
+#define NIOS_STATUS_FAIL 2
+#define PMCI_USER_IMAGE_PAGE GENMASK(10, 8)
+#define POC_USER_IMAGE_1  1
+#define POC_USER_IMAGE_2  2
+#define PMCI_FACTORY_IMAGE_PAGE BIT(31)
+
 #define PMCI_M10BMC_FPGA_RECONF 0xb8
 #define PMCI_FPGA_RECONF_PAGE  GENMASK(22, 20)
 #define PMCI_FPGA_RP_LOAD      BIT(23)
@@ -209,6 +221,13 @@ enum m10bmc_type {
 #define doorbell_reg(m10bmc) ((m10bmc)->csr->doorbell)
 #define auth_result_reg(m10bmc) ((m10bmc)->csr->auth_result)
 
+enum m10bmc_fpga_poc {
+	FPGA_POC_USER_IMAGE_1,
+	FPGA_POC_USER_IMAGE_2,
+	FPGA_POC_FACTORY_U1,
+	FPGA_POC_FACTORY_U2
+};
+
 enum m10bmc_fw_state {
 	M10BMC_FW_STATE_NORMAL,
 	M10BMC_FW_STATE_SEC_UPDATE,