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mmindpalmer-dabbelt
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riscv: drop some idefs from CMO initialization
Wrapping things in #ifdefs makes the code harder to read while we also have IS_ENABLED() macros to do this in regular code and the extension detection is not _that_ runtime critical. So define a stub for riscv_noncoherent_supported() in the non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to us IS_ENABLED. Suggested-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20220905111027.2463297-3-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
1 parent e47bddc commit f055268

3 files changed

Lines changed: 14 additions & 17 deletions

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arch/riscv/errata/thead/errata.c

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
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static bool errata_probe_cmo(unsigned int stage,
3131
unsigned long arch_id, unsigned long impid)
3232
{
33-
#ifdef CONFIG_ERRATA_THEAD_CMO
33+
if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
34+
return false;
35+
3436
if (arch_id != 0 || impid != 0)
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return false;
3638

@@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
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4042
riscv_noncoherent_supported();
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return true;
42-
#else
43-
return false;
44-
#endif
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}
4645

4746
static u32 thead_errata_probe(unsigned int stage,

arch/riscv/include/asm/cacheflush.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
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#ifdef CONFIG_RISCV_DMA_NONCOHERENT
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void riscv_noncoherent_supported(void);
53+
#else
54+
static inline void riscv_noncoherent_supported(void) {}
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#endif
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/*

arch/riscv/kernel/cpufeature.c

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
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static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
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{
267-
#ifdef CONFIG_RISCV_ISA_ZICBOM
268-
switch (stage) {
269-
case RISCV_ALTERNATIVES_EARLY_BOOT:
267+
if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
268+
return false;
269+
270+
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
271+
return false;
272+
273+
if (!riscv_isa_extension_available(NULL, ZICBOM))
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return false;
271-
default:
272-
if (riscv_isa_extension_available(NULL, ZICBOM)) {
273-
riscv_noncoherent_supported();
274-
return true;
275-
} else {
276-
return false;
277-
}
278-
}
279-
#endif
280275

281-
return false;
276+
riscv_noncoherent_supported();
277+
return true;
282278
}
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/*

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