Skip to content

Commit c036201

Browse files
committed
Rename bitfield "struct"s to "bits"
Bits and bytes have better naming parity between each other
1 parent b857209 commit c036201

1 file changed

Lines changed: 15 additions & 15 deletions

File tree

XRPLib/imu.py

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,9 @@ def __init__(self, scl_pin: int, sda_pin: int, addr):
4545
self.reg_ctrl1_xl_byte = bytearray(1)
4646
self.reg_ctrl2_g_byte = bytearray(1)
4747
self.reg_ctrl3_c_byte = bytearray(1)
48-
self.reg_ctrl1_xl_struct = struct(addressof(self.reg_ctrl1_xl_byte), LSM_REG_LAYOUT_CTRL1_XL)
49-
self.reg_ctrl2_g_struct = struct(addressof(self.reg_ctrl2_g_byte), LSM_REG_LAYOUT_CTRL2_G)
50-
self.reg_ctrl3_c_struct = struct(addressof(self.reg_ctrl3_c_byte), LSM_REG_LAYOUT_CTRL3_C)
48+
self.reg_ctrl1_xl_bits = struct(addressof(self.reg_ctrl1_xl_byte), LSM_REG_LAYOUT_CTRL1_XL)
49+
self.reg_ctrl2_g_bits = struct(addressof(self.reg_ctrl2_g_byte), LSM_REG_LAYOUT_CTRL2_G)
50+
self.reg_ctrl3_c_bits = struct(addressof(self.reg_ctrl3_c_byte), LSM_REG_LAYOUT_CTRL3_C)
5151

5252
# Check if the IMU is connected
5353
if not self.is_connected():
@@ -127,8 +127,8 @@ def reset(self, wait_for_reset = True, wait_timeout_ms = 100):
127127
"""
128128
# Set BOOT and SW_RESET bits
129129
self.reg_ctrl3_c_byte = self._getreg(LSM_REG_CTRL3_C)
130-
self.reg_ctrl3_c_struct.BOOT = 1
131-
self.reg_ctrl3_c_struct.SW_RESET = 1
130+
self.reg_ctrl3_c_bits.BOOT = 1
131+
self.reg_ctrl3_c_bits.SW_RESET = 1
132132
self._setreg(LSM_REG_CTRL3_C, self.reg_ctrl3_c_byte)
133133

134134
# Wait for reset to complete, if requested
@@ -150,15 +150,15 @@ def _set_bdu(self, bdu = True):
150150
Sets Block Data Update bit
151151
"""
152152
self.reg_ctrl3_c_byte = self._getreg(LSM_REG_CTRL3_C)
153-
self.reg_ctrl3_c_struct.BDU = bdu
153+
self.reg_ctrl3_c_bits.BDU = bdu
154154
self._setreg(LSM_REG_CTRL3_C, self.reg_ctrl3_c_byte)
155155

156156
def _set_if_inc(self, if_inc = True):
157157
"""
158158
Sets InterFace INCrement bit
159159
"""
160160
self.reg_ctrl3_c_byte = self._getreg(LSM_REG_CTRL3_C)
161-
self.reg_ctrl3_c_struct.IF_INC = if_inc
161+
self.reg_ctrl3_c_bits.IF_INC = if_inc
162162
self._setreg(LSM_REG_CTRL3_C, self.reg_ctrl3_c_byte)
163163

164164
def _mg(self, reg):
@@ -353,11 +353,11 @@ def acc_scale(self, value=None):
353353
# Check if the provided value is in the dictionary
354354
if value not in LSM_ACCEL_FS:
355355
# Return string representation of this value
356-
index = list(LSM_ACCEL_FS.values()).index(self.reg_ctrl1_xl_struct.FS_XL)
356+
index = list(LSM_ACCEL_FS.values()).index(self.reg_ctrl1_xl_bits.FS_XL)
357357
return list(LSM_ACCEL_FS.keys())[index]
358358
else:
359359
# Set value as requested
360-
self.reg_ctrl1_xl_struct.FS_XL = LSM_ACCEL_FS[value]
360+
self.reg_ctrl1_xl_bits.FS_XL = LSM_ACCEL_FS[value]
361361
self._setreg(LSM_REG_CTRL1_XL, self.reg_ctrl1_xl_byte)
362362

363363
def gyro_scale(self, value=None):
@@ -371,11 +371,11 @@ def gyro_scale(self, value=None):
371371
# Check if the provided value is in the dictionary
372372
if value not in LSM_GYRO_FS:
373373
# Return string representation of this value
374-
index = list(LSM_GYRO_FS.values()).index(self.reg_ctrl2_g_struct.FS_G)
374+
index = list(LSM_GYRO_FS.values()).index(self.reg_ctrl2_g_bits.FS_G)
375375
return list(LSM_GYRO_FS.keys())[index]
376376
else:
377377
# Set value as requested
378-
self.reg_ctrl2_g_struct.FS_G = LSM_GYRO_FS[value]
378+
self.reg_ctrl2_g_bits.FS_G = LSM_GYRO_FS[value]
379379
self._setreg(LSM_REG_CTRL2_G, self.reg_ctrl2_g_byte)
380380

381381
def acc_rate(self, value=None):
@@ -389,11 +389,11 @@ def acc_rate(self, value=None):
389389
# Check if the provided value is in the dictionary
390390
if value not in LSM_ODR:
391391
# Return string representation of this value
392-
index = list(LSM_ODR.values()).index(self.reg_ctrl1_xl_struct.ODR_XL)
392+
index = list(LSM_ODR.values()).index(self.reg_ctrl1_xl_bits.ODR_XL)
393393
return list(LSM_ODR.keys())[index]
394394
else:
395395
# Set value as requested
396-
self.reg_ctrl1_xl_struct.ODR_XL = LSM_ODR[value]
396+
self.reg_ctrl1_xl_bits.ODR_XL = LSM_ODR[value]
397397
self._setreg(LSM_REG_CTRL1_XL, self.reg_ctrl1_xl_byte)
398398

399399
def gyro_rate(self, value=None):
@@ -407,11 +407,11 @@ def gyro_rate(self, value=None):
407407
# Check if the provided value is in the dictionary
408408
if value not in LSM_ODR:
409409
# Return string representation of this value
410-
index = list(LSM_ODR.values()).index(self.reg_ctrl1_xl_struct.ODR_G)
410+
index = list(LSM_ODR.values()).index(self.reg_ctrl1_xl_bits.ODR_G)
411411
return list(LSM_ODR.keys())[index]
412412
else:
413413
# Set value as requested
414-
self.reg_ctrl2_g_struct.ODR_G = LSM_ODR[value]
414+
self.reg_ctrl2_g_bits.ODR_G = LSM_ODR[value]
415415
self._setreg(LSM_REG_CTRL2_G, self.reg_ctrl2_g_byte)
416416

417417
# Update timer frequency

0 commit comments

Comments
 (0)