diff --git a/MODULE.bazel b/MODULE.bazel
index 31d81f29..ea2f7fe7 100644
--- a/MODULE.bazel
+++ b/MODULE.bazel
@@ -30,6 +30,11 @@ git_override(
         "//third_party/pigweed:integration_tests_armv7m.patch",
         # Stage .bin alongside .elf in system_image_test runfiles.
         "//third_party/pigweed:system_image_test_bin_runfiles.patch",
+        # syscall_defs is pure type defs that the kernel always depends on, but
+        # upstream gates it incompatible unless userspace_build is enabled. That
+        # breaks every userspace=False system_image (i2c/i3c/smc/...). Drop the
+        # gate so kernel-only images build again.
+        "//third_party/pigweed:syscall_defs_always_compatible.patch",
     ],
     remote = "https://pigweed.googlesource.com/pigweed/pigweed",
 )
diff --git a/MODULE.bazel.lock b/MODULE.bazel.lock
index 23e5784e..7835b519 100644
--- a/MODULE.bazel.lock
+++ b/MODULE.bazel.lock
@@ -2754,8 +2754,8 @@
         "bzlTransitiveDigest": "pJGPYIkbVrEoiR6YLuU72xx4PvVY4idccFMOWJLmQ+4=",
         "usagesDigest": "/Nz9QH+EBlDXoVXWiAEH8owsAo1cu+GkXjlRdolG7Sk=",
         "recordedFileInputs": {
-          "@@//third_party/crates_io/Cargo.lock": "eac2c7966bf4d855547714d841b236d4a4c245118815682e720a48e9035635fb",
-          "@@//third_party/crates_io/Cargo.toml": "5afe4e14be9b26c3eeb6c90ddf6f80426d5bd7af9d3407c83a7f00d6669fbaee",
+          "@@//third_party/crates_io/Cargo.lock": "b719af8ef17c9c4abccdd30ae60906378a85d9ea2dd89422c1e8af2980633f1d",
+          "@@//third_party/crates_io/Cargo.toml": "e21c3f81434a026b87ca715626f3b6c886282521be37332cd0fea4e554810ebe",
           "@@caliptra_deps+//crates_io/embedded/Cargo.lock": "d6c0101f48da22f2bc2d339f358de79bad3dd03218c6db29a14099b9f7757691",
           "@@caliptra_deps+//crates_io/embedded/Cargo.toml": "8f9f4ed2721db13476b12fdac045dac2142b38f189a8abb5f4c446dc0c6ac3dd",
           "@@caliptra_deps+//crates_io/host/Cargo.lock": "ae555b01424917ec61d892c15d7a66af88c2f10be4e0e7b0bc2357b702883b89",
@@ -2781,9 +2781,9 @@
             "repoRuleId": "@@rules_rust+//crate_universe:extensions.bzl%_generate_repo",
             "attributes": {
               "contents": {
-                "BUILD.bazel": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\npackage(default_visibility = [\"//visibility:public\"])\n\nexports_files(\n    [\n        \"cargo-bazel.json\",\n        \"crates.bzl\",\n        \"defs.bzl\",\n    ] + glob(\n        allow_empty = True,\n        include = [\"*.bazel\"],\n    ),\n)\n\nfilegroup(\n    name = \"srcs\",\n    srcs = glob(\n        allow_empty = True,\n        include = [\n            \"*.bazel\",\n            \"*.bzl\",\n        ],\n    ),\n)\n\n# Workspace Member Dependencies\nalias(\n    name = \"aes-0.8.4\",\n    actual = \"@rust_crates__aes-0.8.4//:aes\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes\",\n    actual = \"@rust_crates__aes-0.8.4//:aes\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes-gcm-0.10.3\",\n    actual = \"@rust_crates__aes-gcm-0.10.3//:aes_gcm\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes-gcm\",\n    actual = \"@rust_crates__aes-gcm-0.10.3//:aes_gcm\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aligned-0.4.3\",\n    actual = \"@rust_crates__aligned-0.4.3//:aligned\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aligned\",\n    actual = \"@rust_crates__aligned-0.4.3//:aligned\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"anyhow-1.0.102\",\n    actual = \"@rust_crates__anyhow-1.0.102//:anyhow\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"anyhow\",\n    actual = \"@rust_crates__anyhow-1.0.102//:anyhow\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-0.14.0\",\n    actual = \"@rust_crates__bitfield-0.14.0//:bitfield\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield\",\n    actual = \"@rust_crates__bitfield-0.14.0//:bitfield\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-struct-0.11.0\",\n    actual = \"@rust_crates__bitfield-struct-0.11.0//:bitfield_struct\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-struct\",\n    actual = \"@rust_crates__bitfield-struct-0.11.0//:bitfield_struct\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitflags-2.12.1\",\n    actual = \"@rust_crates__bitflags-2.12.1//:bitflags\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitflags\",\n    actual = \"@rust_crates__bitflags-2.12.1//:bitflags\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"byteorder-1.5.0\",\n    actual = \"@rust_crates__byteorder-1.5.0//:byteorder\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"byteorder\",\n    actual = \"@rust_crates__byteorder-1.5.0//:byteorder\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cfg-if-1.0.4\",\n    actual = \"@rust_crates__cfg-if-1.0.4//:cfg_if\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cfg-if\",\n    actual = \"@rust_crates__cfg-if-1.0.4//:cfg_if\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cipher-0.4.4\",\n    actual = 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\"@rust_crates__ecdsa-0.16.9//:ecdsa\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-1.0.0//:embedded_hal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal\",\n    actual = \"@rust_crates__embedded-hal-1.0.0//:embedded_hal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-async-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-async-1.0.0//:embedded_hal_async\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-async\",\n    actual = \"@rust_crates__embedded-hal-async-1.0.0//:embedded_hal_async\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-nb-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-nb-1.0.0//:embedded_hal_nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-nb\",\n    actual = \"@rust_crates__embedded-hal-nb-1.0.0//:embedded_hal_nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = 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\"@rust_crates__serde-1.0.228//:serde\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde\",\n    actual = \"@rust_crates__serde-1.0.228//:serde\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_derive-1.0.228\",\n    actual = \"@rust_crates__serde_derive-1.0.228//:serde_derive\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_derive\",\n    actual = \"@rust_crates__serde_derive-1.0.228//:serde_derive\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_json5-0.2.1\",\n    actual = \"@rust_crates__serde_json5-0.2.1//:serde_json5\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_json5\",\n    actual = \"@rust_crates__serde_json5-0.2.1//:serde_json5\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha2-0.10.9\",\n    actual = \"@rust_crates__sha2-0.10.9//:sha2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha2\",\n    actual = \"@rust_crates__sha2-0.10.9//:sha2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = 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= \"@rust_crates__syn-1.0.109//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn1-1.0.109\",\n    actual = \"@rust_crates__syn-1.0.109//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn1\",\n    actual = \"@rust_crates__syn-1.0.109//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn-2.0.117\",\n    actual = \"@rust_crates__syn-2.0.117//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn\",\n    actual = \"@rust_crates__syn-2.0.117//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"thiserror-2.0.18\",\n    actual = \"@rust_crates__thiserror-2.0.18//:thiserror\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"thiserror\",\n    actual = \"@rust_crates__thiserror-2.0.18//:thiserror\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tock-registers-0.9.0\",\n    actual = \"@rust_crates__tock-registers-0.9.0//:tock_registers\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tock-registers\",\n    actual = \"@rust_crates__tock-registers-0.9.0//:tock_registers\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tokio-1.52.3\",\n    actual = \"@rust_crates__tokio-1.52.3//:tokio\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tokio\",\n    actual = \"@rust_crates__tokio-1.52.3//:tokio\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tokio-util-0.7.18\",\n    actual = \"@rust_crates__tokio-util-0.7.18//:tokio_util\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tokio-util\",\n    actual = \"@rust_crates__tokio-util-0.7.18//:tokio_util\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"vcell-0.1.3\",\n    actual = \"@rust_crates__vcell-0.1.3//:vcell\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"vcell\",\n    actual = \"@rust_crates__vcell-0.1.3//:vcell\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zerocopy-0.8.50\",\n    actual = \"@rust_crates__zerocopy-0.8.50//:zerocopy\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zerocopy\",\n    actual = \"@rust_crates__zerocopy-0.8.50//:zerocopy\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zeroize-1.8.2\",\n    actual = \"@rust_crates__zeroize-1.8.2//:zeroize\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zeroize\",\n    actual = \"@rust_crates__zeroize-1.8.2//:zeroize\",\n    tags = [\"manual\"],\n)\n",
+                "BUILD.bazel": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\npackage(default_visibility = [\"//visibility:public\"])\n\nexports_files(\n    [\n        \"cargo-bazel.json\",\n        \"crates.bzl\",\n        \"defs.bzl\",\n    ] + glob(\n        allow_empty = True,\n        include = [\"*.bazel\"],\n    ),\n)\n\nfilegroup(\n    name = \"srcs\",\n    srcs = glob(\n        allow_empty = True,\n        include = [\n            \"*.bazel\",\n            \"*.bzl\",\n        ],\n    ),\n)\n\n# Workspace Member Dependencies\nalias(\n    name = \"aes-0.8.4\",\n    actual = \"@rust_crates__aes-0.8.4//:aes\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes\",\n    actual = \"@rust_crates__aes-0.8.4//:aes\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes-gcm-0.10.3\",\n    actual = \"@rust_crates__aes-gcm-0.10.3//:aes_gcm\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aes-gcm\",\n    actual = \"@rust_crates__aes-gcm-0.10.3//:aes_gcm\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aligned-0.4.3\",\n    actual = \"@rust_crates__aligned-0.4.3//:aligned\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"aligned\",\n    actual = \"@rust_crates__aligned-0.4.3//:aligned\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"anyhow-1.0.102\",\n    actual = \"@rust_crates__anyhow-1.0.102//:anyhow\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"anyhow\",\n    actual = \"@rust_crates__anyhow-1.0.102//:anyhow\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-0.14.0\",\n    actual = \"@rust_crates__bitfield-0.14.0//:bitfield\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield\",\n    actual = \"@rust_crates__bitfield-0.14.0//:bitfield\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-struct-0.11.0\",\n    actual = \"@rust_crates__bitfield-struct-0.11.0//:bitfield_struct\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitfield-struct\",\n    actual = \"@rust_crates__bitfield-struct-0.11.0//:bitfield_struct\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitflags-2.12.1\",\n    actual = \"@rust_crates__bitflags-2.12.1//:bitflags\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"bitflags\",\n    actual = \"@rust_crates__bitflags-2.12.1//:bitflags\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"byteorder-1.5.0\",\n    actual = \"@rust_crates__byteorder-1.5.0//:byteorder\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"byteorder\",\n    actual = \"@rust_crates__byteorder-1.5.0//:byteorder\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cfg-if-1.0.4\",\n    actual = \"@rust_crates__cfg-if-1.0.4//:cfg_if\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cfg-if\",\n    actual = \"@rust_crates__cfg-if-1.0.4//:cfg_if\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cipher-0.4.4\",\n    actual = \"@rust_crates__cipher-0.4.4//:cipher\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cipher\",\n    actual = \"@rust_crates__cipher-0.4.4//:cipher\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"clap-4.6.1\",\n    actual = \"@rust_crates__clap-4.6.1//:clap\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"clap\",\n    actual = \"@rust_crates__clap-4.6.1//:clap\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"compiler_builtins-0.1.160\",\n    actual = \"@rust_crates__compiler_builtins-0.1.160//:compiler_builtins\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"compiler_builtins\",\n    actual = \"@rust_crates__compiler_builtins-0.1.160//:compiler_builtins\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m-0.7.7\",\n    actual = \"@rust_crates__cortex-m-0.7.7//:cortex_m\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m\",\n    actual = \"@rust_crates__cortex-m-0.7.7//:cortex_m\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m-rt-0.7.5\",\n    actual = \"@rust_crates__cortex-m-rt-0.7.5//:cortex_m_rt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m-rt\",\n    actual = \"@rust_crates__cortex-m-rt-0.7.5//:cortex_m_rt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m-semihosting-0.5.0\",\n    actual = \"@rust_crates__cortex-m-semihosting-0.5.0//:cortex_m_semihosting\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"cortex-m-semihosting\",\n    actual = \"@rust_crates__cortex-m-semihosting-0.5.0//:cortex_m_semihosting\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"critical-section-1.2.0\",\n    actual = \"@rust_crates__critical-section-1.2.0//:critical_section\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"critical-section\",\n    actual = \"@rust_crates__critical-section-1.2.0//:critical_section\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ctr-0.9.2\",\n    actual = \"@rust_crates__ctr-0.9.2//:ctr\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ctr\",\n    actual = \"@rust_crates__ctr-0.9.2//:ctr\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ecdsa-0.16.9\",\n    actual = \"@rust_crates__ecdsa-0.16.9//:ecdsa\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"ecdsa\",\n    actual = \"@rust_crates__ecdsa-0.16.9//:ecdsa\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-1.0.0//:embedded_hal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal\",\n    actual = \"@rust_crates__embedded-hal-1.0.0//:embedded_hal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-async-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-async-1.0.0//:embedded_hal_async\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-async\",\n    actual = \"@rust_crates__embedded-hal-async-1.0.0//:embedded_hal_async\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-nb-1.0.0\",\n    actual = \"@rust_crates__embedded-hal-nb-1.0.0//:embedded_hal_nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-hal-nb\",\n    actual = \"@rust_crates__embedded-hal-nb-1.0.0//:embedded_hal_nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-io-0.6.1\",\n    actual = \"@rust_crates__embedded-io-0.6.1//:embedded_io\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-io\",\n    actual = \"@rust_crates__embedded-io-0.6.1//:embedded_io\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-storage-0.3.1\",\n    actual = \"@rust_crates__embedded-storage-0.3.1//:embedded_storage\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"embedded-storage\",\n    actual = \"@rust_crates__embedded-storage-0.3.1//:embedded_storage\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"fugit-0.3.9\",\n    actual = \"@rust_crates__fugit-0.3.9//:fugit\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"fugit\",\n    actual = \"@rust_crates__fugit-0.3.9//:fugit\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"futures-0.3.32\",\n    actual = \"@rust_crates__futures-0.3.32//:futures\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"futures\",\n    actual = \"@rust_crates__futures-0.3.32//:futures\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"heapless-0.9.3\",\n    actual = \"@rust_crates__heapless-0.9.3//:heapless\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"heapless\",\n    actual = \"@rust_crates__heapless-0.9.3//:heapless\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hex-0.4.3\",\n    actual = \"@rust_crates__hex-0.4.3//:hex\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hex\",\n    actual = \"@rust_crates__hex-0.4.3//:hex\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hex-literal-0.4.1\",\n    actual = \"@rust_crates__hex-literal-0.4.1//:hex_literal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hex-literal\",\n    actual = \"@rust_crates__hex-literal-0.4.1//:hex_literal\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hmac-0.12.1\",\n    actual = \"@rust_crates__hmac-0.12.1//:hmac\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"hmac\",\n    actual = \"@rust_crates__hmac-0.12.1//:hmac\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"k256-0.13.4\",\n    actual = \"@rust_crates__k256-0.13.4//:k256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"k256\",\n    actual = \"@rust_crates__k256-0.13.4//:k256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"log-0.4.31\",\n    actual = \"@rust_crates__log-0.4.31//:log\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"log\",\n    actual = \"@rust_crates__log-0.4.31//:log\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"mctp-0.2.0\",\n    actual = \"@rust_crates__mctp-0.2.0//:mctp\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"mctp\",\n    actual = \"@rust_crates__mctp-0.2.0//:mctp\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"mctp-lib-0.1.0\",\n    actual = \"@rust_crates__mctp-lib-0.1.0//:mctp_lib\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"mctp-lib\",\n    actual = \"@rust_crates__mctp-lib-0.1.0//:mctp_lib\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"memoffset-0.9.1\",\n    actual = \"@rust_crates__memoffset-0.9.1//:memoffset\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"memoffset\",\n    actual = \"@rust_crates__memoffset-0.9.1//:memoffset\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"minijinja-2.20.0\",\n    actual = \"@rust_crates__minijinja-2.20.0//:minijinja\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"minijinja\",\n    actual = \"@rust_crates__minijinja-2.20.0//:minijinja\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nb-1.1.0\",\n    actual = \"@rust_crates__nb-1.1.0//:nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nb\",\n    actual = \"@rust_crates__nb-1.1.0//:nb\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nom-7.1.3\",\n    actual = \"@rust_crates__nom-7.1.3//:nom\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"nom\",\n    actual = \"@rust_crates__nom-7.1.3//:nom\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"object-0.37.3\",\n    actual = \"@rust_crates__object-0.37.3//:object\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"object\",\n    actual = \"@rust_crates__object-0.37.3//:object\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"openprot-hal-blocking-0.1.0\",\n    actual = \"@rust_crates__openprot-hal-blocking-0.1.0//:openprot_hal_blocking\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"openprot-hal-blocking\",\n    actual = \"@rust_crates__openprot-hal-blocking-0.1.0//:openprot_hal_blocking\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p256-0.13.2\",\n    actual = \"@rust_crates__p256-0.13.2//:p256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p256\",\n    actual = \"@rust_crates__p256-0.13.2//:p256\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p384-0.13.1\",\n    actual = \"@rust_crates__p384-0.13.1//:p384\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"p384\",\n    actual = \"@rust_crates__p384-0.13.1//:p384\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"panic-halt-1.0.0\",\n    actual = \"@rust_crates__panic-halt-1.0.0//:panic_halt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"panic-halt\",\n    actual = \"@rust_crates__panic-halt-1.0.0//:panic_halt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"paste-1.0.15\",\n    actual = \"@rust_crates__paste-1.0.15//:paste\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"paste\",\n    actual = \"@rust_crates__paste-1.0.15//:paste\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"proc-macro2-1.0.106\",\n    actual = \"@rust_crates__proc-macro2-1.0.106//:proc_macro2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"proc-macro2\",\n    actual = \"@rust_crates__proc-macro2-1.0.106//:proc_macro2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"prost-0.13.5\",\n    actual = \"@rust_crates__prost-0.13.5//:prost\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"prost\",\n    actual = \"@rust_crates__prost-0.13.5//:prost\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"quote-1.0.45\",\n    actual = \"@rust_crates__quote-1.0.45//:quote\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"quote\",\n    actual = \"@rust_crates__quote-1.0.45//:quote\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rand_core-0.9.5\",\n    actual = \"@rust_crates__rand_core-0.9.5//:rand_core\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rand_core\",\n    actual = \"@rust_crates__rand_core-0.9.5//:rand_core\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-0.12.1\",\n    actual = \"@rust_crates__riscv-0.12.1//:riscv\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv\",\n    actual = \"@rust_crates__riscv-0.12.1//:riscv\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-rt-0.12.2\",\n    actual = \"@rust_crates__riscv-rt-0.12.2//:riscv_rt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-rt\",\n    actual = \"@rust_crates__riscv-rt-0.12.2//:riscv_rt\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-semihosting-0.1.3\",\n    actual = \"@rust_crates__riscv-semihosting-0.1.3//:riscv_semihosting\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"riscv-semihosting\",\n    actual = \"@rust_crates__riscv-semihosting-0.1.3//:riscv_semihosting\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rustc-demangle-0.1.27\",\n    actual = \"@rust_crates__rustc-demangle-0.1.27//:rustc_demangle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"rustc-demangle\",\n    actual = \"@rust_crates__rustc-demangle-0.1.27//:rustc_demangle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sec1-0.7.3\",\n    actual = \"@rust_crates__sec1-0.7.3//:sec1\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sec1\",\n    actual = \"@rust_crates__sec1-0.7.3//:sec1\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde-1.0.228\",\n    actual = \"@rust_crates__serde-1.0.228//:serde\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde\",\n    actual = \"@rust_crates__serde-1.0.228//:serde\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_derive-1.0.228\",\n    actual = \"@rust_crates__serde_derive-1.0.228//:serde_derive\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_derive\",\n    actual = \"@rust_crates__serde_derive-1.0.228//:serde_derive\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_json5-0.2.1\",\n    actual = \"@rust_crates__serde_json5-0.2.1//:serde_json5\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"serde_json5\",\n    actual = \"@rust_crates__serde_json5-0.2.1//:serde_json5\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha2-0.10.9\",\n    actual = \"@rust_crates__sha2-0.10.9//:sha2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha2\",\n    actual = \"@rust_crates__sha2-0.10.9//:sha2\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha3-0.10.9\",\n    actual = \"@rust_crates__sha3-0.10.9//:sha3\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"sha3\",\n    actual = \"@rust_crates__sha3-0.10.9//:sha3\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"smlang-0.8.0\",\n    actual = \"@rust_crates__smlang-0.8.0//:smlang\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"smlang\",\n    actual = \"@rust_crates__smlang-0.8.0//:smlang\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"spdm-lib-0.1.0\",\n    actual = \"@rust_crates__spdm-lib-0.1.0//:spdm_lib\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"spdm-lib\",\n    actual = \"@rust_crates__spdm-lib-0.1.0//:spdm_lib\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"subtle-2.6.1\",\n    actual = \"@rust_crates__subtle-2.6.1//:subtle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"subtle\",\n    actual = \"@rust_crates__subtle-2.6.1//:subtle\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn-1.0.109\",\n    actual = \"@rust_crates__syn-1.0.109//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn1-1.0.109\",\n    actual = \"@rust_crates__syn-1.0.109//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn1\",\n    actual = \"@rust_crates__syn-1.0.109//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn-2.0.117\",\n    actual = \"@rust_crates__syn-2.0.117//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"syn\",\n    actual = \"@rust_crates__syn-2.0.117//:syn\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"thiserror-2.0.18\",\n    actual = \"@rust_crates__thiserror-2.0.18//:thiserror\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"thiserror\",\n    actual = \"@rust_crates__thiserror-2.0.18//:thiserror\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tock-registers-0.9.0\",\n    actual = \"@rust_crates__tock-registers-0.9.0//:tock_registers\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tock-registers\",\n    actual = \"@rust_crates__tock-registers-0.9.0//:tock_registers\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tokio-1.52.3\",\n    actual = \"@rust_crates__tokio-1.52.3//:tokio\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tokio\",\n    actual = \"@rust_crates__tokio-1.52.3//:tokio\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tokio-util-0.7.18\",\n    actual = \"@rust_crates__tokio-util-0.7.18//:tokio_util\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"tokio-util\",\n    actual = \"@rust_crates__tokio-util-0.7.18//:tokio_util\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"vcell-0.1.3\",\n    actual = \"@rust_crates__vcell-0.1.3//:vcell\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"vcell\",\n    actual = \"@rust_crates__vcell-0.1.3//:vcell\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zerocopy-0.8.50\",\n    actual = \"@rust_crates__zerocopy-0.8.50//:zerocopy\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zerocopy\",\n    actual = \"@rust_crates__zerocopy-0.8.50//:zerocopy\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zeroize-1.8.2\",\n    actual = \"@rust_crates__zeroize-1.8.2//:zeroize\",\n    tags = [\"manual\"],\n)\n\nalias(\n    name = \"zeroize\",\n    actual = \"@rust_crates__zeroize-1.8.2//:zeroize\",\n    tags = [\"manual\"],\n)\n",
                 "alias_rules.bzl": "\"\"\"Alias that transitions its target to `compilation_mode=opt`.  Use `transition_alias=\"opt\"` to enable.\"\"\"\n\nload(\"@rules_cc//cc:defs.bzl\", \"CcInfo\")\nload(\"@rules_rust//rust:rust_common.bzl\", \"COMMON_PROVIDERS\")\n\ndef _transition_alias_impl(ctx):\n    # `ctx.attr.actual` is a list of 1 item due to the transition\n    providers = [ctx.attr.actual[0][provider] for provider in COMMON_PROVIDERS]\n    if CcInfo in ctx.attr.actual[0]:\n        providers.append(ctx.attr.actual[0][CcInfo])\n    return providers\n\ndef _change_compilation_mode(compilation_mode):\n    def _change_compilation_mode_impl(_settings, _attr):\n        return {\n            \"//command_line_option:compilation_mode\": compilation_mode,\n        }\n\n    return transition(\n        implementation = _change_compilation_mode_impl,\n        inputs = [],\n        outputs = [\n            \"//command_line_option:compilation_mode\",\n        ],\n    )\n\ndef _transition_alias_rule(compilation_mode):\n    return rule(\n        implementation = _transition_alias_impl,\n        provides = COMMON_PROVIDERS,\n        attrs = {\n            \"actual\": attr.label(\n                mandatory = True,\n                doc = \"`rust_library()` target to transition to `compilation_mode=opt`.\",\n                providers = COMMON_PROVIDERS,\n                cfg = _change_compilation_mode(compilation_mode),\n            ),\n            \"_allowlist_function_transition\": attr.label(\n                default = \"@bazel_tools//tools/allowlists/function_transition_allowlist\",\n            ),\n        },\n        doc = \"Transitions a Rust library crate to the `compilation_mode=opt`.\",\n    )\n\ntransition_alias_dbg = _transition_alias_rule(\"dbg\")\ntransition_alias_fastbuild = _transition_alias_rule(\"fastbuild\")\ntransition_alias_opt = _transition_alias_rule(\"opt\")\n",
-                "defs.bzl": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\"\"\"\n# `crates_repository` API\n\n- [aliases](#aliases)\n- [crate_deps](#crate_deps)\n- [all_crate_deps](#all_crate_deps)\n- [crate_repositories](#crate_repositories)\n\n\"\"\"\n\nload(\"@bazel_tools//tools/build_defs/repo:git.bzl\", \"git_repository\")\nload(\"@bazel_tools//tools/build_defs/repo:http.bzl\", \"http_archive\")\nload(\"@bazel_tools//tools/build_defs/repo:utils.bzl\", \"maybe\")\nload(\"@bazel_skylib//lib:selects.bzl\", \"selects\")\nload(\"@rules_rust//crate_universe/private:local_crate_mirror.bzl\", \"local_crate_mirror\")\n\n###############################################################################\n# MACROS API\n###############################################################################\n\n# An identifier that represent common dependencies (unconditional).\n_COMMON_CONDITION = \"\"\n\ndef _flatten_dependency_maps(all_dependency_maps):\n    \"\"\"Flatten a list of dependency maps into one dictionary.\n\n    Dependency maps have the following structure:\n\n    ```python\n    DEPENDENCIES_MAP = {\n        # The first key in the map is a Bazel package\n        # name of the workspace this file is defined in.\n        \"workspace_member_package\": {\n\n            # Not all dependencies are supported for all platforms.\n            # the condition key is the condition required to be true\n            # on the host platform.\n            \"condition\": {\n\n                # An alias to a crate target.     # The label of the crate target the\n                # Aliases are only crate names.   # package name refers to.\n                \"package_name\":                   \"@full//:label\",\n            }\n        }\n    }\n    ```\n\n    Args:\n        all_dependency_maps (list): A list of dicts as described above\n\n    Returns:\n        dict: A dictionary as described above\n    \"\"\"\n    dependencies = {}\n\n    for workspace_deps_map in all_dependency_maps:\n        for pkg_name, conditional_deps_map in workspace_deps_map.items():\n            if pkg_name not in dependencies:\n                non_frozen_map = dict()\n                for key, values in conditional_deps_map.items():\n                    non_frozen_map.update({key: dict(values.items())})\n                dependencies.setdefault(pkg_name, non_frozen_map)\n                continue\n\n            for condition, deps_map in conditional_deps_map.items():\n                # If the condition has not been recorded, do so and continue\n                if condition not in dependencies[pkg_name]:\n                    dependencies[pkg_name].setdefault(condition, dict(deps_map.items()))\n                    continue\n\n                # Alert on any miss-matched dependencies\n                inconsistent_entries = []\n                for crate_name, crate_label in deps_map.items():\n                    existing = dependencies[pkg_name][condition].get(crate_name)\n                    if existing and existing != crate_label:\n                        inconsistent_entries.append((crate_name, existing, crate_label))\n                    dependencies[pkg_name][condition].update({crate_name: crate_label})\n\n    return dependencies\n\ndef crate_deps(deps, package_name = None):\n    \"\"\"Finds the fully qualified label of the requested crates for the package where this macro is called.\n\n    Args:\n        deps (list): The desired list of crate targets.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()`.\n\n    Returns:\n        list: A list of labels to generated rust targets (str)\n    \"\"\"\n\n    if not deps:\n        return []\n\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Join both sets of dependencies\n    dependencies = _flatten_dependency_maps([\n        _NORMAL_DEPENDENCIES,\n        _NORMAL_DEV_DEPENDENCIES,\n        _PROC_MACRO_DEPENDENCIES,\n        _PROC_MACRO_DEV_DEPENDENCIES,\n        _BUILD_DEPENDENCIES,\n        _BUILD_PROC_MACRO_DEPENDENCIES,\n    ]).pop(package_name, {})\n\n    # Combine all conditional packages so we can easily index over a flat list\n    # TODO: Perhaps this should actually return select statements and maintain\n    # the conditionals of the dependencies\n    flat_deps = {}\n    for deps_set in dependencies.values():\n        for crate_name, crate_label in deps_set.items():\n            flat_deps.update({crate_name: crate_label})\n\n    missing_crates = []\n    crate_targets = []\n    for crate_target in deps:\n        if crate_target not in flat_deps:\n            missing_crates.append(crate_target)\n        else:\n            crate_targets.append(flat_deps[crate_target])\n\n    if missing_crates:\n        fail(\"Could not find crates `{}` among dependencies of `{}`. Available dependencies were `{}`\".format(\n            missing_crates,\n            package_name,\n            dependencies,\n        ))\n\n    return crate_targets\n\ndef all_crate_deps(\n        normal = False, \n        normal_dev = False, \n        proc_macro = False, \n        proc_macro_dev = False,\n        build = False,\n        build_proc_macro = False,\n        package_name = None):\n    \"\"\"Finds the fully qualified label of all requested direct crate dependencies \\\n    for the package where this macro is called.\n\n    If no parameters are set, all normal dependencies are returned. Setting any one flag will\n    otherwise impact the contents of the returned list.\n\n    Args:\n        normal (bool, optional): If True, normal dependencies are included in the\n            output list.\n        normal_dev (bool, optional): If True, normal dev dependencies will be\n            included in the output list.\n        proc_macro (bool, optional): If True, proc_macro dependencies are included\n            in the output list.\n        proc_macro_dev (bool, optional): If True, dev proc_macro dependencies are\n            included in the output list.\n        build (bool, optional): If True, build dependencies are included\n            in the output list.\n        build_proc_macro (bool, optional): If True, build proc_macro dependencies are\n            included in the output list.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()` when unset.\n\n    Returns:\n        list: A list of labels to generated rust targets (str)\n    \"\"\"\n\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Determine the relevant maps to use\n    all_dependency_maps = []\n    if normal:\n        all_dependency_maps.append(_NORMAL_DEPENDENCIES)\n    if normal_dev:\n        all_dependency_maps.append(_NORMAL_DEV_DEPENDENCIES)\n    if proc_macro:\n        all_dependency_maps.append(_PROC_MACRO_DEPENDENCIES)\n    if proc_macro_dev:\n        all_dependency_maps.append(_PROC_MACRO_DEV_DEPENDENCIES)\n    if build:\n        all_dependency_maps.append(_BUILD_DEPENDENCIES)\n    if build_proc_macro:\n        all_dependency_maps.append(_BUILD_PROC_MACRO_DEPENDENCIES)\n\n    # Default to always using normal dependencies\n    if not all_dependency_maps:\n        all_dependency_maps.append(_NORMAL_DEPENDENCIES)\n\n    dependencies = _flatten_dependency_maps(all_dependency_maps).pop(package_name, None)\n\n    if not dependencies:\n        if dependencies == None:\n            fail(\"Tried to get all_crate_deps for package \" + package_name + \" but that package had no Cargo.toml file\")\n        else:\n            return []\n\n    crate_deps = list(dependencies.pop(_COMMON_CONDITION, {}).values())\n    for condition, deps in dependencies.items():\n        crate_deps += selects.with_or({\n            tuple(_CONDITIONS[condition]): deps.values(),\n            \"//conditions:default\": [],\n        })\n\n    return crate_deps\n\ndef aliases(\n        normal = False,\n        normal_dev = False,\n        proc_macro = False,\n        proc_macro_dev = False,\n        build = False,\n        build_proc_macro = False,\n        package_name = None):\n    \"\"\"Produces a map of Crate alias names to their original label\n\n    If no dependency kinds are specified, `normal` and `proc_macro` are used by default.\n    Setting any one flag will otherwise determine the contents of the returned dict.\n\n    Args:\n        normal (bool, optional): If True, normal dependencies are included in the\n            output list.\n        normal_dev (bool, optional): If True, normal dev dependencies will be\n            included in the output list..\n        proc_macro (bool, optional): If True, proc_macro dependencies are included\n            in the output list.\n        proc_macro_dev (bool, optional): If True, dev proc_macro dependencies are\n            included in the output list.\n        build (bool, optional): If True, build dependencies are included\n            in the output list.\n        build_proc_macro (bool, optional): If True, build proc_macro dependencies are\n            included in the output list.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()` when unset.\n\n    Returns:\n        dict: The aliases of all associated packages\n    \"\"\"\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Determine the relevant maps to use\n    all_aliases_maps = []\n    if normal:\n        all_aliases_maps.append(_NORMAL_ALIASES)\n    if normal_dev:\n        all_aliases_maps.append(_NORMAL_DEV_ALIASES)\n    if proc_macro:\n        all_aliases_maps.append(_PROC_MACRO_ALIASES)\n    if proc_macro_dev:\n        all_aliases_maps.append(_PROC_MACRO_DEV_ALIASES)\n    if build:\n        all_aliases_maps.append(_BUILD_ALIASES)\n    if build_proc_macro:\n        all_aliases_maps.append(_BUILD_PROC_MACRO_ALIASES)\n\n    # Default to always using normal aliases\n    if not all_aliases_maps:\n        all_aliases_maps.append(_NORMAL_ALIASES)\n        all_aliases_maps.append(_PROC_MACRO_ALIASES)\n\n    aliases = _flatten_dependency_maps(all_aliases_maps).pop(package_name, None)\n\n    if not aliases:\n        return dict()\n\n    common_items = aliases.pop(_COMMON_CONDITION, {}).items()\n\n    # If there are only common items in the dictionary, immediately return them\n    if not len(aliases.keys()) == 1:\n        return dict(common_items)\n\n    # Build a single select statement where each conditional has accounted for the\n    # common set of aliases.\n    crate_aliases = {\"//conditions:default\": dict(common_items)}\n    for condition, deps in aliases.items():\n        condition_triples = _CONDITIONS[condition]\n        for triple in condition_triples:\n            if triple in crate_aliases:\n                crate_aliases[triple].update(deps)\n            else:\n                crate_aliases.update({triple: dict(deps.items() + common_items)})\n\n    return select(crate_aliases)\n\n###############################################################################\n# WORKSPACE MEMBER DEPS AND ALIASES\n###############################################################################\n\n_NORMAL_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            \"aes\": Label(\"@rust_crates//:aes-0.8.4\"),\n            \"aes-gcm\": Label(\"@rust_crates//:aes-gcm-0.10.3\"),\n            \"aligned\": Label(\"@rust_crates//:aligned-0.4.3\"),\n            \"anyhow\": Label(\"@rust_crates//:anyhow-1.0.102\"),\n            \"bitfield\": Label(\"@rust_crates//:bitfield-0.14.0\"),\n            \"bitflags\": Label(\"@rust_crates//:bitflags-2.12.1\"),\n            \"byteorder\": Label(\"@rust_crates//:byteorder-1.5.0\"),\n            \"cfg-if\": Label(\"@rust_crates//:cfg-if-1.0.4\"),\n            \"cipher\": Label(\"@rust_crates//:cipher-0.4.4\"),\n            \"clap\": Label(\"@rust_crates//:clap-4.6.1\"),\n            \"compiler_builtins\": Label(\"@rust_crates//:compiler_builtins-0.1.160\"),\n            \"cortex-m\": Label(\"@rust_crates//:cortex-m-0.7.7\"),\n            \"cortex-m-rt\": Label(\"@rust_crates//:cortex-m-rt-0.7.5\"),\n            \"cortex-m-semihosting\": Label(\"@rust_crates//:cortex-m-semihosting-0.5.0\"),\n            \"ctr\": Label(\"@rust_crates//:ctr-0.9.2\"),\n            \"ecdsa\": Label(\"@rust_crates//:ecdsa-0.16.9\"),\n            \"embedded-hal\": Label(\"@rust_crates//:embedded-hal-1.0.0\"),\n            \"embedded-hal-async\": Label(\"@rust_crates//:embedded-hal-async-1.0.0\"),\n            \"embedded-hal-nb\": Label(\"@rust_crates//:embedded-hal-nb-1.0.0\"),\n            \"embedded-io\": Label(\"@rust_crates//:embedded-io-0.6.1\"),\n            \"embedded-storage\": Label(\"@rust_crates//:embedded-storage-0.3.1\"),\n            \"fugit\": Label(\"@rust_crates//:fugit-0.3.9\"),\n            \"futures\": Label(\"@rust_crates//:futures-0.3.32\"),\n            \"heapless\": Label(\"@rust_crates//:heapless-0.9.3\"),\n            \"hex\": Label(\"@rust_crates//:hex-0.4.3\"),\n            \"hex-literal\": Label(\"@rust_crates//:hex-literal-0.4.1\"),\n            \"hmac\": Label(\"@rust_crates//:hmac-0.12.1\"),\n            \"k256\": Label(\"@rust_crates//:k256-0.13.4\"),\n            \"log\": Label(\"@rust_crates//:log-0.4.31\"),\n            \"mctp\": Label(\"@rust_crates//:mctp-0.2.0\"),\n            \"mctp-lib\": Label(\"@rust_crates//:mctp-lib-0.1.0\"),\n            \"memoffset\": Label(\"@rust_crates//:memoffset-0.9.1\"),\n            \"minijinja\": Label(\"@rust_crates//:minijinja-2.20.0\"),\n            \"nb\": Label(\"@rust_crates//:nb-1.1.0\"),\n            \"nom\": Label(\"@rust_crates//:nom-7.1.3\"),\n            \"object\": Label(\"@rust_crates//:object-0.37.3\"),\n            \"openprot-hal-blocking\": Label(\"@rust_crates//:openprot-hal-blocking-0.1.0\"),\n            \"p256\": Label(\"@rust_crates//:p256-0.13.2\"),\n            \"p384\": Label(\"@rust_crates//:p384-0.13.1\"),\n            \"panic-halt\": Label(\"@rust_crates//:panic-halt-1.0.0\"),\n            \"proc-macro2\": Label(\"@rust_crates//:proc-macro2-1.0.106\"),\n            \"prost\": Label(\"@rust_crates//:prost-0.13.5\"),\n            \"quote\": Label(\"@rust_crates//:quote-1.0.45\"),\n            \"rand_core\": Label(\"@rust_crates//:rand_core-0.9.5\"),\n            \"riscv\": Label(\"@rust_crates//:riscv-0.12.1\"),\n            \"riscv-rt\": Label(\"@rust_crates//:riscv-rt-0.12.2\"),\n            \"riscv-semihosting\": Label(\"@rust_crates//:riscv-semihosting-0.1.3\"),\n            \"rustc-demangle\": Label(\"@rust_crates//:rustc-demangle-0.1.27\"),\n            \"sec1\": Label(\"@rust_crates//:sec1-0.7.3\"),\n            \"serde\": Label(\"@rust_crates//:serde-1.0.228\"),\n            \"serde_json5\": Label(\"@rust_crates//:serde_json5-0.2.1\"),\n            \"sha2\": Label(\"@rust_crates//:sha2-0.10.9\"),\n            \"sha3\": Label(\"@rust_crates//:sha3-0.10.9\"),\n            \"smlang\": Label(\"@rust_crates//:smlang-0.8.0\"),\n            \"spdm-lib\": Label(\"@rust_crates//:spdm-lib-0.1.0\"),\n            \"subtle\": Label(\"@rust_crates//:subtle-2.6.1\"),\n            \"syn1\": Label(\"@rust_crates//:syn-1.0.109\"),\n            \"syn\": Label(\"@rust_crates//:syn-2.0.117\"),\n            \"thiserror\": Label(\"@rust_crates//:thiserror-2.0.18\"),\n            \"tock-registers\": Label(\"@rust_crates//:tock-registers-0.9.0\"),\n            \"tokio\": Label(\"@rust_crates//:tokio-1.52.3\"),\n            \"tokio-util\": Label(\"@rust_crates//:tokio-util-0.7.18\"),\n            \"vcell\": Label(\"@rust_crates//:vcell-0.1.3\"),\n            \"zerocopy\": Label(\"@rust_crates//:zerocopy-0.8.50\"),\n            \"zeroize\": Label(\"@rust_crates//:zeroize-1.8.2\"),\n        },\n    },\n}\n\n\n_NORMAL_ALIASES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            Label(\"@rust_crates//:syn-1.0.109\"): \"syn1\",\n        },\n    },\n}\n\n\n_NORMAL_DEV_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_NORMAL_DEV_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            \"bitfield-struct\": Label(\"@rust_crates//:bitfield-struct-0.11.0\"),\n            \"paste\": Label(\"@rust_crates//:paste-1.0.15\"),\n            \"serde_derive\": Label(\"@rust_crates//:serde_derive-1.0.228\"),\n        },\n    },\n}\n\n\n_PROC_MACRO_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEV_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEV_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_PROC_MACRO_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_PROC_MACRO_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_CONDITIONS = {\n    \"aarch64-apple-darwin\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\"],\n    \"aarch64-linux-android\": [],\n    \"aarch64-unknown-linux-gnu\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(all(any(target_os = \\\"linux\\\", target_os = \\\"android\\\"), any(rustix_use_libc, miri, not(all(target_os = \\\"linux\\\", any(target_endian = \\\"little\\\", any(target_arch = \\\"s390x\\\", target_arch = \\\"powerpc\\\")), any(target_arch = \\\"arm\\\", all(target_arch = \\\"aarch64\\\", target_pointer_width = \\\"64\\\"), target_arch = \\\"riscv64\\\", all(rustix_use_experimental_asm, target_arch = \\\"powerpc\\\"), all(rustix_use_experimental_asm, target_arch = \\\"powerpc64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"s390x\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips32r6\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64r6\\\"), target_arch = \\\"x86\\\", all(target_arch = \\\"x86_64\\\", target_pointer_width = \\\"64\\\")))))))\": [],\n    \"cfg(all(not(rustix_use_libc), not(miri), target_os = \\\"linux\\\", any(target_endian = \\\"little\\\", any(target_arch = \\\"s390x\\\", target_arch = \\\"powerpc\\\")), any(target_arch = \\\"arm\\\", all(target_arch = \\\"aarch64\\\", target_pointer_width = \\\"64\\\"), target_arch = \\\"riscv64\\\", all(rustix_use_experimental_asm, target_arch = \\\"powerpc\\\"), all(rustix_use_experimental_asm, target_arch = \\\"powerpc64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"s390x\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips32r6\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64r6\\\"), target_arch = \\\"x86\\\", all(target_arch = \\\"x86_64\\\", target_pointer_width = \\\"64\\\"))))\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(all(not(windows), any(rustix_use_libc, miri, not(all(target_os = \\\"linux\\\", any(target_endian = \\\"little\\\", any(target_arch = \\\"s390x\\\", target_arch = \\\"powerpc\\\")), any(target_arch = \\\"arm\\\", all(target_arch = \\\"aarch64\\\", target_pointer_width = \\\"64\\\"), target_arch = \\\"riscv64\\\", all(rustix_use_experimental_asm, target_arch = \\\"powerpc\\\"), all(rustix_use_experimental_asm, target_arch = \\\"powerpc64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"s390x\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips32r6\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64r6\\\"), target_arch = \\\"x86\\\", all(target_arch = \\\"x86_64\\\", target_pointer_width = \\\"64\\\")))))))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\",\"@rules_rust//rust/platform:thumbv7em-none-eabi\",\"@rules_rust//rust/platform:x86_64-apple-darwin\"],\n    \"cfg(all(target_arch = \\\"aarch64\\\", target_os = \\\"linux\\\"))\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(all(target_arch = \\\"aarch64\\\", target_vendor = \\\"apple\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\"],\n    \"cfg(all(target_arch = \\\"loongarch64\\\", target_os = \\\"linux\\\"))\": [],\n    \"cfg(any())\": [],\n    \"cfg(any(target_arch = \\\"aarch64\\\", target_arch = \\\"x86_64\\\", target_arch = \\\"x86\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(any(target_arch = \\\"arm\\\", target_pointer_width = \\\"32\\\", target_pointer_width = \\\"64\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\",\"@rules_rust//rust/platform:thumbv7em-none-eabi\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(any(unix, target_os = \\\"hermit\\\", target_os = \\\"wasi\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(any(unix, target_os = \\\"wasi\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(target_arch = \\\"aarch64\\\")\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(target_os = \\\"hermit\\\")\": [],\n    \"cfg(target_os = \\\"redox\\\")\": [],\n    \"cfg(target_os = \\\"wasi\\\")\": [],\n    \"cfg(unix)\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(windows)\": [],\n    \"riscv32imc-unknown-none-elf\": [\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\"],\n    \"thumbv7em-none-eabi\": [\"@rules_rust//rust/platform:thumbv7em-none-eabi\"],\n    \"x86_64-apple-darwin\": [\"@rules_rust//rust/platform:x86_64-apple-darwin\"],\n    \"x86_64-unknown-linux-gnu\": [\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n}\n\n###############################################################################\n\ndef crate_repositories():\n    \"\"\"A macro for defining repositories for all generated crates.\n\n    Returns:\n      A list of repos visible to the module through the module extension.\n    \"\"\"\n    maybe(\n        http_archive,\n        name = \"rust_crates__adler2-2.0.1\",\n        sha256 = \"320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/adler2/2.0.1/download\"],\n        strip_prefix = \"adler2-2.0.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.adler2-2.0.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aead-0.5.2\",\n        sha256 = \"d122413f284cf2d62fb1b7db97e02edb8cda96d769b16e443a4f6195e35662b0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aead/0.5.2/download\"],\n        strip_prefix = \"aead-0.5.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aead-0.5.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aes-0.8.4\",\n        sha256 = \"b169f7a6d4742236a0a00c541b845991d0ac43e546831af1249753ab4c3aa3a0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aes/0.8.4/download\"],\n        strip_prefix = \"aes-0.8.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aes-0.8.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aes-gcm-0.10.3\",\n        sha256 = \"831010a0f742e1209b3bcea8fab6a8e149051ba6099432c8cb2cc117dec3ead1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aes-gcm/0.10.3/download\"],\n        strip_prefix = \"aes-gcm-0.10.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aes-gcm-0.10.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aligned-0.4.3\",\n        sha256 = \"ee4508988c62edf04abd8d92897fca0c2995d907ce1dfeaf369dac3716a40685\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aligned/0.4.3/download\"],\n        strip_prefix = \"aligned-0.4.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aligned-0.4.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstream-1.0.0\",\n        sha256 = \"824a212faf96e9acacdbd09febd34438f8f711fb84e09a8916013cd7815ca28d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstream/1.0.0/download\"],\n        strip_prefix = \"anstream-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstream-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-1.0.14\",\n        sha256 = \"940b3a0ca603d1eade50a4846a2afffd5ef57a9feac2c0e2ec2e14f9ead76000\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle/1.0.14/download\"],\n        strip_prefix = \"anstyle-1.0.14\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-1.0.14.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-parse-1.0.0\",\n        sha256 = \"52ce7f38b242319f7cabaa6813055467063ecdc9d355bbb4ce0c68908cd8130e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-parse/1.0.0/download\"],\n        strip_prefix = \"anstyle-parse-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-parse-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-query-1.1.5\",\n        sha256 = \"40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-query/1.1.5/download\"],\n        strip_prefix = \"anstyle-query-1.1.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-query-1.1.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-wincon-3.0.11\",\n        sha256 = \"291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-wincon/3.0.11/download\"],\n        strip_prefix = \"anstyle-wincon-3.0.11\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-wincon-3.0.11.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anyhow-1.0.102\",\n        sha256 = \"7f202df86484c868dbad7eaa557ef785d5c66295e41b460ef922eca0723b842c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anyhow/1.0.102/download\"],\n        strip_prefix = \"anyhow-1.0.102\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anyhow-1.0.102.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__as-slice-0.2.1\",\n        sha256 = \"516b6b4f0e40d50dcda9365d53964ec74560ad4284da2e7fc97122cd83174516\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/as-slice/0.2.1/download\"],\n        strip_prefix = \"as-slice-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.as-slice-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__autocfg-1.5.1\",\n        sha256 = \"f2032f911046de80f0a198e0901378627c33f59ea0ac00e363d481118bd70a53\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/autocfg/1.5.1/download\"],\n        strip_prefix = \"autocfg-1.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.autocfg-1.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bare-metal-0.2.5\",\n        sha256 = \"5deb64efa5bd81e31fcd1938615a6d98c82eafcbcd787162b6f63b91d6bac5b3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bare-metal/0.2.5/download\"],\n        strip_prefix = \"bare-metal-0.2.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bare-metal-0.2.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__base16ct-0.2.0\",\n        sha256 = \"4c7f02d4ea65f2c1853089ffd8d2787bdbc63de2f0d29dedbcf8ccdfa0ccd4cf\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/base16ct/0.2.0/download\"],\n        strip_prefix = \"base16ct-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.base16ct-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-0.13.2\",\n        sha256 = \"46afbd2983a5d5a7bd740ccb198caf5b82f45c40c09c0eed36052d91cb92e719\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield/0.13.2/download\"],\n        strip_prefix = \"bitfield-0.13.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-0.13.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-0.14.0\",\n        sha256 = \"2d7e60934ceec538daadb9d8432424ed043a904d8e0243f3c6446bce549a46ac\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield/0.14.0/download\"],\n        strip_prefix = \"bitfield-0.14.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-0.14.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-struct-0.11.0\",\n        sha256 = \"d3ca019570363e800b05ad4fd890734f28ac7b72f563ad8a35079efb793616f8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield-struct/0.11.0/download\"],\n        strip_prefix = \"bitfield-struct-0.11.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-struct-0.11.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitflags-2.12.1\",\n        sha256 = \"84d7ced0ae9557296835c32bf1b1e02b44c746701f898460fb000d7eaa84f00a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitflags/2.12.1/download\"],\n        strip_prefix = \"bitflags-2.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitflags-2.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__block-buffer-0.10.4\",\n        sha256 = \"3078c7629b62d3f0439517fa394996acacc5cbc91c5a20d8c658e77abd503a71\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/block-buffer/0.10.4/download\"],\n        strip_prefix = \"block-buffer-0.10.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.block-buffer-0.10.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__byteorder-1.5.0\",\n        sha256 = \"1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/byteorder/1.5.0/download\"],\n        strip_prefix = \"byteorder-1.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.byteorder-1.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bytes-1.11.1\",\n        sha256 = \"1e748733b7cbc798e1434b6ac524f0c1ff2ab456fe201501e6497c8417a4fc33\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bytes/1.11.1/download\"],\n        strip_prefix = \"bytes-1.11.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bytes-1.11.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cfg-if-1.0.4\",\n        sha256 = \"9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cfg-if/1.0.4/download\"],\n        strip_prefix = \"cfg-if-1.0.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cfg-if-1.0.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cipher-0.4.4\",\n        sha256 = \"773f3b9af64447d2ce9850330c473515014aa235e6a783b02db81ff39e4a3dad\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cipher/0.4.4/download\"],\n        strip_prefix = \"cipher-0.4.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cipher-0.4.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap-4.6.1\",\n        sha256 = \"1ddb117e43bbf7dacf0a4190fef4d345b9bad68dfc649cb349e7d17d28428e51\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap/4.6.1/download\"],\n        strip_prefix = \"clap-4.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap-4.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_builder-4.6.0\",\n        sha256 = \"714a53001bf66416adb0e2ef5ac857140e7dc3a0c48fb28b2f10762fc4b5069f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_builder/4.6.0/download\"],\n        strip_prefix = \"clap_builder-4.6.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_builder-4.6.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_derive-4.6.1\",\n        sha256 = \"f2ce8604710f6733aa641a2b3731eaa1e8b3d9973d5e3565da11800813f997a9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_derive/4.6.1/download\"],\n        strip_prefix = \"clap_derive-4.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_derive-4.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_lex-1.1.0\",\n        sha256 = \"c8d4a3bb8b1e0c1050499d1815f5ab16d04f0959b233085fb31653fbfc9d98f9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_lex/1.1.0/download\"],\n        strip_prefix = \"clap_lex-1.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_lex-1.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__colorchoice-1.0.5\",\n        sha256 = \"1d07550c9036bf2ae0c684c4297d503f838287c83c53686d05370d0e139ae570\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/colorchoice/1.0.5/download\"],\n        strip_prefix = \"colorchoice-1.0.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.colorchoice-1.0.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__compiler_builtins-0.1.160\",\n        sha256 = \"6376049cfa92c0aa8b9ac95fae22184b981c658208d4ed8a1dc553cd83612895\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/compiler_builtins/0.1.160/download\"],\n        strip_prefix = \"compiler_builtins-0.1.160\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.compiler_builtins-0.1.160.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__const-oid-0.9.6\",\n        sha256 = \"c2459377285ad874054d797f3ccebf984978aa39129f6eafde5cdc8315b612f8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/const-oid/0.9.6/download\"],\n        strip_prefix = \"const-oid-0.9.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.const-oid-0.9.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-0.7.7\",\n        sha256 = \"8ec610d8f49840a5b376c69663b6369e71f4b34484b9b2eb29fb918d92516cb9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m/0.7.7/download\"],\n        strip_prefix = \"cortex-m-0.7.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-0.7.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-rt-0.7.5\",\n        sha256 = \"801d4dec46b34c299ccf6b036717ae0fce602faa4f4fe816d9013b9a7c9f5ba6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m-rt/0.7.5/download\"],\n        strip_prefix = \"cortex-m-rt-0.7.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-rt-0.7.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-rt-macros-0.7.5\",\n        sha256 = \"e37549a379a9e0e6e576fd208ee60394ccb8be963889eebba3ffe0980364f472\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m-rt-macros/0.7.5/download\"],\n        strip_prefix = \"cortex-m-rt-macros-0.7.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-rt-macros-0.7.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-semihosting-0.5.0\",\n        sha256 = \"c23234600452033cc77e4b761e740e02d2c4168e11dbf36ab14a0f58973592b0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m-semihosting/0.5.0/download\"],\n        strip_prefix = \"cortex-m-semihosting-0.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-semihosting-0.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cpufeatures-0.2.17\",\n        sha256 = \"59ed5838eebb26a2bb2e58f6d5b5316989ae9d08bab10e0e6d103e656d1b0280\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cpufeatures/0.2.17/download\"],\n        strip_prefix = \"cpufeatures-0.2.17\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cpufeatures-0.2.17.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crc-3.4.0\",\n        sha256 = \"5eb8a2a1cd12ab0d987a5d5e825195d372001a4094a0376319d5a0ad71c1ba0d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crc/3.4.0/download\"],\n        strip_prefix = \"crc-3.4.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crc-3.4.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crc-catalog-2.5.0\",\n        sha256 = \"217698eaf96b4a3f0bc4f3662aaa55bdf913cd54d7204591faa790070c6d0853\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crc-catalog/2.5.0/download\"],\n        strip_prefix = \"crc-catalog-2.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crc-catalog-2.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crc32fast-1.5.0\",\n        sha256 = \"9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crc32fast/1.5.0/download\"],\n        strip_prefix = \"crc32fast-1.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crc32fast-1.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__critical-section-1.2.0\",\n        sha256 = \"790eea4361631c5e7d22598ecd5723ff611904e3344ce8720784c93e3d83d40b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/critical-section/1.2.0/download\"],\n        strip_prefix = \"critical-section-1.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.critical-section-1.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crypto-bigint-0.5.5\",\n        sha256 = \"0dc92fb57ca44df6db8059111ab3af99a63d5d0f8375d9972e319a379c6bab76\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crypto-bigint/0.5.5/download\"],\n        strip_prefix = \"crypto-bigint-0.5.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crypto-bigint-0.5.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crypto-common-0.1.7\",\n        sha256 = \"78c8292055d1c1df0cce5d180393dc8cce0abec0a7102adb6c7b1eef6016d60a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crypto-common/0.1.7/download\"],\n        strip_prefix = \"crypto-common-0.1.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crypto-common-0.1.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ctr-0.9.2\",\n        sha256 = \"0369ee1ad671834580515889b80f2ea915f23b8be8d0daa4bbaf2ac5c7590835\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ctr/0.9.2/download\"],\n        strip_prefix = \"ctr-0.9.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ctr-0.9.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__der-0.7.10\",\n        sha256 = \"e7c1832837b905bbfb5101e07cc24c8deddf52f93225eee6ead5f4d63d53ddcb\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/der/0.7.10/download\"],\n        strip_prefix = \"der-0.7.10\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.der-0.7.10.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__digest-0.10.7\",\n        sha256 = \"9ed9a281f7bc9b7576e61468ba615a66a5c8cfdff42420a70aa82701a3b1e292\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/digest/0.10.7/download\"],\n        strip_prefix = \"digest-0.10.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.digest-0.10.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ecdsa-0.16.9\",\n        sha256 = \"ee27f32b5c5292967d2d4a9d7f1e0b0aed2c15daded5a60300e4abb9d8020bca\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ecdsa/0.16.9/download\"],\n        strip_prefix = \"ecdsa-0.16.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ecdsa-0.16.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__either-1.16.0\",\n        sha256 = \"91622ff5e7162018101f2fea40d6ebf4a78bbe5a49736a2020649edf9693679e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/either/1.16.0/download\"],\n        strip_prefix = \"either-1.16.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.either-1.16.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__elliptic-curve-0.13.8\",\n        sha256 = \"b5e6043086bf7973472e0c7dff2142ea0b680d30e18d9cc40f267efbf222bd47\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/elliptic-curve/0.13.8/download\"],\n        strip_prefix = \"elliptic-curve-0.13.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.elliptic-curve-0.13.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-crc-macros-1.0.0\",\n        sha256 = \"4f1c75747a43b086df1a87fb2a889590bc0725e0abf54bba6d0c4bf7bd9e762c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-crc-macros/1.0.0/download\"],\n        strip_prefix = \"embedded-crc-macros-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-crc-macros-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-0.2.7\",\n        sha256 = \"35949884794ad573cf46071e41c9b60efb0cb311e3ca01f7af807af1debc66ff\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal/0.2.7/download\"],\n        strip_prefix = \"embedded-hal-0.2.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-0.2.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-1.0.0\",\n        sha256 = \"361a90feb7004eca4019fb28352a9465666b24f840f5c3cddf0ff13920590b89\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-async-1.0.0\",\n        sha256 = \"0c4c685bbef7fe13c3c6dd4da26841ed3980ef33e841cddfa15ce8a8fb3f1884\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal-async/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-async-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-async-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-nb-1.0.0\",\n        sha256 = \"fba4268c14288c828995299e59b12babdbe170f6c6d73731af1b4648142e8605\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal-nb/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-nb-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-nb-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-io-0.6.1\",\n        sha256 = \"edd0f118536f44f5ccd48bcb8b111bdc3de888b58c74639dfb034a357d0f206d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-io/0.6.1/download\"],\n        strip_prefix = \"embedded-io-0.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-io-0.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-io-async-0.6.1\",\n        sha256 = \"3ff09972d4073aa8c299395be75161d582e7629cd663171d62af73c8d50dba3f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-io-async/0.6.1/download\"],\n        strip_prefix = \"embedded-io-async-0.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-io-async-0.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-storage-0.3.1\",\n        sha256 = \"a21dea9854beb860f3062d10228ce9b976da520a73474aed3171ec276bc0c032\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-storage/0.3.1/download\"],\n        strip_prefix = \"embedded-storage-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-storage-0.3.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__equivalent-1.0.2\",\n        sha256 = \"877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/equivalent/1.0.2/download\"],\n        strip_prefix = \"equivalent-1.0.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.equivalent-1.0.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__errno-0.3.14\",\n        sha256 = \"39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/errno/0.3.14/download\"],\n        strip_prefix = \"errno-0.3.14\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.errno-0.3.14.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ff-0.13.1\",\n        sha256 = \"c0b50bfb653653f9ca9095b427bed08ab8d75a137839d9ad64eb11810d5b6393\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ff/0.13.1/download\"],\n        strip_prefix = \"ff-0.13.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ff-0.13.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__flate2-1.1.9\",\n        sha256 = \"843fba2746e448b37e26a819579957415c8cef339bf08564fe8b7ddbd959573c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/flate2/1.1.9/download\"],\n        strip_prefix = \"flate2-1.1.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.flate2-1.1.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__foldhash-0.1.5\",\n        sha256 = \"d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/foldhash/0.1.5/download\"],\n        strip_prefix = \"foldhash-0.1.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.foldhash-0.1.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__fugit-0.3.9\",\n        sha256 = \"4e639847d312d9a82d2e75b0edcc1e934efcc64e6cb7aa94f0b1fbec0bc231d6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/fugit/0.3.9/download\"],\n        strip_prefix = \"fugit-0.3.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.fugit-0.3.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-0.3.32\",\n        sha256 = \"8b147ee9d1f6d097cef9ce628cd2ee62288d963e16fb287bd9286455b241382d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures/0.3.32/download\"],\n        strip_prefix = \"futures-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-channel-0.3.32\",\n        sha256 = \"07bbe89c50d7a535e539b8c17bc0b49bdb77747034daa8087407d655f3f7cc1d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-channel/0.3.32/download\"],\n        strip_prefix = \"futures-channel-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-channel-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-core-0.3.32\",\n        sha256 = \"7e3450815272ef58cec6d564423f6e755e25379b217b0bc688e295ba24df6b1d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-core/0.3.32/download\"],\n        strip_prefix = \"futures-core-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-core-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-executor-0.3.32\",\n        sha256 = \"baf29c38818342a3b26b5b923639e7b1f4a61fc5e76102d4b1981c6dc7a7579d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-executor/0.3.32/download\"],\n        strip_prefix = \"futures-executor-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-executor-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-io-0.3.32\",\n        sha256 = \"cecba35d7ad927e23624b22ad55235f2239cfa44fd10428eecbeba6d6a717718\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-io/0.3.32/download\"],\n        strip_prefix = \"futures-io-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-io-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-macro-0.3.32\",\n        sha256 = \"e835b70203e41293343137df5c0664546da5745f82ec9b84d40be8336958447b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-macro/0.3.32/download\"],\n        strip_prefix = \"futures-macro-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-macro-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-sink-0.3.32\",\n        sha256 = \"c39754e157331b013978ec91992bde1ac089843443c49cbc7f46150b0fad0893\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-sink/0.3.32/download\"],\n        strip_prefix = \"futures-sink-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-sink-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-task-0.3.32\",\n        sha256 = \"037711b3d59c33004d3856fbdc83b99d4ff37a24768fa1be9ce3538a1cde4393\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-task/0.3.32/download\"],\n        strip_prefix = \"futures-task-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-task-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-util-0.3.32\",\n        sha256 = \"389ca41296e6190b48053de0321d02a77f32f8a5d2461dd38762c0593805c6d6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-util/0.3.32/download\"],\n        strip_prefix = \"futures-util-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-util-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__gcd-2.3.0\",\n        sha256 = \"1d758ba1b47b00caf47f24925c0074ecb20d6dfcffe7f6d53395c0465674841a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/gcd/2.3.0/download\"],\n        strip_prefix = \"gcd-2.3.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.gcd-2.3.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__generic-array-0.14.7\",\n        sha256 = \"85649ca51fd72272d7821adaf274ad91c288277713d9c18820d8499a7ff69e9a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/generic-array/0.14.7/download\"],\n        strip_prefix = \"generic-array-0.14.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.generic-array-0.14.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ghash-0.5.1\",\n        sha256 = \"f0d8a4362ccb29cb0b265253fb0a2728f592895ee6854fd9bc13f2ffda266ff1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ghash/0.5.1/download\"],\n        strip_prefix = \"ghash-0.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ghash-0.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__group-0.13.0\",\n        sha256 = \"f0f9ef7462f7c099f518d754361858f86d8a07af53ba9af0fe635bbccb151a63\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/group/0.13.0/download\"],\n        strip_prefix = \"group-0.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.group-0.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hash32-0.3.1\",\n        sha256 = \"47d60b12902ba28e2730cd37e95b8c9223af2808df9e902d4df49588d1470606\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hash32/0.3.1/download\"],\n        strip_prefix = \"hash32-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hash32-0.3.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashbrown-0.15.5\",\n        sha256 = \"9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashbrown/0.15.5/download\"],\n        strip_prefix = \"hashbrown-0.15.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashbrown-0.15.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashbrown-0.17.1\",\n        sha256 = \"ed5909b6e89a2db4456e54cd5f673791d7eca6732202bbf2a9cc504fe2f9b84a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashbrown/0.17.1/download\"],\n        strip_prefix = \"hashbrown-0.17.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashbrown-0.17.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heapless-0.8.0\",\n        sha256 = \"0bfb9eb618601c89945a70e254898da93b13be0388091d42117462b265bb3fad\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heapless/0.8.0/download\"],\n        strip_prefix = \"heapless-0.8.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heapless-0.8.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heapless-0.9.3\",\n        sha256 = \"25ba4bd83f9415b58b4ed8dc5714c76e626a105be4646c02630ad730ad3b5aa4\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heapless/0.9.3/download\"],\n        strip_prefix = \"heapless-0.9.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heapless-0.9.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heck-0.5.0\",\n        sha256 = \"2304e00983f87ffb38b55b444b5e3b60a884b5d30c0fca7d82fe33449bbe55ea\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heck/0.5.0/download\"],\n        strip_prefix = \"heck-0.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heck-0.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hex-0.4.3\",\n        sha256 = \"7f24254aa9a54b5c858eaee2f5bccdb46aaf0e486a595ed5fd8f86ba55232a70\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hex/0.4.3/download\"],\n        strip_prefix = \"hex-0.4.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hex-0.4.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hex-literal-0.4.1\",\n        sha256 = \"6fe2267d4ed49bc07b63801559be28c718ea06c4738b7a03c94df7386d2cde46\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hex-literal/0.4.1/download\"],\n        strip_prefix = \"hex-literal-0.4.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hex-literal-0.4.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hmac-0.12.1\",\n        sha256 = \"6c49c37c09c17a53d937dfbb742eb3a961d65a994e6bcdcf37e7399d0cc8ab5e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hmac/0.12.1/download\"],\n        strip_prefix = \"hmac-0.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hmac-0.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__indexmap-2.14.0\",\n        sha256 = \"d466e9454f08e4a911e14806c24e16fba1b4c121d1ea474396f396069cf949d9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/indexmap/2.14.0/download\"],\n        strip_prefix = \"indexmap-2.14.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.indexmap-2.14.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__inout-0.1.4\",\n        sha256 = \"879f10e63c20629ecabbb64a8010319738c66a5cd0c29b02d63d272b03751d01\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/inout/0.1.4/download\"],\n        strip_prefix = \"inout-0.1.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.inout-0.1.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__is_terminal_polyfill-1.70.2\",\n        sha256 = \"a6cb138bb79a146c1bd460005623e142ef0181e3d0219cb493e02f7d08a35695\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/is_terminal_polyfill/1.70.2/download\"],\n        strip_prefix = \"is_terminal_polyfill-1.70.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.is_terminal_polyfill-1.70.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__itertools-0.14.0\",\n        sha256 = \"2b192c782037fadd9cfa75548310488aabdbf3d2da73885b31bd0abd03351285\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/itertools/0.14.0/download\"],\n        strip_prefix = \"itertools-0.14.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.itertools-0.14.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__k256-0.13.4\",\n        sha256 = \"f6e3919bbaa2945715f0bb6d3934a173d1e9a59ac23767fbaaef277265a7411b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/k256/0.13.4/download\"],\n        strip_prefix = \"k256-0.13.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.k256-0.13.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__keccak-0.1.6\",\n        sha256 = \"cb26cec98cce3a3d96cbb7bced3c4b16e3d13f27ec56dbd62cbc8f39cfb9d653\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/keccak/0.1.6/download\"],\n        strip_prefix = \"keccak-0.1.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.keccak-0.1.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__libc-0.2.186\",\n        sha256 = \"68ab91017fe16c622486840e4c83c9a37afeff978bd239b5293d61ece587de66\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/libc/0.2.186/download\"],\n        strip_prefix = \"libc-0.2.186\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.libc-0.2.186.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__linux-raw-sys-0.12.1\",\n        sha256 = \"32a66949e030da00e8c7d4434b251670a91556f4144941d37452769c25d58a53\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/linux-raw-sys/0.12.1/download\"],\n        strip_prefix = \"linux-raw-sys-0.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.linux-raw-sys-0.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__lock_api-0.4.14\",\n        sha256 = \"224399e74b87b5f3557511d98dff8b14089b3dadafcab6bb93eab67d3aace965\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/lock_api/0.4.14/download\"],\n        strip_prefix = \"lock_api-0.4.14\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.lock_api-0.4.14.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__log-0.4.31\",\n        sha256 = \"113b30b4cd05f7c06868fdb2854f66a7b9fece9a48425351cd532e810d74024f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/log/0.4.31/download\"],\n        strip_prefix = \"log-0.4.31\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.log-0.4.31.bazel\"),\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__mctp-0.2.0\",\n        commit = \"b134e145f93d634dff7eb9f2a01559273c687365\",\n        init_submodules = True,\n        remote = \"https://github.com/CodeConstruct/mctp-rs.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.mctp-0.2.0.bazel\"),\n        strip_prefix = \"mctp\",\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__mctp-estack-0.1.0\",\n        commit = \"b134e145f93d634dff7eb9f2a01559273c687365\",\n        init_submodules = True,\n        remote = \"https://github.com/CodeConstruct/mctp-rs.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.mctp-estack-0.1.0.bazel\"),\n        strip_prefix = \"mctp-estack\",\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__mctp-lib-0.1.0\",\n        commit = \"742fa0e991aa2b87509ff12739e011a674643d91\",\n        init_submodules = True,\n        remote = \"https://github.com/OpenPRoT/mctp-lib.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.mctp-lib-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memchr-2.8.1\",\n        sha256 = \"6b947ae49db0d222b1dbc6b113ce7248a3fc3a6ca21b696717bfc000ba4484d8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memchr/2.8.1/download\"],\n        strip_prefix = \"memchr-2.8.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memchr-2.8.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memo-map-0.3.3\",\n        sha256 = \"38d1115007560874e373613744c6fba374c17688327a71c1476d1a5954cc857b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memo-map/0.3.3/download\"],\n        strip_prefix = \"memo-map-0.3.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memo-map-0.3.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memoffset-0.9.1\",\n        sha256 = \"488016bfae457b036d996092f6cb448677611ce4449e970ceaf42695203f218a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memoffset/0.9.1/download\"],\n        strip_prefix = \"memoffset-0.9.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memoffset-0.9.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__minijinja-2.20.0\",\n        sha256 = \"2929e494b2280e1e18959bb2e121da03347ae896896fdfaceaab43c88a02803f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/minijinja/2.20.0/download\"],\n        strip_prefix = \"minijinja-2.20.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.minijinja-2.20.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__minimal-lexical-0.2.1\",\n        sha256 = \"68354c5c6bd36d73ff3feceb05efa59b6acb7626617f4962be322a825e61f79a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/minimal-lexical/0.2.1/download\"],\n        strip_prefix = \"minimal-lexical-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.minimal-lexical-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__miniz_oxide-0.8.9\",\n        sha256 = \"1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/miniz_oxide/0.8.9/download\"],\n        strip_prefix = \"miniz_oxide-0.8.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.miniz_oxide-0.8.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__mio-1.2.1\",\n        sha256 = \"02bd0af71c67b473010cbbc60715ee815645a4dc942899111f494b4b737d6fda\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/mio/1.2.1/download\"],\n        strip_prefix = \"mio-1.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.mio-1.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nb-0.1.3\",\n        sha256 = \"801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/nb/0.1.3/download\"],\n        strip_prefix = \"nb-0.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.nb-0.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nb-1.1.0\",\n        sha256 = \"8d5439c4ad607c3c23abf66de8c8bf57ba8adcd1f129e699851a6e43935d339d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/nb/1.1.0/download\"],\n        strip_prefix = \"nb-1.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.nb-1.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nom-7.1.3\",\n        sha256 = \"d273983c5a657a70a3e8f2a01329822f3b8c8172b73826411a55751e404a0a4a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/nom/7.1.3/download\"],\n        strip_prefix = \"nom-7.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.nom-7.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__object-0.37.3\",\n        sha256 = \"ff76201f031d8863c38aa7f905eca4f53abbfa15f609db4277d44cd8938f33fe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/object/0.37.3/download\"],\n        strip_prefix = \"object-0.37.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.object-0.37.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__once_cell_polyfill-1.70.2\",\n        sha256 = \"384b8ab6d37215f3c5301a95a4accb5d64aa607f1fcb26a11b5303878451b4fe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/once_cell_polyfill/1.70.2/download\"],\n        strip_prefix = \"once_cell_polyfill-1.70.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.once_cell_polyfill-1.70.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__opaque-debug-0.3.1\",\n        sha256 = \"c08d65885ee38876c4f86fa503fb49d7b507c2b62552df7c70b2fce627e06381\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/opaque-debug/0.3.1/download\"],\n        strip_prefix = \"opaque-debug-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.opaque-debug-0.3.1.bazel\"),\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__openprot-hal-blocking-0.1.0\",\n        commit = \"c6cd23a56f3cc7945b062ea1bcdabf3af0dba82d\",\n        init_submodules = True,\n        remote = \"https://github.com/rusty1968/openprot.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.openprot-hal-blocking-0.1.0.bazel\"),\n        strip_prefix = \"hal/blocking\",\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__p256-0.13.2\",\n        sha256 = \"c9863ad85fa8f4460f9c48cb909d38a0d689dba1f6f6988a5e3e0d31071bcd4b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/p256/0.13.2/download\"],\n        strip_prefix = \"p256-0.13.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.p256-0.13.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__p384-0.13.1\",\n        sha256 = \"fe42f1670a52a47d448f14b6a5c61dd78fce51856e68edaa38f7ae3a46b8d6b6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/p384/0.13.1/download\"],\n        strip_prefix = \"p384-0.13.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.p384-0.13.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__panic-halt-1.0.0\",\n        sha256 = \"a513e167849a384b7f9b746e517604398518590a9142f4846a32e3c2a4de7b11\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/panic-halt/1.0.0/download\"],\n        strip_prefix = \"panic-halt-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.panic-halt-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__parking_lot-0.12.5\",\n        sha256 = \"93857453250e3077bd71ff98b6a65ea6621a19bb0f559a85248955ac12c45a1a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/parking_lot/0.12.5/download\"],\n        strip_prefix = \"parking_lot-0.12.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.parking_lot-0.12.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__parking_lot_core-0.9.12\",\n        sha256 = \"2621685985a2ebf1c516881c026032ac7deafcda1a2c9b7850dc81e3dfcb64c1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/parking_lot_core/0.9.12/download\"],\n        strip_prefix = \"parking_lot_core-0.9.12\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.parking_lot_core-0.9.12.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__paste-1.0.15\",\n        sha256 = \"57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/paste/1.0.15/download\"],\n        strip_prefix = \"paste-1.0.15\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.paste-1.0.15.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest-2.8.6\",\n        sha256 = \"e0848c601009d37dfa3430c4666e147e49cdcf1b92ecd3e63657d8a5f19da662\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest/2.8.6/download\"],\n        strip_prefix = \"pest-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_derive-2.8.6\",\n        sha256 = \"11f486f1ea21e6c10ed15d5a7c77165d0ee443402f0780849d1768e7d9d6fe77\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_derive/2.8.6/download\"],\n        strip_prefix = \"pest_derive-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_derive-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_generator-2.8.6\",\n        sha256 = \"8040c4647b13b210a963c1ed407c1ff4fdfa01c31d6d2a098218702e6664f94f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_generator/2.8.6/download\"],\n        strip_prefix = \"pest_generator-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_generator-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_meta-2.8.6\",\n        sha256 = \"89815c69d36021a140146f26659a81d6c2afa33d216d736dd4be5381a7362220\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_meta/2.8.6/download\"],\n        strip_prefix = \"pest_meta-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_meta-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pin-project-lite-0.2.17\",\n        sha256 = \"a89322df9ebe1c1578d689c92318e070967d1042b512afbe49518723f4e6d5cd\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pin-project-lite/0.2.17/download\"],\n        strip_prefix = \"pin-project-lite-0.2.17\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pin-project-lite-0.2.17.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__polyval-0.6.2\",\n        sha256 = \"9d1fe60d06143b2430aa532c94cfe9e29783047f06c0d7fd359a9a51b729fa25\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/polyval/0.6.2/download\"],\n        strip_prefix = \"polyval-0.6.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.polyval-0.6.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__primeorder-0.13.6\",\n        sha256 = \"353e1ca18966c16d9deb1c69278edbc5f194139612772bd9537af60ac231e1e6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/primeorder/0.13.6/download\"],\n        strip_prefix = \"primeorder-0.13.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.primeorder-0.13.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__proc-macro2-1.0.106\",\n        sha256 = \"8fd00f0bb2e90d81d1044c2b32617f68fcb9fa3bb7640c23e9c748e53fb30934\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/proc-macro2/1.0.106/download\"],\n        strip_prefix = \"proc-macro2-1.0.106\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.proc-macro2-1.0.106.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__prost-0.13.5\",\n        sha256 = \"2796faa41db3ec313a31f7624d9286acf277b52de526150b7e69f3debf891ee5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/prost/0.13.5/download\"],\n        strip_prefix = \"prost-0.13.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.prost-0.13.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__prost-derive-0.13.5\",\n        sha256 = \"8a56d757972c98b346a9b766e3f02746cde6dd1cd1d1d563472929fdd74bec4d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/prost-derive/0.13.5/download\"],\n        strip_prefix = \"prost-derive-0.13.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.prost-derive-0.13.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__quote-1.0.45\",\n        sha256 = \"41f2619966050689382d2b44f664f4bc593e129785a36d6ee376ddf37259b924\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/quote/1.0.45/download\"],\n        strip_prefix = \"quote-1.0.45\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.quote-1.0.45.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rand_core-0.6.4\",\n        sha256 = \"ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rand_core/0.6.4/download\"],\n        strip_prefix = \"rand_core-0.6.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rand_core-0.6.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rand_core-0.9.5\",\n        sha256 = \"76afc826de14238e6e8c374ddcc1fa19e374fd8dd986b0d2af0d02377261d83c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rand_core/0.9.5/download\"],\n        strip_prefix = \"rand_core-0.9.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rand_core-0.9.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__redox_syscall-0.5.18\",\n        sha256 = \"ed2bf2547551a7053d6fdfafda3f938979645c44812fbfcda098faae3f1a362d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/redox_syscall/0.5.18/download\"],\n        strip_prefix = \"redox_syscall-0.5.18\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.redox_syscall-0.5.18.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = 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[\"https://static.crates.io/crates/riscv/0.12.1/download\"],\n        strip_prefix = \"riscv-0.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.13.0\",\n        sha256 = \"afa3cdbeccae4359f6839a00e8b77e5736caa200ba216caf38d24e4c16e2b586\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.13.0/download\"],\n        strip_prefix = \"riscv-0.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-macros-0.1.0\",\n        sha256 = \"f265be5d634272320a7de94cea15c22a3bfdd4eb42eb43edc528415f066a1f25\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-macros/0.1.0/download\"],\n        strip_prefix = \"riscv-macros-0.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-macros-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-macros-0.2.0\",\n        sha256 = \"e8c4aa1ea1af6dcc83a61be12e8189f9b293c3ba5a487778a4cd89fb060fdbbc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-macros/0.2.0/download\"],\n        strip_prefix = \"riscv-macros-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-macros-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-pac-0.2.0\",\n        sha256 = \"8188909339ccc0c68cfb5a04648313f09621e8b87dc03095454f1a11f6c5d436\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-pac/0.2.0/download\"],\n        strip_prefix = \"riscv-pac-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-pac-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-rt-0.12.2\",\n        sha256 = \"c0d35e32cf1383183e8885d8a9aa4402a087fd094dc34c2cb6df6687d0229dfe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-rt/0.12.2/download\"],\n        strip_prefix = \"riscv-rt-0.12.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-rt-0.12.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-rt-macros-0.2.2\",\n        sha256 = \"30f19a85fe107b65031e0ba8ec60c34c2494069fe910d6c297f5e7cb5a6f76d0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-rt-macros/0.2.2/download\"],\n        strip_prefix = \"riscv-rt-macros-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-rt-macros-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-semihosting-0.1.3\",\n        sha256 = \"1086dd4bcc13de1cb14b93849411e3466de7e5907d2d8eb269032536e93facc6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-semihosting/0.1.3/download\"],\n        strip_prefix = \"riscv-semihosting-0.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-semihosting-0.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustc-demangle-0.1.27\",\n        sha256 = \"b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustc-demangle/0.1.27/download\"],\n        strip_prefix = \"rustc-demangle-0.1.27\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustc-demangle-0.1.27.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustc_version-0.2.3\",\n        sha256 = \"138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustc_version/0.2.3/download\"],\n        strip_prefix = \"rustc_version-0.2.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustc_version-0.2.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustix-1.1.4\",\n        sha256 = \"b6fe4565b9518b83ef4f91bb47ce29620ca828bd32cb7e408f0062e9930ba190\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustix/1.1.4/download\"],\n        strip_prefix = \"rustix-1.1.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustix-1.1.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ruzstd-0.8.3\",\n        sha256 = \"a7c1c839d570d835527c9a5e4db7cb2198683a988cb9d7293fc8674e6bd58fc8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ruzstd/0.8.3/download\"],\n        strip_prefix = \"ruzstd-0.8.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ruzstd-0.8.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__scopeguard-1.2.0\",\n        sha256 = \"94143f37725109f92c262ed2cf5e59bce7498c01bcc1502d7b9afe439a4e9f49\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/scopeguard/1.2.0/download\"],\n        strip_prefix = \"scopeguard-1.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.scopeguard-1.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sec1-0.7.3\",\n        sha256 = \"d3e97a565f76233a6003f9f5c54be1d9c5bdfa3eccfb189469f11ec4901c47dc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sec1/0.7.3/download\"],\n        strip_prefix = \"sec1-0.7.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sec1-0.7.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__semver-0.9.0\",\n        sha256 = \"1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/semver/0.9.0/download\"],\n        strip_prefix = \"semver-0.9.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.semver-0.9.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__semver-parser-0.7.0\",\n        sha256 = \"388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/semver-parser/0.7.0/download\"],\n        strip_prefix = \"semver-parser-0.7.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.semver-parser-0.7.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde-1.0.228\",\n        sha256 = \"9a8e94ea7f378bd32cbbd37198a4a91436180c5bb472411e48b5ec2e2124ae9e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde/1.0.228/download\"],\n        strip_prefix = \"serde-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_core-1.0.228\",\n        sha256 = \"41d385c7d4ca58e59fc732af25c3983b67ac852c1a25000afe1175de458b67ad\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_core/1.0.228/download\"],\n        strip_prefix = \"serde_core-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_core-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_derive-1.0.228\",\n        sha256 = \"d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_derive/1.0.228/download\"],\n        strip_prefix = \"serde_derive-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_derive-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_json5-0.2.1\",\n        sha256 = \"5d34d03f54462862f2a42918391c9526337f53171eaa4d8894562be7f252edd3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_json5/0.2.1/download\"],\n        strip_prefix = \"serde_json5-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_json5-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sha2-0.10.9\",\n        sha256 = \"a7507d819769d01a365ab707794a4084392c824f54a7a6a7862f8c3d0892b283\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sha2/0.10.9/download\"],\n        strip_prefix = \"sha2-0.10.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sha2-0.10.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sha3-0.10.9\",\n        sha256 = \"77fd7028345d415a4034cf8777cd4f8ab1851274233b45f84e3d955502d93874\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sha3/0.10.9/download\"],\n        strip_prefix = \"sha3-0.10.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sha3-0.10.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__signal-hook-registry-1.4.8\",\n        sha256 = \"c4db69cba1110affc0e9f7bcd48bbf87b3f4fc7c61fc9155afd4c469eb3d6c1b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/signal-hook-registry/1.4.8/download\"],\n        strip_prefix = \"signal-hook-registry-1.4.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.signal-hook-registry-1.4.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__signature-2.2.0\",\n        sha256 = \"77549399552de45a898a580c1b41d445bf730df867cc44e6c0233bbc4b8329de\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/signature/2.2.0/download\"],\n        strip_prefix = \"signature-2.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.signature-2.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__simd-adler32-0.3.9\",\n        sha256 = \"703d5c7ef118737c72f1af64ad2f6f8c5e1921f818cdcb97b8fe6fc69bf66214\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/simd-adler32/0.3.9/download\"],\n        strip_prefix = \"simd-adler32-0.3.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.simd-adler32-0.3.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__slab-0.4.12\",\n        sha256 = \"0c790de23124f9ab44544d7ac05d60440adc586479ce501c1d6d7da3cd8c9cf5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/slab/0.4.12/download\"],\n        strip_prefix = \"slab-0.4.12\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.slab-0.4.12.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__smallvec-1.15.1\",\n        sha256 = \"67b1b7a3b5fe4f1376887184045fcf45c69e92af734b7aaddc05fb777b6fbd03\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/smallvec/1.15.1/download\"],\n        strip_prefix = \"smallvec-1.15.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.smallvec-1.15.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__smbus-pec-1.0.1\",\n        sha256 = \"ca0763a680cd5d72b28f7bfc8a054c117d8841380a6ad4f72f05bd2a34217d3e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/smbus-pec/1.0.1/download\"],\n        strip_prefix = \"smbus-pec-1.0.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.smbus-pec-1.0.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__smlang-0.8.0\",\n        sha256 = \"1de84f9f80bbe6272174e2bfdb8cf7ce4815b218038a42161c2f21c1d872c215\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/smlang/0.8.0/download\"],\n        strip_prefix = \"smlang-0.8.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.smlang-0.8.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__smlang-macros-0.8.0\",\n        sha256 = \"231b4425dcc43afc7e18c34e7c6738cd252d42d91d909c948df14107c9ae79f1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/smlang-macros/0.8.0/download\"],\n        strip_prefix = \"smlang-macros-0.8.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.smlang-macros-0.8.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__socket2-0.6.4\",\n        sha256 = \"52d1cfed4120b4d927bf7c0f86d2087a4a7d6027c906d9f9d525a80573b9be51\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/socket2/0.6.4/download\"],\n        strip_prefix = \"socket2-0.6.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.socket2-0.6.4.bazel\"),\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__spdm-lib-0.1.0\",\n        commit = \"41d81717f5d2b4d6b004819a829ae015e44febce\",\n        init_submodules = True,\n        remote = \"https://github.com/OpenPRoT/spdm-lib.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.spdm-lib-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__stable_deref_trait-1.2.1\",\n        sha256 = \"6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/stable_deref_trait/1.2.1/download\"],\n        strip_prefix = \"stable_deref_trait-1.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.stable_deref_trait-1.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__string_morph-0.1.0\",\n        sha256 = \"183aaf7fa637cc7b5f54c45b8f7cb6e8d73831f9f75a56b6defa5bf8c51d1699\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/string_morph/0.1.0/download\"],\n        strip_prefix = \"string_morph-0.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.string_morph-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__strsim-0.11.1\",\n        sha256 = \"7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/strsim/0.11.1/download\"],\n        strip_prefix = \"strsim-0.11.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.strsim-0.11.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__subtle-2.6.1\",\n        sha256 = \"13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/subtle/2.6.1/download\"],\n        strip_prefix = \"subtle-2.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.subtle-2.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__syn-1.0.109\",\n        sha256 = \"72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/syn/1.0.109/download\"],\n        strip_prefix = \"syn-1.0.109\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.syn-1.0.109.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__syn-2.0.117\",\n        sha256 = \"e665b8803e7b1d2a727f4023456bbbbe74da67099c585258af0ad9c5013b9b99\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/syn/2.0.117/download\"],\n        strip_prefix = \"syn-2.0.117\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.syn-2.0.117.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__terminal_size-0.4.4\",\n        sha256 = \"230a1b821ccbd75b185820a1f1ff7b14d21da1e442e22c0863ea5f08771a8874\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/terminal_size/0.4.4/download\"],\n        strip_prefix = \"terminal_size-0.4.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.terminal_size-0.4.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__thiserror-2.0.18\",\n        sha256 = \"4288b5bcbc7920c07a1149a35cf9590a2aa808e0bc1eafaade0b80947865fbc4\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/thiserror/2.0.18/download\"],\n        strip_prefix = \"thiserror-2.0.18\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.thiserror-2.0.18.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__thiserror-impl-2.0.18\",\n        sha256 = \"ebc4ee7f67670e9b64d05fa4253e753e016c6c95ff35b89b7941d6b856dec1d5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/thiserror-impl/2.0.18/download\"],\n        strip_prefix = \"thiserror-impl-2.0.18\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.thiserror-impl-2.0.18.bazel\"),\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__tock-registers-0.9.0\",\n        commit = \"9554639b17501a9f5940cef7a1770a0823e790c3\",\n        init_submodules = True,\n        remote = \"https://github.com/tock/tock.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.tock-registers-0.9.0.bazel\"),\n        strip_prefix = \"libraries/tock-register-interface\",\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__tokio-1.52.3\",\n        sha256 = \"8fc7f01b389ac15039e4dc9531aa973a135d7a4135281b12d7c1bc79fd57fffe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/tokio/1.52.3/download\"],\n        strip_prefix = \"tokio-1.52.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.tokio-1.52.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__tokio-macros-2.7.0\",\n        sha256 = \"385a6cb71ab9ab790c5fe8d67f1645e6c450a7ce006a33de03daa956cf70a496\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/tokio-macros/2.7.0/download\"],\n        strip_prefix = \"tokio-macros-2.7.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.tokio-macros-2.7.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__tokio-util-0.7.18\",\n        sha256 = \"9ae9cec805b01e8fc3fd2fe289f89149a9b66dd16786abd8b19cfa7b48cb0098\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/tokio-util/0.7.18/download\"],\n        strip_prefix = \"tokio-util-0.7.18\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.tokio-util-0.7.18.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__twox-hash-2.1.2\",\n        sha256 = \"9ea3136b675547379c4bd395ca6b938e5ad3c3d20fad76e7fe85f9e0d011419c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/twox-hash/2.1.2/download\"],\n        strip_prefix = \"twox-hash-2.1.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.twox-hash-2.1.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__typenum-1.20.1\",\n        sha256 = \"b6f5e870be6c3b371b77fe0ee0bafb859fa4964b4404c27de1d380043c4dda20\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/typenum/1.20.1/download\"],\n        strip_prefix = \"typenum-1.20.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.typenum-1.20.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ucd-trie-0.1.7\",\n        sha256 = \"2896d95c02a80c6d6a5d6e953d479f5ddf2dfdb6a244441010e373ac0fb88971\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ucd-trie/0.1.7/download\"],\n        strip_prefix = \"ucd-trie-0.1.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ucd-trie-0.1.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__unicode-ident-1.0.24\",\n        sha256 = \"e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/unicode-ident/1.0.24/download\"],\n        strip_prefix = \"unicode-ident-1.0.24\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.unicode-ident-1.0.24.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__universal-hash-0.5.1\",\n        sha256 = \"fc1de2c688dc15305988b563c3854064043356019f97a4b46276fe734c4f07ea\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/universal-hash/0.5.1/download\"],\n        strip_prefix = \"universal-hash-0.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.universal-hash-0.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__utf8parse-0.2.2\",\n        sha256 = \"06abde3611657adf66d383f00b093d7faecc7fa57071cce2578660c9f1010821\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/utf8parse/0.2.2/download\"],\n        strip_prefix = \"utf8parse-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.utf8parse-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__uuid-1.23.2\",\n        sha256 = \"d258b83ceec21034727ecee8c382cfa6c3e133699b0742c64571814fb420c9f7\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/uuid/1.23.2/download\"],\n        strip_prefix = \"uuid-1.23.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.uuid-1.23.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__vcell-0.1.3\",\n        sha256 = \"77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/vcell/0.1.3/download\"],\n        strip_prefix = \"vcell-0.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.vcell-0.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__version_check-0.9.5\",\n        sha256 = \"0b928f33d975fc6ad9f86c8f283853ad26bdd5b10b7f1542aa2fa15e2289105a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/version_check/0.9.5/download\"],\n        strip_prefix = \"version_check-0.9.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.version_check-0.9.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__void-1.0.2\",\n        sha256 = \"6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/void/1.0.2/download\"],\n        strip_prefix = \"void-1.0.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.void-1.0.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__volatile-register-0.2.2\",\n        sha256 = \"de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/volatile-register/0.2.2/download\"],\n        strip_prefix = \"volatile-register-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.volatile-register-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__wasi-0.11.1-wasi-snapshot-preview1\",\n        sha256 = \"ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/wasi/0.11.1+wasi-snapshot-preview1/download\"],\n        strip_prefix = \"wasi-0.11.1+wasi-snapshot-preview1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.wasi-0.11.1+wasi-snapshot-preview1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__windows-link-0.2.1\",\n        sha256 = \"f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/windows-link/0.2.1/download\"],\n        strip_prefix = \"windows-link-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.windows-link-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__windows-sys-0.61.2\",\n        sha256 = \"ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/windows-sys/0.61.2/download\"],\n        strip_prefix = \"windows-sys-0.61.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.windows-sys-0.61.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zerocopy-0.8.50\",\n        sha256 = \"3b065d4f0e55f82fae73202e189638116a87c55ab6b8e6c2721e13dd9d854ad1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zerocopy/0.8.50/download\"],\n        strip_prefix = \"zerocopy-0.8.50\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zerocopy-0.8.50.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zerocopy-derive-0.8.50\",\n        sha256 = \"0b631b19d36a892ab55420c92dbc83ccd79274f25be714855d3074aa71cab639\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zerocopy-derive/0.8.50/download\"],\n        strip_prefix = \"zerocopy-derive-0.8.50\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zerocopy-derive-0.8.50.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zeroize-1.8.2\",\n        sha256 = \"b97154e67e32c85465826e8bcc1c59429aaaf107c1e4a9e53c8d8ccd5eff88d0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zeroize/1.8.2/download\"],\n        strip_prefix = \"zeroize-1.8.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zeroize-1.8.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__zeroize_derive-1.4.3\",\n        sha256 = \"85a5b4158499876c763cb03bc4e49185d3cccbabb15b33c627f7884f43db852e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/zeroize_derive/1.4.3/download\"],\n        strip_prefix = \"zeroize_derive-1.4.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.zeroize_derive-1.4.3.bazel\"),\n    )\n\n    return [\n       struct(repo=\"rust_crates__aes-0.8.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__aes-gcm-0.10.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__aligned-0.4.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__anyhow-1.0.102\", is_dev_dep = False),\n       struct(repo=\"rust_crates__bitfield-0.14.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__bitfield-struct-0.11.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__bitflags-2.12.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__byteorder-1.5.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cfg-if-1.0.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cipher-0.4.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__clap-4.6.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__compiler_builtins-0.1.160\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cortex-m-0.7.7\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cortex-m-rt-0.7.5\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cortex-m-semihosting-0.5.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__ctr-0.9.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__ecdsa-0.16.9\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-hal-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-hal-async-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-hal-nb-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-io-0.6.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__embedded-storage-0.3.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__fugit-0.3.9\", is_dev_dep = False),\n       struct(repo=\"rust_crates__futures-0.3.32\", is_dev_dep = False),\n       struct(repo=\"rust_crates__heapless-0.9.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__hex-0.4.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__hex-literal-0.4.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__hmac-0.12.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__k256-0.13.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__log-0.4.31\", is_dev_dep = False),\n       struct(repo=\"rust_crates__mctp-0.2.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__mctp-lib-0.1.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__memoffset-0.9.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__minijinja-2.20.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__nb-1.1.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__nom-7.1.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__object-0.37.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__openprot-hal-blocking-0.1.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__p256-0.13.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__p384-0.13.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__panic-halt-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__paste-1.0.15\", is_dev_dep = False),\n       struct(repo=\"rust_crates__proc-macro2-1.0.106\", is_dev_dep = False),\n       struct(repo=\"rust_crates__prost-0.13.5\", is_dev_dep = False),\n       struct(repo=\"rust_crates__quote-1.0.45\", is_dev_dep = False),\n       struct(repo=\"rust_crates__rand_core-0.9.5\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-0.12.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-rt-0.12.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-semihosting-0.1.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__rustc-demangle-0.1.27\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sec1-0.7.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde-1.0.228\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde_derive-1.0.228\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde_json5-0.2.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sha2-0.10.9\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sha3-0.10.9\", is_dev_dep = False),\n       struct(repo=\"rust_crates__smlang-0.8.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__spdm-lib-0.1.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__subtle-2.6.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__syn-1.0.109\", is_dev_dep = False),\n       struct(repo=\"rust_crates__syn-2.0.117\", is_dev_dep = False),\n       struct(repo=\"rust_crates__thiserror-2.0.18\", is_dev_dep = False),\n       struct(repo=\"rust_crates__tock-registers-0.9.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__tokio-1.52.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__tokio-util-0.7.18\", is_dev_dep = False),\n       struct(repo=\"rust_crates__vcell-0.1.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__zerocopy-0.8.50\", is_dev_dep = False),\n       struct(repo=\"rust_crates__zeroize-1.8.2\", is_dev_dep = False),\n    ]\n"
+                "defs.bzl": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\"\"\"\n# `crates_repository` API\n\n- [aliases](#aliases)\n- [crate_deps](#crate_deps)\n- [all_crate_deps](#all_crate_deps)\n- [crate_repositories](#crate_repositories)\n\n\"\"\"\n\nload(\"@bazel_tools//tools/build_defs/repo:git.bzl\", \"git_repository\")\nload(\"@bazel_tools//tools/build_defs/repo:http.bzl\", \"http_archive\")\nload(\"@bazel_tools//tools/build_defs/repo:utils.bzl\", \"maybe\")\nload(\"@bazel_skylib//lib:selects.bzl\", \"selects\")\nload(\"@rules_rust//crate_universe/private:local_crate_mirror.bzl\", \"local_crate_mirror\")\n\n###############################################################################\n# MACROS API\n###############################################################################\n\n# An identifier that represent common dependencies (unconditional).\n_COMMON_CONDITION = \"\"\n\ndef _flatten_dependency_maps(all_dependency_maps):\n    \"\"\"Flatten a list of dependency maps into one dictionary.\n\n    Dependency maps have the following structure:\n\n    ```python\n    DEPENDENCIES_MAP = {\n        # The first key in the map is a Bazel package\n        # name of the workspace this file is defined in.\n        \"workspace_member_package\": {\n\n            # Not all dependencies are supported for all platforms.\n            # the condition key is the condition required to be true\n            # on the host platform.\n            \"condition\": {\n\n                # An alias to a crate target.     # The label of the crate target the\n                # Aliases are only crate names.   # package name refers to.\n                \"package_name\":                   \"@full//:label\",\n            }\n        }\n    }\n    ```\n\n    Args:\n        all_dependency_maps (list): A list of dicts as described above\n\n    Returns:\n        dict: A dictionary as described above\n    \"\"\"\n    dependencies = {}\n\n    for workspace_deps_map in all_dependency_maps:\n        for pkg_name, conditional_deps_map in workspace_deps_map.items():\n            if pkg_name not in dependencies:\n                non_frozen_map = dict()\n                for key, values in conditional_deps_map.items():\n                    non_frozen_map.update({key: dict(values.items())})\n                dependencies.setdefault(pkg_name, non_frozen_map)\n                continue\n\n            for condition, deps_map in conditional_deps_map.items():\n                # If the condition has not been recorded, do so and continue\n                if condition not in dependencies[pkg_name]:\n                    dependencies[pkg_name].setdefault(condition, dict(deps_map.items()))\n                    continue\n\n                # Alert on any miss-matched dependencies\n                inconsistent_entries = []\n                for crate_name, crate_label in deps_map.items():\n                    existing = dependencies[pkg_name][condition].get(crate_name)\n                    if existing and existing != crate_label:\n                        inconsistent_entries.append((crate_name, existing, crate_label))\n                    dependencies[pkg_name][condition].update({crate_name: crate_label})\n\n    return dependencies\n\ndef crate_deps(deps, package_name = None):\n    \"\"\"Finds the fully qualified label of the requested crates for the package where this macro is called.\n\n    Args:\n        deps (list): The desired list of crate targets.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()`.\n\n    Returns:\n        list: A list of labels to generated rust targets (str)\n    \"\"\"\n\n    if not deps:\n        return []\n\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Join both sets of dependencies\n    dependencies = _flatten_dependency_maps([\n        _NORMAL_DEPENDENCIES,\n        _NORMAL_DEV_DEPENDENCIES,\n        _PROC_MACRO_DEPENDENCIES,\n        _PROC_MACRO_DEV_DEPENDENCIES,\n        _BUILD_DEPENDENCIES,\n        _BUILD_PROC_MACRO_DEPENDENCIES,\n    ]).pop(package_name, {})\n\n    # Combine all conditional packages so we can easily index over a flat list\n    # TODO: Perhaps this should actually return select statements and maintain\n    # the conditionals of the dependencies\n    flat_deps = {}\n    for deps_set in dependencies.values():\n        for crate_name, crate_label in deps_set.items():\n            flat_deps.update({crate_name: crate_label})\n\n    missing_crates = []\n    crate_targets = []\n    for crate_target in deps:\n        if crate_target not in flat_deps:\n            missing_crates.append(crate_target)\n        else:\n            crate_targets.append(flat_deps[crate_target])\n\n    if missing_crates:\n        fail(\"Could not find crates `{}` among dependencies of `{}`. Available dependencies were `{}`\".format(\n            missing_crates,\n            package_name,\n            dependencies,\n        ))\n\n    return crate_targets\n\ndef all_crate_deps(\n        normal = False, \n        normal_dev = False, \n        proc_macro = False, \n        proc_macro_dev = False,\n        build = False,\n        build_proc_macro = False,\n        package_name = None):\n    \"\"\"Finds the fully qualified label of all requested direct crate dependencies \\\n    for the package where this macro is called.\n\n    If no parameters are set, all normal dependencies are returned. Setting any one flag will\n    otherwise impact the contents of the returned list.\n\n    Args:\n        normal (bool, optional): If True, normal dependencies are included in the\n            output list.\n        normal_dev (bool, optional): If True, normal dev dependencies will be\n            included in the output list.\n        proc_macro (bool, optional): If True, proc_macro dependencies are included\n            in the output list.\n        proc_macro_dev (bool, optional): If True, dev proc_macro dependencies are\n            included in the output list.\n        build (bool, optional): If True, build dependencies are included\n            in the output list.\n        build_proc_macro (bool, optional): If True, build proc_macro dependencies are\n            included in the output list.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()` when unset.\n\n    Returns:\n        list: A list of labels to generated rust targets (str)\n    \"\"\"\n\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Determine the relevant maps to use\n    all_dependency_maps = []\n    if normal:\n        all_dependency_maps.append(_NORMAL_DEPENDENCIES)\n    if normal_dev:\n        all_dependency_maps.append(_NORMAL_DEV_DEPENDENCIES)\n    if proc_macro:\n        all_dependency_maps.append(_PROC_MACRO_DEPENDENCIES)\n    if proc_macro_dev:\n        all_dependency_maps.append(_PROC_MACRO_DEV_DEPENDENCIES)\n    if build:\n        all_dependency_maps.append(_BUILD_DEPENDENCIES)\n    if build_proc_macro:\n        all_dependency_maps.append(_BUILD_PROC_MACRO_DEPENDENCIES)\n\n    # Default to always using normal dependencies\n    if not all_dependency_maps:\n        all_dependency_maps.append(_NORMAL_DEPENDENCIES)\n\n    dependencies = _flatten_dependency_maps(all_dependency_maps).pop(package_name, None)\n\n    if not dependencies:\n        if dependencies == None:\n            fail(\"Tried to get all_crate_deps for package \" + package_name + \" but that package had no Cargo.toml file\")\n        else:\n            return []\n\n    crate_deps = list(dependencies.pop(_COMMON_CONDITION, {}).values())\n    for condition, deps in dependencies.items():\n        crate_deps += selects.with_or({\n            tuple(_CONDITIONS[condition]): deps.values(),\n            \"//conditions:default\": [],\n        })\n\n    return crate_deps\n\ndef aliases(\n        normal = False,\n        normal_dev = False,\n        proc_macro = False,\n        proc_macro_dev = False,\n        build = False,\n        build_proc_macro = False,\n        package_name = None):\n    \"\"\"Produces a map of Crate alias names to their original label\n\n    If no dependency kinds are specified, `normal` and `proc_macro` are used by default.\n    Setting any one flag will otherwise determine the contents of the returned dict.\n\n    Args:\n        normal (bool, optional): If True, normal dependencies are included in the\n            output list.\n        normal_dev (bool, optional): If True, normal dev dependencies will be\n            included in the output list..\n        proc_macro (bool, optional): If True, proc_macro dependencies are included\n            in the output list.\n        proc_macro_dev (bool, optional): If True, dev proc_macro dependencies are\n            included in the output list.\n        build (bool, optional): If True, build dependencies are included\n            in the output list.\n        build_proc_macro (bool, optional): If True, build proc_macro dependencies are\n            included in the output list.\n        package_name (str, optional): The package name of the set of dependencies to look up.\n            Defaults to `native.package_name()` when unset.\n\n    Returns:\n        dict: The aliases of all associated packages\n    \"\"\"\n    if package_name == None:\n        package_name = native.package_name()\n\n    # Determine the relevant maps to use\n    all_aliases_maps = []\n    if normal:\n        all_aliases_maps.append(_NORMAL_ALIASES)\n    if normal_dev:\n        all_aliases_maps.append(_NORMAL_DEV_ALIASES)\n    if proc_macro:\n        all_aliases_maps.append(_PROC_MACRO_ALIASES)\n    if proc_macro_dev:\n        all_aliases_maps.append(_PROC_MACRO_DEV_ALIASES)\n    if build:\n        all_aliases_maps.append(_BUILD_ALIASES)\n    if build_proc_macro:\n        all_aliases_maps.append(_BUILD_PROC_MACRO_ALIASES)\n\n    # Default to always using normal aliases\n    if not all_aliases_maps:\n        all_aliases_maps.append(_NORMAL_ALIASES)\n        all_aliases_maps.append(_PROC_MACRO_ALIASES)\n\n    aliases = _flatten_dependency_maps(all_aliases_maps).pop(package_name, None)\n\n    if not aliases:\n        return dict()\n\n    common_items = aliases.pop(_COMMON_CONDITION, {}).items()\n\n    # If there are only common items in the dictionary, immediately return them\n    if not len(aliases.keys()) == 1:\n        return dict(common_items)\n\n    # Build a single select statement where each conditional has accounted for the\n    # common set of aliases.\n    crate_aliases = {\"//conditions:default\": dict(common_items)}\n    for condition, deps in aliases.items():\n        condition_triples = _CONDITIONS[condition]\n        for triple in condition_triples:\n            if triple in crate_aliases:\n                crate_aliases[triple].update(deps)\n            else:\n                crate_aliases.update({triple: dict(deps.items() + common_items)})\n\n    return select(crate_aliases)\n\n###############################################################################\n# WORKSPACE MEMBER DEPS AND ALIASES\n###############################################################################\n\n_NORMAL_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            \"aes\": Label(\"@rust_crates//:aes-0.8.4\"),\n            \"aes-gcm\": Label(\"@rust_crates//:aes-gcm-0.10.3\"),\n            \"aligned\": Label(\"@rust_crates//:aligned-0.4.3\"),\n            \"anyhow\": Label(\"@rust_crates//:anyhow-1.0.102\"),\n            \"bitfield\": Label(\"@rust_crates//:bitfield-0.14.0\"),\n            \"bitflags\": Label(\"@rust_crates//:bitflags-2.12.1\"),\n            \"byteorder\": Label(\"@rust_crates//:byteorder-1.5.0\"),\n            \"cfg-if\": Label(\"@rust_crates//:cfg-if-1.0.4\"),\n            \"cipher\": Label(\"@rust_crates//:cipher-0.4.4\"),\n            \"clap\": Label(\"@rust_crates//:clap-4.6.1\"),\n            \"compiler_builtins\": Label(\"@rust_crates//:compiler_builtins-0.1.160\"),\n            \"cortex-m\": Label(\"@rust_crates//:cortex-m-0.7.7\"),\n            \"cortex-m-rt\": Label(\"@rust_crates//:cortex-m-rt-0.7.5\"),\n            \"cortex-m-semihosting\": Label(\"@rust_crates//:cortex-m-semihosting-0.5.0\"),\n            \"critical-section\": Label(\"@rust_crates//:critical-section-1.2.0\"),\n            \"ctr\": Label(\"@rust_crates//:ctr-0.9.2\"),\n            \"ecdsa\": Label(\"@rust_crates//:ecdsa-0.16.9\"),\n            \"embedded-hal\": Label(\"@rust_crates//:embedded-hal-1.0.0\"),\n            \"embedded-hal-async\": Label(\"@rust_crates//:embedded-hal-async-1.0.0\"),\n            \"embedded-hal-nb\": Label(\"@rust_crates//:embedded-hal-nb-1.0.0\"),\n            \"embedded-io\": Label(\"@rust_crates//:embedded-io-0.6.1\"),\n            \"embedded-storage\": Label(\"@rust_crates//:embedded-storage-0.3.1\"),\n            \"fugit\": Label(\"@rust_crates//:fugit-0.3.9\"),\n            \"futures\": Label(\"@rust_crates//:futures-0.3.32\"),\n            \"heapless\": Label(\"@rust_crates//:heapless-0.9.3\"),\n            \"hex\": Label(\"@rust_crates//:hex-0.4.3\"),\n            \"hex-literal\": Label(\"@rust_crates//:hex-literal-0.4.1\"),\n            \"hmac\": Label(\"@rust_crates//:hmac-0.12.1\"),\n            \"k256\": Label(\"@rust_crates//:k256-0.13.4\"),\n            \"log\": Label(\"@rust_crates//:log-0.4.31\"),\n            \"mctp\": Label(\"@rust_crates//:mctp-0.2.0\"),\n            \"mctp-lib\": Label(\"@rust_crates//:mctp-lib-0.1.0\"),\n            \"memoffset\": Label(\"@rust_crates//:memoffset-0.9.1\"),\n            \"minijinja\": Label(\"@rust_crates//:minijinja-2.20.0\"),\n            \"nb\": Label(\"@rust_crates//:nb-1.1.0\"),\n            \"nom\": Label(\"@rust_crates//:nom-7.1.3\"),\n            \"object\": Label(\"@rust_crates//:object-0.37.3\"),\n            \"openprot-hal-blocking\": Label(\"@rust_crates//:openprot-hal-blocking-0.1.0\"),\n            \"p256\": Label(\"@rust_crates//:p256-0.13.2\"),\n            \"p384\": Label(\"@rust_crates//:p384-0.13.1\"),\n            \"panic-halt\": Label(\"@rust_crates//:panic-halt-1.0.0\"),\n            \"proc-macro2\": Label(\"@rust_crates//:proc-macro2-1.0.106\"),\n            \"prost\": Label(\"@rust_crates//:prost-0.13.5\"),\n            \"quote\": Label(\"@rust_crates//:quote-1.0.45\"),\n            \"rand_core\": Label(\"@rust_crates//:rand_core-0.9.5\"),\n            \"riscv\": Label(\"@rust_crates//:riscv-0.12.1\"),\n            \"riscv-rt\": Label(\"@rust_crates//:riscv-rt-0.12.2\"),\n            \"riscv-semihosting\": Label(\"@rust_crates//:riscv-semihosting-0.1.3\"),\n            \"rustc-demangle\": Label(\"@rust_crates//:rustc-demangle-0.1.27\"),\n            \"sec1\": Label(\"@rust_crates//:sec1-0.7.3\"),\n            \"serde\": Label(\"@rust_crates//:serde-1.0.228\"),\n            \"serde_json5\": Label(\"@rust_crates//:serde_json5-0.2.1\"),\n            \"sha2\": Label(\"@rust_crates//:sha2-0.10.9\"),\n            \"sha3\": Label(\"@rust_crates//:sha3-0.10.9\"),\n            \"smlang\": Label(\"@rust_crates//:smlang-0.8.0\"),\n            \"spdm-lib\": Label(\"@rust_crates//:spdm-lib-0.1.0\"),\n            \"subtle\": Label(\"@rust_crates//:subtle-2.6.1\"),\n            \"syn1\": Label(\"@rust_crates//:syn-1.0.109\"),\n            \"syn\": Label(\"@rust_crates//:syn-2.0.117\"),\n            \"thiserror\": Label(\"@rust_crates//:thiserror-2.0.18\"),\n            \"tock-registers\": Label(\"@rust_crates//:tock-registers-0.9.0\"),\n            \"tokio\": Label(\"@rust_crates//:tokio-1.52.3\"),\n            \"tokio-util\": Label(\"@rust_crates//:tokio-util-0.7.18\"),\n            \"vcell\": Label(\"@rust_crates//:vcell-0.1.3\"),\n            \"zerocopy\": Label(\"@rust_crates//:zerocopy-0.8.50\"),\n            \"zeroize\": Label(\"@rust_crates//:zeroize-1.8.2\"),\n        },\n    },\n}\n\n\n_NORMAL_ALIASES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            Label(\"@rust_crates//:syn-1.0.109\"): \"syn1\",\n        },\n    },\n}\n\n\n_NORMAL_DEV_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_NORMAL_DEV_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n        _COMMON_CONDITION: {\n            \"bitfield-struct\": Label(\"@rust_crates//:bitfield-struct-0.11.0\"),\n            \"paste\": Label(\"@rust_crates//:paste-1.0.15\"),\n            \"serde_derive\": Label(\"@rust_crates//:serde_derive-1.0.228\"),\n        },\n    },\n}\n\n\n_PROC_MACRO_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEV_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_PROC_MACRO_DEV_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_PROC_MACRO_DEPENDENCIES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_BUILD_PROC_MACRO_ALIASES = {\n    \"third_party/crates_io\": {\n    },\n}\n\n\n_CONDITIONS = {\n    \"aarch64-apple-darwin\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\"],\n    \"aarch64-linux-android\": [],\n    \"aarch64-unknown-linux-gnu\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(all(any(target_os = \\\"linux\\\", target_os = \\\"android\\\"), any(rustix_use_libc, miri, not(all(target_os = \\\"linux\\\", any(target_endian = \\\"little\\\", any(target_arch = \\\"s390x\\\", target_arch = \\\"powerpc\\\")), any(target_arch = \\\"arm\\\", all(target_arch = \\\"aarch64\\\", target_pointer_width = \\\"64\\\"), target_arch = \\\"riscv64\\\", all(rustix_use_experimental_asm, target_arch = \\\"powerpc\\\"), all(rustix_use_experimental_asm, target_arch = \\\"powerpc64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"s390x\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips32r6\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64r6\\\"), target_arch = \\\"x86\\\", all(target_arch = \\\"x86_64\\\", target_pointer_width = \\\"64\\\")))))))\": [],\n    \"cfg(all(not(rustix_use_libc), not(miri), target_os = \\\"linux\\\", any(target_endian = \\\"little\\\", any(target_arch = \\\"s390x\\\", target_arch = \\\"powerpc\\\")), any(target_arch = \\\"arm\\\", all(target_arch = \\\"aarch64\\\", target_pointer_width = \\\"64\\\"), target_arch = \\\"riscv64\\\", all(rustix_use_experimental_asm, target_arch = \\\"powerpc\\\"), all(rustix_use_experimental_asm, target_arch = \\\"powerpc64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"s390x\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips32r6\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64r6\\\"), target_arch = \\\"x86\\\", all(target_arch = \\\"x86_64\\\", target_pointer_width = \\\"64\\\"))))\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(all(not(windows), any(rustix_use_libc, miri, not(all(target_os = \\\"linux\\\", any(target_endian = \\\"little\\\", any(target_arch = \\\"s390x\\\", target_arch = \\\"powerpc\\\")), any(target_arch = \\\"arm\\\", all(target_arch = \\\"aarch64\\\", target_pointer_width = \\\"64\\\"), target_arch = \\\"riscv64\\\", all(rustix_use_experimental_asm, target_arch = \\\"powerpc\\\"), all(rustix_use_experimental_asm, target_arch = \\\"powerpc64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"s390x\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips32r6\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64\\\"), all(rustix_use_experimental_asm, target_arch = \\\"mips64r6\\\"), target_arch = \\\"x86\\\", all(target_arch = \\\"x86_64\\\", target_pointer_width = \\\"64\\\")))))))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\",\"@rules_rust//rust/platform:thumbv7em-none-eabi\",\"@rules_rust//rust/platform:x86_64-apple-darwin\"],\n    \"cfg(all(target_arch = \\\"aarch64\\\", target_os = \\\"linux\\\"))\": [\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(all(target_arch = \\\"aarch64\\\", target_vendor = \\\"apple\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\"],\n    \"cfg(all(target_arch = \\\"loongarch64\\\", target_os = \\\"linux\\\"))\": [],\n    \"cfg(any())\": [],\n    \"cfg(any(target_arch = \\\"aarch64\\\", target_arch = \\\"x86_64\\\", target_arch = \\\"x86\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(any(target_arch = \\\"arm\\\", target_pointer_width = \\\"32\\\", target_pointer_width = \\\"64\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\",\"@rules_rust//rust/platform:thumbv7em-none-eabi\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(any(unix, target_os = \\\"hermit\\\", target_os = \\\"wasi\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(any(unix, target_os = \\\"wasi\\\"))\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(target_arch = \\\"aarch64\\\")\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\"],\n    \"cfg(target_os = \\\"hermit\\\")\": [],\n    \"cfg(target_os = \\\"redox\\\")\": [],\n    \"cfg(target_os = \\\"wasi\\\")\": [],\n    \"cfg(unix)\": [\"@rules_rust//rust/platform:aarch64-apple-darwin\",\"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\",\"@rules_rust//rust/platform:x86_64-apple-darwin\",\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n    \"cfg(windows)\": [],\n    \"riscv32imc-unknown-none-elf\": [\"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\"],\n    \"thumbv7em-none-eabi\": [\"@rules_rust//rust/platform:thumbv7em-none-eabi\"],\n    \"x86_64-apple-darwin\": [\"@rules_rust//rust/platform:x86_64-apple-darwin\"],\n    \"x86_64-unknown-linux-gnu\": [\"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\"],\n}\n\n###############################################################################\n\ndef crate_repositories():\n    \"\"\"A macro for defining repositories for all generated crates.\n\n    Returns:\n      A list of repos visible to the module through the module extension.\n    \"\"\"\n    maybe(\n        http_archive,\n        name = \"rust_crates__adler2-2.0.1\",\n        sha256 = \"320119579fcad9c21884f5c4861d16174d0e06250625266f50fe6898340abefa\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/adler2/2.0.1/download\"],\n        strip_prefix = \"adler2-2.0.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.adler2-2.0.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aead-0.5.2\",\n        sha256 = \"d122413f284cf2d62fb1b7db97e02edb8cda96d769b16e443a4f6195e35662b0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aead/0.5.2/download\"],\n        strip_prefix = \"aead-0.5.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aead-0.5.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aes-0.8.4\",\n        sha256 = \"b169f7a6d4742236a0a00c541b845991d0ac43e546831af1249753ab4c3aa3a0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aes/0.8.4/download\"],\n        strip_prefix = \"aes-0.8.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aes-0.8.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aes-gcm-0.10.3\",\n        sha256 = \"831010a0f742e1209b3bcea8fab6a8e149051ba6099432c8cb2cc117dec3ead1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aes-gcm/0.10.3/download\"],\n        strip_prefix = \"aes-gcm-0.10.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aes-gcm-0.10.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__aligned-0.4.3\",\n        sha256 = \"ee4508988c62edf04abd8d92897fca0c2995d907ce1dfeaf369dac3716a40685\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/aligned/0.4.3/download\"],\n        strip_prefix = \"aligned-0.4.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.aligned-0.4.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstream-1.0.0\",\n        sha256 = \"824a212faf96e9acacdbd09febd34438f8f711fb84e09a8916013cd7815ca28d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstream/1.0.0/download\"],\n        strip_prefix = \"anstream-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstream-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-1.0.14\",\n        sha256 = \"940b3a0ca603d1eade50a4846a2afffd5ef57a9feac2c0e2ec2e14f9ead76000\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle/1.0.14/download\"],\n        strip_prefix = \"anstyle-1.0.14\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-1.0.14.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-parse-1.0.0\",\n        sha256 = \"52ce7f38b242319f7cabaa6813055467063ecdc9d355bbb4ce0c68908cd8130e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-parse/1.0.0/download\"],\n        strip_prefix = \"anstyle-parse-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-parse-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-query-1.1.5\",\n        sha256 = \"40c48f72fd53cd289104fc64099abca73db4166ad86ea0b4341abe65af83dadc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-query/1.1.5/download\"],\n        strip_prefix = \"anstyle-query-1.1.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-query-1.1.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anstyle-wincon-3.0.11\",\n        sha256 = \"291e6a250ff86cd4a820112fb8898808a366d8f9f58ce16d1f538353ad55747d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anstyle-wincon/3.0.11/download\"],\n        strip_prefix = \"anstyle-wincon-3.0.11\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anstyle-wincon-3.0.11.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__anyhow-1.0.102\",\n        sha256 = \"7f202df86484c868dbad7eaa557ef785d5c66295e41b460ef922eca0723b842c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/anyhow/1.0.102/download\"],\n        strip_prefix = \"anyhow-1.0.102\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.anyhow-1.0.102.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__as-slice-0.2.1\",\n        sha256 = \"516b6b4f0e40d50dcda9365d53964ec74560ad4284da2e7fc97122cd83174516\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/as-slice/0.2.1/download\"],\n        strip_prefix = \"as-slice-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.as-slice-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__autocfg-1.5.1\",\n        sha256 = \"f2032f911046de80f0a198e0901378627c33f59ea0ac00e363d481118bd70a53\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/autocfg/1.5.1/download\"],\n        strip_prefix = \"autocfg-1.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.autocfg-1.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bare-metal-0.2.5\",\n        sha256 = \"5deb64efa5bd81e31fcd1938615a6d98c82eafcbcd787162b6f63b91d6bac5b3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bare-metal/0.2.5/download\"],\n        strip_prefix = \"bare-metal-0.2.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bare-metal-0.2.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__base16ct-0.2.0\",\n        sha256 = \"4c7f02d4ea65f2c1853089ffd8d2787bdbc63de2f0d29dedbcf8ccdfa0ccd4cf\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/base16ct/0.2.0/download\"],\n        strip_prefix = \"base16ct-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.base16ct-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-0.13.2\",\n        sha256 = \"46afbd2983a5d5a7bd740ccb198caf5b82f45c40c09c0eed36052d91cb92e719\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield/0.13.2/download\"],\n        strip_prefix = \"bitfield-0.13.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-0.13.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-0.14.0\",\n        sha256 = \"2d7e60934ceec538daadb9d8432424ed043a904d8e0243f3c6446bce549a46ac\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield/0.14.0/download\"],\n        strip_prefix = \"bitfield-0.14.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-0.14.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitfield-struct-0.11.0\",\n        sha256 = \"d3ca019570363e800b05ad4fd890734f28ac7b72f563ad8a35079efb793616f8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitfield-struct/0.11.0/download\"],\n        strip_prefix = \"bitfield-struct-0.11.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitfield-struct-0.11.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bitflags-2.12.1\",\n        sha256 = \"84d7ced0ae9557296835c32bf1b1e02b44c746701f898460fb000d7eaa84f00a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bitflags/2.12.1/download\"],\n        strip_prefix = \"bitflags-2.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bitflags-2.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__block-buffer-0.10.4\",\n        sha256 = \"3078c7629b62d3f0439517fa394996acacc5cbc91c5a20d8c658e77abd503a71\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/block-buffer/0.10.4/download\"],\n        strip_prefix = \"block-buffer-0.10.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.block-buffer-0.10.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__byteorder-1.5.0\",\n        sha256 = \"1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/byteorder/1.5.0/download\"],\n        strip_prefix = \"byteorder-1.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.byteorder-1.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__bytes-1.11.1\",\n        sha256 = \"1e748733b7cbc798e1434b6ac524f0c1ff2ab456fe201501e6497c8417a4fc33\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/bytes/1.11.1/download\"],\n        strip_prefix = \"bytes-1.11.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.bytes-1.11.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cfg-if-1.0.4\",\n        sha256 = \"9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cfg-if/1.0.4/download\"],\n        strip_prefix = \"cfg-if-1.0.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cfg-if-1.0.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cipher-0.4.4\",\n        sha256 = \"773f3b9af64447d2ce9850330c473515014aa235e6a783b02db81ff39e4a3dad\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cipher/0.4.4/download\"],\n        strip_prefix = \"cipher-0.4.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cipher-0.4.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap-4.6.1\",\n        sha256 = \"1ddb117e43bbf7dacf0a4190fef4d345b9bad68dfc649cb349e7d17d28428e51\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap/4.6.1/download\"],\n        strip_prefix = \"clap-4.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap-4.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_builder-4.6.0\",\n        sha256 = \"714a53001bf66416adb0e2ef5ac857140e7dc3a0c48fb28b2f10762fc4b5069f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_builder/4.6.0/download\"],\n        strip_prefix = \"clap_builder-4.6.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_builder-4.6.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_derive-4.6.1\",\n        sha256 = \"f2ce8604710f6733aa641a2b3731eaa1e8b3d9973d5e3565da11800813f997a9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_derive/4.6.1/download\"],\n        strip_prefix = \"clap_derive-4.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_derive-4.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__clap_lex-1.1.0\",\n        sha256 = \"c8d4a3bb8b1e0c1050499d1815f5ab16d04f0959b233085fb31653fbfc9d98f9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/clap_lex/1.1.0/download\"],\n        strip_prefix = \"clap_lex-1.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.clap_lex-1.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__colorchoice-1.0.5\",\n        sha256 = \"1d07550c9036bf2ae0c684c4297d503f838287c83c53686d05370d0e139ae570\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/colorchoice/1.0.5/download\"],\n        strip_prefix = \"colorchoice-1.0.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.colorchoice-1.0.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__compiler_builtins-0.1.160\",\n        sha256 = \"6376049cfa92c0aa8b9ac95fae22184b981c658208d4ed8a1dc553cd83612895\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/compiler_builtins/0.1.160/download\"],\n        strip_prefix = \"compiler_builtins-0.1.160\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.compiler_builtins-0.1.160.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__const-oid-0.9.6\",\n        sha256 = \"c2459377285ad874054d797f3ccebf984978aa39129f6eafde5cdc8315b612f8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/const-oid/0.9.6/download\"],\n        strip_prefix = \"const-oid-0.9.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.const-oid-0.9.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-0.7.7\",\n        sha256 = \"8ec610d8f49840a5b376c69663b6369e71f4b34484b9b2eb29fb918d92516cb9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m/0.7.7/download\"],\n        strip_prefix = \"cortex-m-0.7.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-0.7.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-rt-0.7.5\",\n        sha256 = \"801d4dec46b34c299ccf6b036717ae0fce602faa4f4fe816d9013b9a7c9f5ba6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m-rt/0.7.5/download\"],\n        strip_prefix = \"cortex-m-rt-0.7.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-rt-0.7.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-rt-macros-0.7.5\",\n        sha256 = \"e37549a379a9e0e6e576fd208ee60394ccb8be963889eebba3ffe0980364f472\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m-rt-macros/0.7.5/download\"],\n        strip_prefix = \"cortex-m-rt-macros-0.7.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-rt-macros-0.7.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cortex-m-semihosting-0.5.0\",\n        sha256 = \"c23234600452033cc77e4b761e740e02d2c4168e11dbf36ab14a0f58973592b0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cortex-m-semihosting/0.5.0/download\"],\n        strip_prefix = \"cortex-m-semihosting-0.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cortex-m-semihosting-0.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__cpufeatures-0.2.17\",\n        sha256 = \"59ed5838eebb26a2bb2e58f6d5b5316989ae9d08bab10e0e6d103e656d1b0280\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/cpufeatures/0.2.17/download\"],\n        strip_prefix = \"cpufeatures-0.2.17\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.cpufeatures-0.2.17.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crc-3.4.0\",\n        sha256 = \"5eb8a2a1cd12ab0d987a5d5e825195d372001a4094a0376319d5a0ad71c1ba0d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crc/3.4.0/download\"],\n        strip_prefix = \"crc-3.4.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crc-3.4.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crc-catalog-2.5.0\",\n        sha256 = \"217698eaf96b4a3f0bc4f3662aaa55bdf913cd54d7204591faa790070c6d0853\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crc-catalog/2.5.0/download\"],\n        strip_prefix = \"crc-catalog-2.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crc-catalog-2.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crc32fast-1.5.0\",\n        sha256 = \"9481c1c90cbf2ac953f07c8d4a58aa3945c425b7185c9154d67a65e4230da511\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crc32fast/1.5.0/download\"],\n        strip_prefix = \"crc32fast-1.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crc32fast-1.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__critical-section-1.2.0\",\n        sha256 = \"790eea4361631c5e7d22598ecd5723ff611904e3344ce8720784c93e3d83d40b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/critical-section/1.2.0/download\"],\n        strip_prefix = \"critical-section-1.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.critical-section-1.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crypto-bigint-0.5.5\",\n        sha256 = \"0dc92fb57ca44df6db8059111ab3af99a63d5d0f8375d9972e319a379c6bab76\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crypto-bigint/0.5.5/download\"],\n        strip_prefix = \"crypto-bigint-0.5.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crypto-bigint-0.5.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__crypto-common-0.1.7\",\n        sha256 = \"78c8292055d1c1df0cce5d180393dc8cce0abec0a7102adb6c7b1eef6016d60a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/crypto-common/0.1.7/download\"],\n        strip_prefix = \"crypto-common-0.1.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.crypto-common-0.1.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ctr-0.9.2\",\n        sha256 = \"0369ee1ad671834580515889b80f2ea915f23b8be8d0daa4bbaf2ac5c7590835\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ctr/0.9.2/download\"],\n        strip_prefix = \"ctr-0.9.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ctr-0.9.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__der-0.7.10\",\n        sha256 = \"e7c1832837b905bbfb5101e07cc24c8deddf52f93225eee6ead5f4d63d53ddcb\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/der/0.7.10/download\"],\n        strip_prefix = \"der-0.7.10\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.der-0.7.10.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__digest-0.10.7\",\n        sha256 = \"9ed9a281f7bc9b7576e61468ba615a66a5c8cfdff42420a70aa82701a3b1e292\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/digest/0.10.7/download\"],\n        strip_prefix = \"digest-0.10.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.digest-0.10.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ecdsa-0.16.9\",\n        sha256 = \"ee27f32b5c5292967d2d4a9d7f1e0b0aed2c15daded5a60300e4abb9d8020bca\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ecdsa/0.16.9/download\"],\n        strip_prefix = \"ecdsa-0.16.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ecdsa-0.16.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__either-1.16.0\",\n        sha256 = \"91622ff5e7162018101f2fea40d6ebf4a78bbe5a49736a2020649edf9693679e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/either/1.16.0/download\"],\n        strip_prefix = \"either-1.16.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.either-1.16.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__elliptic-curve-0.13.8\",\n        sha256 = \"b5e6043086bf7973472e0c7dff2142ea0b680d30e18d9cc40f267efbf222bd47\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/elliptic-curve/0.13.8/download\"],\n        strip_prefix = \"elliptic-curve-0.13.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.elliptic-curve-0.13.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-crc-macros-1.0.0\",\n        sha256 = \"4f1c75747a43b086df1a87fb2a889590bc0725e0abf54bba6d0c4bf7bd9e762c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-crc-macros/1.0.0/download\"],\n        strip_prefix = \"embedded-crc-macros-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-crc-macros-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-0.2.7\",\n        sha256 = \"35949884794ad573cf46071e41c9b60efb0cb311e3ca01f7af807af1debc66ff\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal/0.2.7/download\"],\n        strip_prefix = \"embedded-hal-0.2.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-0.2.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-1.0.0\",\n        sha256 = \"361a90feb7004eca4019fb28352a9465666b24f840f5c3cddf0ff13920590b89\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-async-1.0.0\",\n        sha256 = \"0c4c685bbef7fe13c3c6dd4da26841ed3980ef33e841cddfa15ce8a8fb3f1884\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal-async/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-async-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-async-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-hal-nb-1.0.0\",\n        sha256 = \"fba4268c14288c828995299e59b12babdbe170f6c6d73731af1b4648142e8605\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-hal-nb/1.0.0/download\"],\n        strip_prefix = \"embedded-hal-nb-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-hal-nb-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-io-0.6.1\",\n        sha256 = \"edd0f118536f44f5ccd48bcb8b111bdc3de888b58c74639dfb034a357d0f206d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-io/0.6.1/download\"],\n        strip_prefix = \"embedded-io-0.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-io-0.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-io-async-0.6.1\",\n        sha256 = \"3ff09972d4073aa8c299395be75161d582e7629cd663171d62af73c8d50dba3f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-io-async/0.6.1/download\"],\n        strip_prefix = \"embedded-io-async-0.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-io-async-0.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__embedded-storage-0.3.1\",\n        sha256 = \"a21dea9854beb860f3062d10228ce9b976da520a73474aed3171ec276bc0c032\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/embedded-storage/0.3.1/download\"],\n        strip_prefix = \"embedded-storage-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.embedded-storage-0.3.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__equivalent-1.0.2\",\n        sha256 = \"877a4ace8713b0bcf2a4e7eec82529c029f1d0619886d18145fea96c3ffe5c0f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/equivalent/1.0.2/download\"],\n        strip_prefix = \"equivalent-1.0.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.equivalent-1.0.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__errno-0.3.14\",\n        sha256 = \"39cab71617ae0d63f51a36d69f866391735b51691dbda63cf6f96d042b63efeb\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/errno/0.3.14/download\"],\n        strip_prefix = \"errno-0.3.14\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.errno-0.3.14.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ff-0.13.1\",\n        sha256 = \"c0b50bfb653653f9ca9095b427bed08ab8d75a137839d9ad64eb11810d5b6393\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ff/0.13.1/download\"],\n        strip_prefix = \"ff-0.13.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ff-0.13.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__flate2-1.1.9\",\n        sha256 = \"843fba2746e448b37e26a819579957415c8cef339bf08564fe8b7ddbd959573c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/flate2/1.1.9/download\"],\n        strip_prefix = \"flate2-1.1.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.flate2-1.1.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__foldhash-0.1.5\",\n        sha256 = \"d9c4f5dac5e15c24eb999c26181a6ca40b39fe946cbe4c263c7209467bc83af2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/foldhash/0.1.5/download\"],\n        strip_prefix = \"foldhash-0.1.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.foldhash-0.1.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__fugit-0.3.9\",\n        sha256 = \"4e639847d312d9a82d2e75b0edcc1e934efcc64e6cb7aa94f0b1fbec0bc231d6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/fugit/0.3.9/download\"],\n        strip_prefix = \"fugit-0.3.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.fugit-0.3.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-0.3.32\",\n        sha256 = \"8b147ee9d1f6d097cef9ce628cd2ee62288d963e16fb287bd9286455b241382d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures/0.3.32/download\"],\n        strip_prefix = \"futures-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-channel-0.3.32\",\n        sha256 = \"07bbe89c50d7a535e539b8c17bc0b49bdb77747034daa8087407d655f3f7cc1d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-channel/0.3.32/download\"],\n        strip_prefix = \"futures-channel-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-channel-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-core-0.3.32\",\n        sha256 = \"7e3450815272ef58cec6d564423f6e755e25379b217b0bc688e295ba24df6b1d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-core/0.3.32/download\"],\n        strip_prefix = \"futures-core-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-core-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-executor-0.3.32\",\n        sha256 = \"baf29c38818342a3b26b5b923639e7b1f4a61fc5e76102d4b1981c6dc7a7579d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-executor/0.3.32/download\"],\n        strip_prefix = \"futures-executor-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-executor-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-io-0.3.32\",\n        sha256 = \"cecba35d7ad927e23624b22ad55235f2239cfa44fd10428eecbeba6d6a717718\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-io/0.3.32/download\"],\n        strip_prefix = \"futures-io-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-io-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-macro-0.3.32\",\n        sha256 = \"e835b70203e41293343137df5c0664546da5745f82ec9b84d40be8336958447b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-macro/0.3.32/download\"],\n        strip_prefix = \"futures-macro-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-macro-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-sink-0.3.32\",\n        sha256 = \"c39754e157331b013978ec91992bde1ac089843443c49cbc7f46150b0fad0893\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-sink/0.3.32/download\"],\n        strip_prefix = \"futures-sink-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-sink-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-task-0.3.32\",\n        sha256 = \"037711b3d59c33004d3856fbdc83b99d4ff37a24768fa1be9ce3538a1cde4393\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-task/0.3.32/download\"],\n        strip_prefix = \"futures-task-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-task-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__futures-util-0.3.32\",\n        sha256 = \"389ca41296e6190b48053de0321d02a77f32f8a5d2461dd38762c0593805c6d6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/futures-util/0.3.32/download\"],\n        strip_prefix = \"futures-util-0.3.32\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.futures-util-0.3.32.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__gcd-2.3.0\",\n        sha256 = \"1d758ba1b47b00caf47f24925c0074ecb20d6dfcffe7f6d53395c0465674841a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/gcd/2.3.0/download\"],\n        strip_prefix = \"gcd-2.3.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.gcd-2.3.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__generic-array-0.14.7\",\n        sha256 = \"85649ca51fd72272d7821adaf274ad91c288277713d9c18820d8499a7ff69e9a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/generic-array/0.14.7/download\"],\n        strip_prefix = \"generic-array-0.14.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.generic-array-0.14.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ghash-0.5.1\",\n        sha256 = \"f0d8a4362ccb29cb0b265253fb0a2728f592895ee6854fd9bc13f2ffda266ff1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ghash/0.5.1/download\"],\n        strip_prefix = \"ghash-0.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ghash-0.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__group-0.13.0\",\n        sha256 = \"f0f9ef7462f7c099f518d754361858f86d8a07af53ba9af0fe635bbccb151a63\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/group/0.13.0/download\"],\n        strip_prefix = \"group-0.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.group-0.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hash32-0.3.1\",\n        sha256 = \"47d60b12902ba28e2730cd37e95b8c9223af2808df9e902d4df49588d1470606\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hash32/0.3.1/download\"],\n        strip_prefix = \"hash32-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hash32-0.3.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashbrown-0.15.5\",\n        sha256 = \"9229cfe53dfd69f0609a49f65461bd93001ea1ef889cd5529dd176593f5338a1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashbrown/0.15.5/download\"],\n        strip_prefix = \"hashbrown-0.15.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashbrown-0.15.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hashbrown-0.17.1\",\n        sha256 = \"ed5909b6e89a2db4456e54cd5f673791d7eca6732202bbf2a9cc504fe2f9b84a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hashbrown/0.17.1/download\"],\n        strip_prefix = \"hashbrown-0.17.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hashbrown-0.17.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heapless-0.8.0\",\n        sha256 = \"0bfb9eb618601c89945a70e254898da93b13be0388091d42117462b265bb3fad\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heapless/0.8.0/download\"],\n        strip_prefix = \"heapless-0.8.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heapless-0.8.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heapless-0.9.3\",\n        sha256 = \"25ba4bd83f9415b58b4ed8dc5714c76e626a105be4646c02630ad730ad3b5aa4\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heapless/0.9.3/download\"],\n        strip_prefix = \"heapless-0.9.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heapless-0.9.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__heck-0.5.0\",\n        sha256 = \"2304e00983f87ffb38b55b444b5e3b60a884b5d30c0fca7d82fe33449bbe55ea\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/heck/0.5.0/download\"],\n        strip_prefix = \"heck-0.5.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.heck-0.5.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hex-0.4.3\",\n        sha256 = \"7f24254aa9a54b5c858eaee2f5bccdb46aaf0e486a595ed5fd8f86ba55232a70\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/hex/0.4.3/download\"],\n        strip_prefix = \"hex-0.4.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.hex-0.4.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__hex-literal-0.4.1\",\n        sha256 = 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[\"https://static.crates.io/crates/indexmap/2.14.0/download\"],\n        strip_prefix = \"indexmap-2.14.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.indexmap-2.14.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__inout-0.1.4\",\n        sha256 = \"879f10e63c20629ecabbb64a8010319738c66a5cd0c29b02d63d272b03751d01\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/inout/0.1.4/download\"],\n        strip_prefix = \"inout-0.1.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.inout-0.1.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__is_terminal_polyfill-1.70.2\",\n        sha256 = \"a6cb138bb79a146c1bd460005623e142ef0181e3d0219cb493e02f7d08a35695\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/is_terminal_polyfill/1.70.2/download\"],\n        strip_prefix = \"is_terminal_polyfill-1.70.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.is_terminal_polyfill-1.70.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__itertools-0.14.0\",\n        sha256 = \"2b192c782037fadd9cfa75548310488aabdbf3d2da73885b31bd0abd03351285\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/itertools/0.14.0/download\"],\n        strip_prefix = \"itertools-0.14.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.itertools-0.14.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__k256-0.13.4\",\n        sha256 = \"f6e3919bbaa2945715f0bb6d3934a173d1e9a59ac23767fbaaef277265a7411b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/k256/0.13.4/download\"],\n        strip_prefix = \"k256-0.13.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.k256-0.13.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__keccak-0.1.6\",\n        sha256 = \"cb26cec98cce3a3d96cbb7bced3c4b16e3d13f27ec56dbd62cbc8f39cfb9d653\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/keccak/0.1.6/download\"],\n        strip_prefix = \"keccak-0.1.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.keccak-0.1.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__libc-0.2.186\",\n        sha256 = \"68ab91017fe16c622486840e4c83c9a37afeff978bd239b5293d61ece587de66\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/libc/0.2.186/download\"],\n        strip_prefix = \"libc-0.2.186\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.libc-0.2.186.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__linux-raw-sys-0.12.1\",\n        sha256 = \"32a66949e030da00e8c7d4434b251670a91556f4144941d37452769c25d58a53\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/linux-raw-sys/0.12.1/download\"],\n        strip_prefix = \"linux-raw-sys-0.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.linux-raw-sys-0.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__lock_api-0.4.14\",\n        sha256 = \"224399e74b87b5f3557511d98dff8b14089b3dadafcab6bb93eab67d3aace965\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/lock_api/0.4.14/download\"],\n        strip_prefix = \"lock_api-0.4.14\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.lock_api-0.4.14.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__log-0.4.31\",\n        sha256 = \"113b30b4cd05f7c06868fdb2854f66a7b9fece9a48425351cd532e810d74024f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/log/0.4.31/download\"],\n        strip_prefix = \"log-0.4.31\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.log-0.4.31.bazel\"),\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__mctp-0.2.0\",\n        commit = \"b134e145f93d634dff7eb9f2a01559273c687365\",\n        init_submodules = True,\n        remote = \"https://github.com/CodeConstruct/mctp-rs.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.mctp-0.2.0.bazel\"),\n        strip_prefix = \"mctp\",\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__mctp-estack-0.1.0\",\n        commit = \"b134e145f93d634dff7eb9f2a01559273c687365\",\n        init_submodules = True,\n        remote = \"https://github.com/CodeConstruct/mctp-rs.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.mctp-estack-0.1.0.bazel\"),\n        strip_prefix = \"mctp-estack\",\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__mctp-lib-0.1.0\",\n        commit = \"742fa0e991aa2b87509ff12739e011a674643d91\",\n        init_submodules = True,\n        remote = \"https://github.com/OpenPRoT/mctp-lib.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.mctp-lib-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memchr-2.8.1\",\n        sha256 = \"6b947ae49db0d222b1dbc6b113ce7248a3fc3a6ca21b696717bfc000ba4484d8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memchr/2.8.1/download\"],\n        strip_prefix = \"memchr-2.8.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memchr-2.8.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memo-map-0.3.3\",\n        sha256 = \"38d1115007560874e373613744c6fba374c17688327a71c1476d1a5954cc857b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memo-map/0.3.3/download\"],\n        strip_prefix = \"memo-map-0.3.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memo-map-0.3.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__memoffset-0.9.1\",\n        sha256 = \"488016bfae457b036d996092f6cb448677611ce4449e970ceaf42695203f218a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/memoffset/0.9.1/download\"],\n        strip_prefix = \"memoffset-0.9.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.memoffset-0.9.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__minijinja-2.20.0\",\n        sha256 = \"2929e494b2280e1e18959bb2e121da03347ae896896fdfaceaab43c88a02803f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/minijinja/2.20.0/download\"],\n        strip_prefix = \"minijinja-2.20.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.minijinja-2.20.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__minimal-lexical-0.2.1\",\n        sha256 = \"68354c5c6bd36d73ff3feceb05efa59b6acb7626617f4962be322a825e61f79a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/minimal-lexical/0.2.1/download\"],\n        strip_prefix = \"minimal-lexical-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.minimal-lexical-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__miniz_oxide-0.8.9\",\n        sha256 = \"1fa76a2c86f704bdb222d66965fb3d63269ce38518b83cb0575fca855ebb6316\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/miniz_oxide/0.8.9/download\"],\n        strip_prefix = \"miniz_oxide-0.8.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.miniz_oxide-0.8.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__mio-1.2.1\",\n        sha256 = \"02bd0af71c67b473010cbbc60715ee815645a4dc942899111f494b4b737d6fda\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/mio/1.2.1/download\"],\n        strip_prefix = \"mio-1.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.mio-1.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nb-0.1.3\",\n        sha256 = \"801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/nb/0.1.3/download\"],\n        strip_prefix = \"nb-0.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.nb-0.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nb-1.1.0\",\n        sha256 = \"8d5439c4ad607c3c23abf66de8c8bf57ba8adcd1f129e699851a6e43935d339d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/nb/1.1.0/download\"],\n        strip_prefix = \"nb-1.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.nb-1.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__nom-7.1.3\",\n        sha256 = \"d273983c5a657a70a3e8f2a01329822f3b8c8172b73826411a55751e404a0a4a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/nom/7.1.3/download\"],\n        strip_prefix = \"nom-7.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.nom-7.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__object-0.37.3\",\n        sha256 = \"ff76201f031d8863c38aa7f905eca4f53abbfa15f609db4277d44cd8938f33fe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/object/0.37.3/download\"],\n        strip_prefix = \"object-0.37.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.object-0.37.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__once_cell_polyfill-1.70.2\",\n        sha256 = \"384b8ab6d37215f3c5301a95a4accb5d64aa607f1fcb26a11b5303878451b4fe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/once_cell_polyfill/1.70.2/download\"],\n        strip_prefix = \"once_cell_polyfill-1.70.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.once_cell_polyfill-1.70.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__opaque-debug-0.3.1\",\n        sha256 = \"c08d65885ee38876c4f86fa503fb49d7b507c2b62552df7c70b2fce627e06381\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/opaque-debug/0.3.1/download\"],\n        strip_prefix = \"opaque-debug-0.3.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.opaque-debug-0.3.1.bazel\"),\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__openprot-hal-blocking-0.1.0\",\n        commit = \"c6cd23a56f3cc7945b062ea1bcdabf3af0dba82d\",\n        init_submodules = True,\n        remote = \"https://github.com/rusty1968/openprot.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.openprot-hal-blocking-0.1.0.bazel\"),\n        strip_prefix = \"hal/blocking\",\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__p256-0.13.2\",\n        sha256 = \"c9863ad85fa8f4460f9c48cb909d38a0d689dba1f6f6988a5e3e0d31071bcd4b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/p256/0.13.2/download\"],\n        strip_prefix = \"p256-0.13.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.p256-0.13.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__p384-0.13.1\",\n        sha256 = \"fe42f1670a52a47d448f14b6a5c61dd78fce51856e68edaa38f7ae3a46b8d6b6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/p384/0.13.1/download\"],\n        strip_prefix = \"p384-0.13.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.p384-0.13.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__panic-halt-1.0.0\",\n        sha256 = \"a513e167849a384b7f9b746e517604398518590a9142f4846a32e3c2a4de7b11\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/panic-halt/1.0.0/download\"],\n        strip_prefix = \"panic-halt-1.0.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.panic-halt-1.0.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__parking_lot-0.12.5\",\n        sha256 = \"93857453250e3077bd71ff98b6a65ea6621a19bb0f559a85248955ac12c45a1a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/parking_lot/0.12.5/download\"],\n        strip_prefix = \"parking_lot-0.12.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.parking_lot-0.12.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__parking_lot_core-0.9.12\",\n        sha256 = \"2621685985a2ebf1c516881c026032ac7deafcda1a2c9b7850dc81e3dfcb64c1\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/parking_lot_core/0.9.12/download\"],\n        strip_prefix = \"parking_lot_core-0.9.12\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.parking_lot_core-0.9.12.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__paste-1.0.15\",\n        sha256 = \"57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/paste/1.0.15/download\"],\n        strip_prefix = \"paste-1.0.15\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.paste-1.0.15.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest-2.8.6\",\n        sha256 = \"e0848c601009d37dfa3430c4666e147e49cdcf1b92ecd3e63657d8a5f19da662\",\n        type = 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build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_generator-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pest_meta-2.8.6\",\n        sha256 = \"89815c69d36021a140146f26659a81d6c2afa33d216d736dd4be5381a7362220\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pest_meta/2.8.6/download\"],\n        strip_prefix = \"pest_meta-2.8.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pest_meta-2.8.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__pin-project-lite-0.2.17\",\n        sha256 = \"a89322df9ebe1c1578d689c92318e070967d1042b512afbe49518723f4e6d5cd\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/pin-project-lite/0.2.17/download\"],\n        strip_prefix = \"pin-project-lite-0.2.17\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.pin-project-lite-0.2.17.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__polyval-0.6.2\",\n        sha256 = \"9d1fe60d06143b2430aa532c94cfe9e29783047f06c0d7fd359a9a51b729fa25\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/polyval/0.6.2/download\"],\n        strip_prefix = \"polyval-0.6.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.polyval-0.6.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__primeorder-0.13.6\",\n        sha256 = \"353e1ca18966c16d9deb1c69278edbc5f194139612772bd9537af60ac231e1e6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/primeorder/0.13.6/download\"],\n        strip_prefix = \"primeorder-0.13.6\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.primeorder-0.13.6.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__proc-macro2-1.0.106\",\n        sha256 = \"8fd00f0bb2e90d81d1044c2b32617f68fcb9fa3bb7640c23e9c748e53fb30934\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/proc-macro2/1.0.106/download\"],\n        strip_prefix = \"proc-macro2-1.0.106\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.proc-macro2-1.0.106.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__prost-0.13.5\",\n        sha256 = \"2796faa41db3ec313a31f7624d9286acf277b52de526150b7e69f3debf891ee5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/prost/0.13.5/download\"],\n        strip_prefix = \"prost-0.13.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.prost-0.13.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__prost-derive-0.13.5\",\n        sha256 = \"8a56d757972c98b346a9b766e3f02746cde6dd1cd1d1d563472929fdd74bec4d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/prost-derive/0.13.5/download\"],\n        strip_prefix = \"prost-derive-0.13.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.prost-derive-0.13.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__quote-1.0.45\",\n        sha256 = \"41f2619966050689382d2b44f664f4bc593e129785a36d6ee376ddf37259b924\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/quote/1.0.45/download\"],\n        strip_prefix = \"quote-1.0.45\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.quote-1.0.45.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rand_core-0.6.4\",\n        sha256 = \"ec0be4795e2f6a28069bec0b5ff3e2ac9bafc99e6a9a7dc3547996c5c816922c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rand_core/0.6.4/download\"],\n        strip_prefix = \"rand_core-0.6.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rand_core-0.6.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rand_core-0.9.5\",\n        sha256 = \"76afc826de14238e6e8c374ddcc1fa19e374fd8dd986b0d2af0d02377261d83c\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rand_core/0.9.5/download\"],\n        strip_prefix = \"rand_core-0.9.5\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rand_core-0.9.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__redox_syscall-0.5.18\",\n        sha256 = \"ed2bf2547551a7053d6fdfafda3f938979645c44812fbfcda098faae3f1a362d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/redox_syscall/0.5.18/download\"],\n        strip_prefix = \"redox_syscall-0.5.18\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.redox_syscall-0.5.18.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rfc6979-0.4.0\",\n        sha256 = \"f8dd2a808d456c4a54e300a23e9f5a67e122c3024119acbfd73e3bf664491cb2\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rfc6979/0.4.0/download\"],\n        strip_prefix = \"rfc6979-0.4.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rfc6979-0.4.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.11.1\",\n        sha256 = \"2f5c1b8bf41ea746266cdee443d1d1e9125c86ce1447e1a2615abd34330d33a9\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.11.1/download\"],\n        strip_prefix = \"riscv-0.11.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.11.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.12.1\",\n        sha256 = \"5ea8ff73d3720bdd0a97925f0bf79ad2744b6da8ff36be3840c48ac81191d7a7\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.12.1/download\"],\n        strip_prefix = \"riscv-0.12.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.12.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-0.13.0\",\n        sha256 = \"afa3cdbeccae4359f6839a00e8b77e5736caa200ba216caf38d24e4c16e2b586\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv/0.13.0/download\"],\n        strip_prefix = \"riscv-0.13.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-0.13.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-macros-0.1.0\",\n        sha256 = \"f265be5d634272320a7de94cea15c22a3bfdd4eb42eb43edc528415f066a1f25\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-macros/0.1.0/download\"],\n        strip_prefix = \"riscv-macros-0.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-macros-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-macros-0.2.0\",\n        sha256 = \"e8c4aa1ea1af6dcc83a61be12e8189f9b293c3ba5a487778a4cd89fb060fdbbc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-macros/0.2.0/download\"],\n        strip_prefix = \"riscv-macros-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-macros-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-pac-0.2.0\",\n        sha256 = \"8188909339ccc0c68cfb5a04648313f09621e8b87dc03095454f1a11f6c5d436\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-pac/0.2.0/download\"],\n        strip_prefix = \"riscv-pac-0.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-pac-0.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-rt-0.12.2\",\n        sha256 = \"c0d35e32cf1383183e8885d8a9aa4402a087fd094dc34c2cb6df6687d0229dfe\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-rt/0.12.2/download\"],\n        strip_prefix = \"riscv-rt-0.12.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-rt-0.12.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-rt-macros-0.2.2\",\n        sha256 = \"30f19a85fe107b65031e0ba8ec60c34c2494069fe910d6c297f5e7cb5a6f76d0\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-rt-macros/0.2.2/download\"],\n        strip_prefix = \"riscv-rt-macros-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-rt-macros-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__riscv-semihosting-0.1.3\",\n        sha256 = \"1086dd4bcc13de1cb14b93849411e3466de7e5907d2d8eb269032536e93facc6\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/riscv-semihosting/0.1.3/download\"],\n        strip_prefix = \"riscv-semihosting-0.1.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.riscv-semihosting-0.1.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustc-demangle-0.1.27\",\n        sha256 = \"b50b8869d9fc858ce7266cce0194bd74df58b9d0e3f6df3a9fc8eb470d95c09d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustc-demangle/0.1.27/download\"],\n        strip_prefix = \"rustc-demangle-0.1.27\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustc-demangle-0.1.27.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustc_version-0.2.3\",\n        sha256 = \"138e3e0acb6c9fb258b19b67cb8abd63c00679d2851805ea151465464fe9030a\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustc_version/0.2.3/download\"],\n        strip_prefix = \"rustc_version-0.2.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustc_version-0.2.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__rustix-1.1.4\",\n        sha256 = \"b6fe4565b9518b83ef4f91bb47ce29620ca828bd32cb7e408f0062e9930ba190\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/rustix/1.1.4/download\"],\n        strip_prefix = \"rustix-1.1.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.rustix-1.1.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ruzstd-0.8.3\",\n        sha256 = \"a7c1c839d570d835527c9a5e4db7cb2198683a988cb9d7293fc8674e6bd58fc8\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ruzstd/0.8.3/download\"],\n        strip_prefix = \"ruzstd-0.8.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ruzstd-0.8.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__scopeguard-1.2.0\",\n        sha256 = \"94143f37725109f92c262ed2cf5e59bce7498c01bcc1502d7b9afe439a4e9f49\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/scopeguard/1.2.0/download\"],\n        strip_prefix = \"scopeguard-1.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.scopeguard-1.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sec1-0.7.3\",\n        sha256 = \"d3e97a565f76233a6003f9f5c54be1d9c5bdfa3eccfb189469f11ec4901c47dc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sec1/0.7.3/download\"],\n        strip_prefix = \"sec1-0.7.3\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sec1-0.7.3.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__semver-0.9.0\",\n        sha256 = \"1d7eb9ef2c18661902cc47e535f9bc51b78acd254da71d375c2f6720d9a40403\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/semver/0.9.0/download\"],\n        strip_prefix = \"semver-0.9.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.semver-0.9.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__semver-parser-0.7.0\",\n        sha256 = \"388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/semver-parser/0.7.0/download\"],\n        strip_prefix = \"semver-parser-0.7.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.semver-parser-0.7.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde-1.0.228\",\n        sha256 = \"9a8e94ea7f378bd32cbbd37198a4a91436180c5bb472411e48b5ec2e2124ae9e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde/1.0.228/download\"],\n        strip_prefix = \"serde-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_core-1.0.228\",\n        sha256 = \"41d385c7d4ca58e59fc732af25c3983b67ac852c1a25000afe1175de458b67ad\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_core/1.0.228/download\"],\n        strip_prefix = \"serde_core-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_core-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_derive-1.0.228\",\n        sha256 = \"d540f220d3187173da220f885ab66608367b6574e925011a9353e4badda91d79\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_derive/1.0.228/download\"],\n        strip_prefix = \"serde_derive-1.0.228\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_derive-1.0.228.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__serde_json5-0.2.1\",\n        sha256 = \"5d34d03f54462862f2a42918391c9526337f53171eaa4d8894562be7f252edd3\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/serde_json5/0.2.1/download\"],\n        strip_prefix = \"serde_json5-0.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.serde_json5-0.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sha2-0.10.9\",\n        sha256 = \"a7507d819769d01a365ab707794a4084392c824f54a7a6a7862f8c3d0892b283\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sha2/0.10.9/download\"],\n        strip_prefix = \"sha2-0.10.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sha2-0.10.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__sha3-0.10.9\",\n        sha256 = \"77fd7028345d415a4034cf8777cd4f8ab1851274233b45f84e3d955502d93874\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/sha3/0.10.9/download\"],\n        strip_prefix = \"sha3-0.10.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.sha3-0.10.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__signal-hook-registry-1.4.8\",\n        sha256 = \"c4db69cba1110affc0e9f7bcd48bbf87b3f4fc7c61fc9155afd4c469eb3d6c1b\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/signal-hook-registry/1.4.8/download\"],\n        strip_prefix = \"signal-hook-registry-1.4.8\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.signal-hook-registry-1.4.8.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__signature-2.2.0\",\n        sha256 = \"77549399552de45a898a580c1b41d445bf730df867cc44e6c0233bbc4b8329de\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/signature/2.2.0/download\"],\n        strip_prefix = \"signature-2.2.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.signature-2.2.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__simd-adler32-0.3.9\",\n        sha256 = \"703d5c7ef118737c72f1af64ad2f6f8c5e1921f818cdcb97b8fe6fc69bf66214\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/simd-adler32/0.3.9/download\"],\n        strip_prefix = \"simd-adler32-0.3.9\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.simd-adler32-0.3.9.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__slab-0.4.12\",\n        sha256 = \"0c790de23124f9ab44544d7ac05d60440adc586479ce501c1d6d7da3cd8c9cf5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/slab/0.4.12/download\"],\n        strip_prefix = \"slab-0.4.12\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.slab-0.4.12.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__smallvec-1.15.1\",\n        sha256 = \"67b1b7a3b5fe4f1376887184045fcf45c69e92af734b7aaddc05fb777b6fbd03\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/smallvec/1.15.1/download\"],\n        strip_prefix = \"smallvec-1.15.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.smallvec-1.15.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__smbus-pec-1.0.1\",\n        sha256 = \"ca0763a680cd5d72b28f7bfc8a054c117d8841380a6ad4f72f05bd2a34217d3e\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/smbus-pec/1.0.1/download\"],\n        strip_prefix = \"smbus-pec-1.0.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.smbus-pec-1.0.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__smlang-0.8.0\",\n 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[\"https://static.crates.io/crates/socket2/0.6.4/download\"],\n        strip_prefix = \"socket2-0.6.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.socket2-0.6.4.bazel\"),\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__spdm-lib-0.1.0\",\n        commit = \"41d81717f5d2b4d6b004819a829ae015e44febce\",\n        init_submodules = True,\n        remote = \"https://github.com/OpenPRoT/spdm-lib.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.spdm-lib-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__stable_deref_trait-1.2.1\",\n        sha256 = \"6ce2be8dc25455e1f91df71bfa12ad37d7af1092ae736f3a6cd0e37bc7810596\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/stable_deref_trait/1.2.1/download\"],\n        strip_prefix = \"stable_deref_trait-1.2.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.stable_deref_trait-1.2.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__string_morph-0.1.0\",\n        sha256 = \"183aaf7fa637cc7b5f54c45b8f7cb6e8d73831f9f75a56b6defa5bf8c51d1699\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/string_morph/0.1.0/download\"],\n        strip_prefix = \"string_morph-0.1.0\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.string_morph-0.1.0.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__strsim-0.11.1\",\n        sha256 = \"7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/strsim/0.11.1/download\"],\n        strip_prefix = \"strsim-0.11.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.strsim-0.11.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__subtle-2.6.1\",\n        sha256 = \"13c2bddecc57b384dee18652358fb23172facb8a2c51ccc10d74c157bdea3292\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/subtle/2.6.1/download\"],\n        strip_prefix = \"subtle-2.6.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.subtle-2.6.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__syn-1.0.109\",\n        sha256 = \"72b64191b275b66ffe2469e8af2c1cfe3bafa67b529ead792a6d0160888b4237\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/syn/1.0.109/download\"],\n        strip_prefix = \"syn-1.0.109\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.syn-1.0.109.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__syn-2.0.117\",\n        sha256 = \"e665b8803e7b1d2a727f4023456bbbbe74da67099c585258af0ad9c5013b9b99\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/syn/2.0.117/download\"],\n        strip_prefix = \"syn-2.0.117\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.syn-2.0.117.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__terminal_size-0.4.4\",\n        sha256 = \"230a1b821ccbd75b185820a1f1ff7b14d21da1e442e22c0863ea5f08771a8874\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/terminal_size/0.4.4/download\"],\n        strip_prefix = \"terminal_size-0.4.4\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.terminal_size-0.4.4.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__thiserror-2.0.18\",\n        sha256 = \"4288b5bcbc7920c07a1149a35cf9590a2aa808e0bc1eafaade0b80947865fbc4\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/thiserror/2.0.18/download\"],\n        strip_prefix = \"thiserror-2.0.18\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.thiserror-2.0.18.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__thiserror-impl-2.0.18\",\n        sha256 = \"ebc4ee7f67670e9b64d05fa4253e753e016c6c95ff35b89b7941d6b856dec1d5\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/thiserror-impl/2.0.18/download\"],\n        strip_prefix = \"thiserror-impl-2.0.18\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.thiserror-impl-2.0.18.bazel\"),\n    )\n\n    maybe(\n        git_repository,\n        name = \"rust_crates__tock-registers-0.9.0\",\n        commit = \"9554639b17501a9f5940cef7a1770a0823e790c3\",\n        init_submodules = True,\n        remote = \"https://github.com/tock/tock.git\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.tock-registers-0.9.0.bazel\"),\n        strip_prefix = \"libraries/tock-register-interface\",\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__tokio-1.52.3\",\n        sha256 = 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Label(\"@rust_crates//rust_crates:BUILD.typenum-1.20.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__ucd-trie-0.1.7\",\n        sha256 = \"2896d95c02a80c6d6a5d6e953d479f5ddf2dfdb6a244441010e373ac0fb88971\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/ucd-trie/0.1.7/download\"],\n        strip_prefix = \"ucd-trie-0.1.7\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.ucd-trie-0.1.7.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__unicode-ident-1.0.24\",\n        sha256 = \"e6e4313cd5fcd3dad5cafa179702e2b244f760991f45397d14d4ebf38247da75\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/unicode-ident/1.0.24/download\"],\n        strip_prefix = \"unicode-ident-1.0.24\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.unicode-ident-1.0.24.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__universal-hash-0.5.1\",\n        sha256 = \"fc1de2c688dc15305988b563c3854064043356019f97a4b46276fe734c4f07ea\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/universal-hash/0.5.1/download\"],\n        strip_prefix = \"universal-hash-0.5.1\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.universal-hash-0.5.1.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__utf8parse-0.2.2\",\n        sha256 = \"06abde3611657adf66d383f00b093d7faecc7fa57071cce2578660c9f1010821\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/utf8parse/0.2.2/download\"],\n        strip_prefix = \"utf8parse-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.utf8parse-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__uuid-1.23.2\",\n        sha256 = \"d258b83ceec21034727ecee8c382cfa6c3e133699b0742c64571814fb420c9f7\",\n        type = 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Label(\"@rust_crates//rust_crates:BUILD.version_check-0.9.5.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__void-1.0.2\",\n        sha256 = \"6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/void/1.0.2/download\"],\n        strip_prefix = \"void-1.0.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.void-1.0.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = \"rust_crates__volatile-register-0.2.2\",\n        sha256 = \"de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc\",\n        type = \"tar.gz\",\n        urls = [\"https://static.crates.io/crates/volatile-register/0.2.2/download\"],\n        strip_prefix = \"volatile-register-0.2.2\",\n        build_file = Label(\"@rust_crates//rust_crates:BUILD.volatile-register-0.2.2.bazel\"),\n    )\n\n    maybe(\n        http_archive,\n        name = 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build_file = Label(\"@rust_crates//rust_crates:BUILD.zeroize_derive-1.4.3.bazel\"),\n    )\n\n    return [\n       struct(repo=\"rust_crates__aes-0.8.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__aes-gcm-0.10.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__aligned-0.4.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__anyhow-1.0.102\", is_dev_dep = False),\n       struct(repo=\"rust_crates__bitfield-0.14.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__bitfield-struct-0.11.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__bitflags-2.12.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__byteorder-1.5.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cfg-if-1.0.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__cipher-0.4.4\", is_dev_dep = False),\n       struct(repo=\"rust_crates__clap-4.6.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__compiler_builtins-0.1.160\", is_dev_dep = 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struct(repo=\"rust_crates__openprot-hal-blocking-0.1.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__p256-0.13.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__p384-0.13.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__panic-halt-1.0.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__paste-1.0.15\", is_dev_dep = False),\n       struct(repo=\"rust_crates__proc-macro2-1.0.106\", is_dev_dep = False),\n       struct(repo=\"rust_crates__prost-0.13.5\", is_dev_dep = False),\n       struct(repo=\"rust_crates__quote-1.0.45\", is_dev_dep = False),\n       struct(repo=\"rust_crates__rand_core-0.9.5\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-0.12.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-rt-0.12.2\", is_dev_dep = False),\n       struct(repo=\"rust_crates__riscv-semihosting-0.1.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__rustc-demangle-0.1.27\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sec1-0.7.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde-1.0.228\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde_derive-1.0.228\", is_dev_dep = False),\n       struct(repo=\"rust_crates__serde_json5-0.2.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sha2-0.10.9\", is_dev_dep = False),\n       struct(repo=\"rust_crates__sha3-0.10.9\", is_dev_dep = False),\n       struct(repo=\"rust_crates__smlang-0.8.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__spdm-lib-0.1.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__subtle-2.6.1\", is_dev_dep = False),\n       struct(repo=\"rust_crates__syn-1.0.109\", is_dev_dep = False),\n       struct(repo=\"rust_crates__syn-2.0.117\", is_dev_dep = False),\n       struct(repo=\"rust_crates__thiserror-2.0.18\", is_dev_dep = False),\n       struct(repo=\"rust_crates__tock-registers-0.9.0\", is_dev_dep = False),\n       struct(repo=\"rust_crates__tokio-1.52.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__tokio-util-0.7.18\", is_dev_dep = False),\n       struct(repo=\"rust_crates__vcell-0.1.3\", is_dev_dep = False),\n       struct(repo=\"rust_crates__zerocopy-0.8.50\", is_dev_dep = False),\n       struct(repo=\"rust_crates__zeroize-1.8.2\", is_dev_dep = False),\n    ]\n"
               }
             }
           },
@@ -3296,7 +3296,7 @@
                 "https://static.crates.io/crates/cortex-m/0.7.7/download"
               ],
               "strip_prefix": "cortex-m-0.7.7",
-              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\n    \"@rules_rust//cargo:defs.bzl\",\n    \"cargo_build_script\",\n    \"cargo_toml_env_vars\",\n)\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"cortex_m\",\n    deps = [\n        \"@rust_crates__bare-metal-0.2.5//:bare_metal\",\n        \"@rust_crates__bitfield-0.13.2//:bitfield\",\n        \"@rust_crates__cortex-m-0.7.7//:build_script_build\",\n        \"@rust_crates__embedded-hal-0.2.7//:embedded_hal\",\n        \"@rust_crates__volatile-register-0.2.2//:volatile_register\",\n    ],\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_root = \"src/lib.rs\",\n    edition = \"2018\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=cortex-m\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:thumbv7em-none-eabi\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"0.7.7\",\n)\n\ncargo_build_script(\n    name = \"_bs\",\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \"**/*.rs\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_name = \"build_script_build\",\n    crate_root = \"build.rs\",\n    data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    edition = \"2018\",\n    links = \"cortex-m\",\n    pkg_name = \"cortex-m\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=cortex-m\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    version = \"0.7.7\",\n    visibility = [\"//visibility:private\"],\n)\n\nalias(\n    name = \"build_script_build\",\n    actual = \":_bs\",\n    tags = [\"manual\"],\n)\n"
+              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\n    \"@rules_rust//cargo:defs.bzl\",\n    \"cargo_build_script\",\n    \"cargo_toml_env_vars\",\n)\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"cortex_m\",\n    deps = [\n        \"@rust_crates__bare-metal-0.2.5//:bare_metal\",\n        \"@rust_crates__bitfield-0.13.2//:bitfield\",\n        \"@rust_crates__cortex-m-0.7.7//:build_script_build\",\n        \"@rust_crates__critical-section-1.2.0//:critical_section\",\n        \"@rust_crates__embedded-hal-0.2.7//:embedded_hal\",\n        \"@rust_crates__volatile-register-0.2.2//:volatile_register\",\n    ],\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"critical-section\",\n        \"critical-section-single-core\",\n    ],\n    crate_root = \"src/lib.rs\",\n    edition = \"2018\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=cortex-m\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:thumbv7em-none-eabi\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"0.7.7\",\n)\n\ncargo_build_script(\n    name = \"_bs\",\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \"**/*.rs\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"critical-section\",\n        \"critical-section-single-core\",\n    ],\n    crate_name = \"build_script_build\",\n    crate_root = \"build.rs\",\n    data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    edition = \"2018\",\n    links = \"cortex-m\",\n    pkg_name = \"cortex-m\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=cortex-m\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    version = \"0.7.7\",\n    visibility = [\"//visibility:private\"],\n)\n\nalias(\n    name = \"build_script_build\",\n    actual = \":_bs\",\n    tags = [\"manual\"],\n)\n"
             }
           },
           "rust_crates__cortex-m-rt-0.7.5": {
@@ -3424,7 +3424,7 @@
                 "https://static.crates.io/crates/critical-section/1.2.0/download"
               ],
               "strip_prefix": "critical-section-1.2.0",
-              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"critical_section\",\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_root = \"src/lib.rs\",\n    edition = \"2018\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=critical-section\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:thumbv7em-none-eabi\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"1.2.0\",\n)\n"
+              "build_file_content": "###############################################################################\n# @generated\n# DO NOT MODIFY: This file is auto-generated by a crate_universe tool. To \n# regenerate this file, run the following:\n#\n#     bazel mod show_repo 'openprot'\n###############################################################################\n\nload(\"@rules_rust//cargo:defs.bzl\", \"cargo_toml_env_vars\")\n\nload(\"@rules_rust//rust:defs.bzl\", \"rust_library\")\n\n# buildifier: disable=bzl-visibility\nload(\"@rules_rust//crate_universe/private:selects.bzl\", \"selects\")\n\npackage(default_visibility = [\"//visibility:public\"])\n\ncargo_toml_env_vars(\n    name = \"cargo_toml_env_vars\",\n    src = \"Cargo.toml\",\n)\n\nrust_library(\n    name = \"critical_section\",\n    compile_data = glob(\n        allow_empty = True,\n        include = [\"**\"],\n        exclude = [\n            \"**/* *\",\n            \".tmp_git_root/**/*\",\n            \"BUILD\",\n            \"BUILD.bazel\",\n            \"WORKSPACE\",\n            \"WORKSPACE.bazel\",\n        ],\n    ),\n    crate_features = [\n        \"restore-state-bool\",\n    ],\n    crate_root = \"src/lib.rs\",\n    edition = \"2018\",\n    rustc_env_files = [\n        \":cargo_toml_env_vars\",\n    ],\n    rustc_flags = [\n        \"--cap-lints=allow\",\n    ],\n    srcs = glob(\n        allow_empty = True,\n        include = [\"**/*.rs\"],\n    ),\n    tags = [\n        \"cargo-bazel\",\n        \"crate-name=critical-section\",\n        \"manual\",\n        \"noclippy\",\n        \"norustfmt\",\n    ],\n    target_compatible_with = select({\n        \"@rules_rust//rust/platform:aarch64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:aarch64-unknown-linux-gnu\": [],\n        \"@rules_rust//rust/platform:riscv32imc-unknown-none-elf\": [],\n        \"@rules_rust//rust/platform:thumbv7em-none-eabi\": [],\n        \"@rules_rust//rust/platform:x86_64-apple-darwin\": [],\n        \"@rules_rust//rust/platform:x86_64-unknown-linux-gnu\": [],\n        \"//conditions:default\": [\"@platforms//:incompatible\"],\n    }),\n    version = \"1.2.0\",\n)\n"
             }
           },
           "rust_crates__crypto-bigint-0.5.5": {
diff --git a/target/ast10x0/peripherals/BUILD.bazel b/target/ast10x0/peripherals/BUILD.bazel
index 450531bf..7d5a421a 100644
--- a/target/ast10x0/peripherals/BUILD.bazel
+++ b/target/ast10x0/peripherals/BUILD.bazel
@@ -24,6 +24,16 @@ rust_library(
         "i2c/timing.rs",
         "i2c/transfer.rs",
         "i2c/types.rs",
+        "i3c/ccc.rs",
+        "i3c/config.rs",
+        "i3c/constants.rs",
+        "i3c/controller.rs",
+        "i3c/error.rs",
+        "i3c/hardware.rs",
+        "i3c/ibi.rs",
+        "i3c/mod.rs",
+        "i3c/registers.rs",
+        "i3c/types.rs",
         "lib.rs",
         "scu/clock.rs",
         "scu/mod.rs",
@@ -67,10 +77,13 @@ rust_library(
         "@ast1060_pac",
         "@pigweed//pw_log/rust:pw_log",
         "@rust_crates//:bitflags",
+        "@rust_crates//:cortex-m",
+        "@rust_crates//:critical-section",
         "@rust_crates//:embedded-hal",
         "@rust_crates//:embedded-hal-nb",
         "@rust_crates//:embedded-io",
         "@rust_crates//:embedded-storage",
+        "@rust_crates//:heapless",
         "@rust_crates//:nb",
     ],
 )
diff --git a/target/ast10x0/peripherals/i3c/ccc.rs b/target/ast10x0/peripherals/i3c/ccc.rs
new file mode 100644
index 00000000..bd9bfdc4
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/ccc.rs
@@ -0,0 +1,763 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C Common Command Codes (CCC)
+//!
+//! Functions and types for executing I3C CCCs.
+
+use super::config::I3cConfig;
+use super::constants::{
+    I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE, I3C_CCC_GETBCR, I3C_CCC_GETDCR, I3C_CCC_GETMRL,
+    I3C_CCC_GETMWL, I3C_CCC_GETMXDS, I3C_CCC_GETPID, I3C_CCC_GETSTATUS, I3C_CCC_RSTDAA,
+    I3C_CCC_SETMRL, I3C_CCC_SETMRL_BC, I3C_CCC_SETMWL, I3C_CCC_SETMWL_BC, I3C_CCC_SETNEWDA,
+};
+use super::error::{CccErrorKind, I3cError};
+use super::hardware::HardwareInterface;
+
+// =============================================================================
+// CCC Types
+// =============================================================================
+
+/// CCC target payload for direct CCCs
+#[derive(Debug)]
+pub struct CccTargetPayload<'a> {
+    /// Target 7-bit dynamic address
+    pub addr: u8,
+    /// `false` = write, `true` = read
+    pub rnw: bool,
+    /// Data buffer for write (source) or read (destination)
+    pub data: Option<&'a mut [u8]>,
+    /// Actual bytes transferred (driver fills on return)
+    pub num_xfer: usize,
+}
+
+/// CCC descriptor
+#[derive(Debug)]
+pub struct Ccc<'a> {
+    /// CCC ID (command code)
+    pub id: u8,
+    /// Optional CCC data immediately following the CCC byte
+    pub data: Option<&'a mut [u8]>,
+    /// Actual bytes transferred (driver fills on return)
+    pub num_xfer: usize,
+}
+
+/// Complete CCC transaction description
+#[derive(Debug)]
+pub struct CccPayload<'a, 'b> {
+    /// The CCC command
+    pub ccc: Option<Ccc<'a>>,
+    /// Optional list of direct-CCC target payloads
+    pub targets: Option<&'b mut [CccTargetPayload<'a>]>,
+}
+
+// =============================================================================
+// CCC Reset Action
+// =============================================================================
+
+/// RSTACT defining byte values
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum CccRstActDefByte {
+    /// No reset
+    NoReset = 0x0,
+    /// Reset peripheral only
+    PeriphralOnly = 0x1,
+    /// Reset whole target
+    ResetWholeTarget = 0x2,
+    /// Debug network adapter
+    DebugNetworkAdapter = 0x3,
+    /// Virtual target detect
+    VirtualTargetDetect = 0x4,
+}
+
+impl CccRstActDefByte {
+    #[inline]
+    fn as_byte(self) -> u8 {
+        self as u8
+    }
+}
+
+// =============================================================================
+// GETSTATUS Types
+// =============================================================================
+
+/// GETSTATUS format selection
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum GetStatusFormat {
+    /// Format 1 (no defining byte)
+    Fmt1,
+    /// Format 2 (with defining byte)
+    Fmt2(GetStatusDefByte),
+}
+
+/// GETSTATUS defining byte values
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum GetStatusDefByte {
+    /// 0x00 - TGTSTAT
+    TgtStat,
+    /// 0x91 - PRECR
+    Precr,
+}
+
+impl GetStatusDefByte {
+    #[inline]
+    fn as_byte(self) -> u8 {
+        match self {
+            Self::TgtStat => 0x00,
+            Self::Precr => 0x91,
+        }
+    }
+}
+
+/// GETSTATUS response
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum GetStatusResp {
+    /// Format 1 response
+    Fmt1 { status: u16 },
+    /// Format 2 response
+    Fmt2 {
+        kind: GetStatusDefByte,
+        raw_u16: u16,
+    },
+}
+
+// =============================================================================
+// CCC Helper Functions
+// =============================================================================
+
+const fn ccc_enec(broadcast: bool) -> u8 {
+    if broadcast {
+        0x00
+    } else {
+        0x80
+    }
+}
+
+const fn ccc_disec(broadcast: bool) -> u8 {
+    if broadcast {
+        0x01
+    } else {
+        0x81
+    }
+}
+
+const fn ccc_rstact(broadcast: bool) -> u8 {
+    if broadcast {
+        0x2a
+    } else {
+        0x9a
+    }
+}
+
+// =============================================================================
+// CCC Operations
+// =============================================================================
+
+/// Enable/disable events for all devices (broadcast)
+pub fn ccc_events_all_set<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    enable: bool,
+    events: u8,
+) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    let id = if enable {
+        ccc_enec(true)
+    } else {
+        ccc_disec(true)
+    };
+
+    hw.do_ccc(
+        config,
+        &mut CccPayload {
+            ccc: Some(Ccc {
+                id,
+                data: Some(&mut [events]),
+                num_xfer: 0,
+            }),
+            targets: None,
+        },
+    )
+    .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
+
+/// Enable/disable events for a specific device (direct)
+pub fn ccc_events_set<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    da: u8,
+    enable: bool,
+    events: u8,
+) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    if da == 0 {
+        return Err(I3cError::CccError(CccErrorKind::InvalidParam));
+    }
+
+    let mut ev_buf = [events];
+    let tgt = CccTargetPayload {
+        addr: da,
+        rnw: false,
+        data: Some(&mut ev_buf[..]),
+        num_xfer: 0,
+    };
+
+    let mut tgts = [tgt];
+    let ccc_id = if enable {
+        ccc_enec(false)
+    } else {
+        ccc_disec(false)
+    };
+    let ccc = Ccc {
+        id: ccc_id,
+        data: None,
+        num_xfer: 0,
+    };
+
+    let mut payload = CccPayload {
+        ccc: Some(ccc),
+        targets: Some(&mut tgts[..]),
+    };
+
+    hw.do_ccc(config, &mut payload)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
+
+/// Execute RSTACT (Reset Action) broadcast
+pub fn ccc_rstact_all<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    action: CccRstActDefByte,
+) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    let mut db = [action.as_byte()];
+    let ccc = Ccc {
+        id: ccc_rstact(true),
+        data: Some(&mut db[..]),
+        num_xfer: 0,
+    };
+    let mut payload = CccPayload {
+        ccc: Some(ccc),
+        targets: None,
+    };
+
+    hw.do_ccc(config, &mut payload)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
+
+/// Get BCR (Bus Characteristics Register) from a device
+pub fn ccc_getbcr<H>(hw: &mut H, config: &mut I3cConfig, dyn_addr: u8) -> Result<u8, I3cError>
+where
+    H: HardwareInterface,
+{
+    if dyn_addr == 0 {
+        return Err(I3cError::CccError(CccErrorKind::InvalidParam));
+    }
+
+    let mut bcr_buf = [0u8; 1];
+
+    let tgt = CccTargetPayload {
+        addr: dyn_addr,
+        rnw: true,
+        data: Some(&mut bcr_buf[..]),
+        num_xfer: 0,
+    };
+    let mut tgts = [tgt];
+
+    let ccc = Ccc {
+        id: I3C_CCC_GETBCR,
+        data: None,
+        num_xfer: 0,
+    };
+    let mut payload = CccPayload {
+        ccc: Some(ccc),
+        targets: Some(&mut tgts[..]),
+    };
+
+    hw.do_ccc(config, &mut payload)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))?;
+
+    Ok(bcr_buf[0])
+}
+
+/// Get DCR (Device Characteristics Register) from a device
+pub fn ccc_getdcr<H>(hw: &mut H, config: &mut I3cConfig, dyn_addr: u8) -> Result<u8, I3cError>
+where
+    H: HardwareInterface,
+{
+    if dyn_addr == 0 {
+        return Err(I3cError::CccError(CccErrorKind::InvalidParam));
+    }
+
+    let mut dcr_buf = [0u8; 1];
+
+    let tgt = CccTargetPayload {
+        addr: dyn_addr,
+        rnw: true,
+        data: Some(&mut dcr_buf[..]),
+        num_xfer: 0,
+    };
+    let mut tgts = [tgt];
+
+    let ccc = Ccc {
+        id: I3C_CCC_GETDCR,
+        data: None,
+        num_xfer: 0,
+    };
+    let mut payload = CccPayload {
+        ccc: Some(ccc),
+        targets: Some(&mut tgts[..]),
+    };
+
+    hw.do_ccc(config, &mut payload)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))?;
+
+    Ok(dcr_buf[0])
+}
+
+/// Bus-only SETNEWDA: send the CCC, touch **no** bookkeeping or DAT state.
+///
+/// For the DAA engine (`I3cController::bus_daa`), which addresses a device
+/// that answered on a *different* entry's address (mis-assignment /
+/// unsolicited cases) and manages the tables itself. Everyone else should use
+/// [`ccc_setnewda`].
+pub(crate) fn ccc_setnewda_bus_only<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    curr_da: u8,
+    new_da: u8,
+) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    if curr_da == 0 || new_da == 0 {
+        return Err(I3cError::CccError(CccErrorKind::InvalidParam));
+    }
+
+    let mut new_dyn_addr = (new_da & 0x7F) << 1;
+    let tgt = CccTargetPayload {
+        addr: curr_da,
+        rnw: false,
+        data: Some(core::slice::from_mut(&mut new_dyn_addr)),
+        num_xfer: 0,
+    };
+    let mut tgts = [tgt];
+    let ccc = Ccc {
+        id: I3C_CCC_SETNEWDA,
+        data: None,
+        num_xfer: 0,
+    };
+    let mut payload = CccPayload {
+        ccc: Some(ccc),
+        targets: Some(&mut tgts[..]),
+    };
+
+    hw.do_ccc(config, &mut payload)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
+
+/// Set new dynamic address for a device
+pub fn ccc_setnewda<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    curr_da: u8,
+    new_da: u8,
+) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    let Some(pos) = config.attached.pos_of_addr(curr_da) else {
+        return Err(I3cError::CccError(CccErrorKind::NotFound));
+    };
+
+    if !config.addrbook.is_free(new_da) {
+        return Err(I3cError::CccError(CccErrorKind::NoFreeSlot));
+    }
+
+    ccc_setnewda_bus_only(hw, config, curr_da, new_da)?;
+
+    // The device now answers on `new_da`: mirror the move into the address
+    // book / attached table and reprogram the DAT slot, or every subsequent
+    // private transfer would still address the device through the stale entry.
+    // The fresh DAT write restores the SIR/MR-reject defaults — call
+    // `ibi_enable` again afterwards if the device had IBIs enabled.
+    config
+        .reassign_da(curr_da, new_da)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))?;
+    hw.attach_i3c_dev(pos.into(), new_da)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
+
+/// Send a direct write CCC with a small fixed payload.
+fn ccc_direct_write<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    id: u8,
+    da: u8,
+    payload: &mut [u8],
+) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    if da == 0 {
+        return Err(I3cError::CccError(CccErrorKind::InvalidParam));
+    }
+    let tgt = CccTargetPayload {
+        addr: da,
+        rnw: false,
+        data: Some(payload),
+        num_xfer: 0,
+    };
+    let mut tgts = [tgt];
+    let mut p = CccPayload {
+        ccc: Some(Ccc {
+            id,
+            data: None,
+            num_xfer: 0,
+        }),
+        targets: Some(&mut tgts[..]),
+    };
+    hw.do_ccc(config, &mut p)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
+
+/// Send a direct read CCC into a small fixed buffer.
+fn ccc_direct_read<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    id: u8,
+    da: u8,
+    out: &mut [u8],
+) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    if da == 0 {
+        return Err(I3cError::CccError(CccErrorKind::InvalidParam));
+    }
+    let tgt = CccTargetPayload {
+        addr: da,
+        rnw: true,
+        data: Some(out),
+        num_xfer: 0,
+    };
+    let mut tgts = [tgt];
+    let mut p = CccPayload {
+        ccc: Some(Ccc {
+            id,
+            data: None,
+            num_xfer: 0,
+        }),
+        targets: Some(&mut tgts[..]),
+    };
+    hw.do_ccc(config, &mut p)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
+
+/// Set Maximum Write Length for a device (direct SETMWL); mirrors the value
+/// into the attached-device entry on success.
+pub fn ccc_setmwl<H>(hw: &mut H, config: &mut I3cConfig, da: u8, mwl: u16) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    let mut payload = mwl.to_be_bytes();
+    ccc_direct_write(hw, config, I3C_CCC_SETMWL, da, &mut payload)?;
+    if let Some(idx) = config.attached.find_dev_idx_by_addr(da)
+        && let Some(dev) = config.attached.devices.get_mut(idx)
+    {
+        dev.mwl = mwl;
+    }
+    Ok(())
+}
+
+/// Set Maximum Read Length for a device (direct SETMRL). `ibi_len` adds the
+/// optional third byte (max IBI payload size) for targets whose BCR
+/// advertises an IBI payload. Mirrors the values into the attached-device
+/// entry on success.
+pub fn ccc_setmrl<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    da: u8,
+    mrl: u16,
+    ibi_len: Option<u8>,
+) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    let be = mrl.to_be_bytes();
+    let mut buf3 = [be[0], be[1], 0];
+    let payload: &mut [u8] = match ibi_len {
+        Some(n) => {
+            buf3[2] = n;
+            &mut buf3[..3]
+        }
+        None => &mut buf3[..2],
+    };
+    ccc_direct_write(hw, config, I3C_CCC_SETMRL, da, payload)?;
+    if let Some(idx) = config.attached.find_dev_idx_by_addr(da)
+        && let Some(dev) = config.attached.devices.get_mut(idx)
+    {
+        dev.mrl = mrl;
+        if let Some(n) = ibi_len {
+            dev.max_ibi = n;
+        }
+    }
+    Ok(())
+}
+
+/// Broadcast SETMWL to all devices.
+pub fn ccc_setmwl_all<H>(hw: &mut H, config: &mut I3cConfig, mwl: u16) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    let mut payload = mwl.to_be_bytes();
+    hw.do_ccc(
+        config,
+        &mut CccPayload {
+            ccc: Some(Ccc {
+                id: I3C_CCC_SETMWL_BC,
+                data: Some(&mut payload[..]),
+                num_xfer: 0,
+            }),
+            targets: None,
+        },
+    )
+    .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
+
+/// Broadcast SETMRL to all devices.
+pub fn ccc_setmrl_all<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    mrl: u16,
+    ibi_len: Option<u8>,
+) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    let be = mrl.to_be_bytes();
+    let mut buf3 = [be[0], be[1], 0];
+    let payload: &mut [u8] = match ibi_len {
+        Some(n) => {
+            buf3[2] = n;
+            &mut buf3[..3]
+        }
+        None => &mut buf3[..2],
+    };
+    hw.do_ccc(
+        config,
+        &mut CccPayload {
+            ccc: Some(Ccc {
+                id: I3C_CCC_SETMRL_BC,
+                data: Some(payload),
+                num_xfer: 0,
+            }),
+            targets: None,
+        },
+    )
+    .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
+
+/// Get Maximum Write Length from a device (GETMWL); mirrors the value into
+/// the attached-device entry.
+pub fn ccc_getmwl<H>(hw: &mut H, config: &mut I3cConfig, da: u8) -> Result<u16, I3cError>
+where
+    H: HardwareInterface,
+{
+    let mut buf = [0u8; 2];
+    ccc_direct_read(hw, config, I3C_CCC_GETMWL, da, &mut buf)?;
+    let mwl = u16::from_be_bytes(buf);
+    if let Some(idx) = config.attached.find_dev_idx_by_addr(da)
+        && let Some(dev) = config.attached.devices.get_mut(idx)
+    {
+        dev.mwl = mwl;
+    }
+    Ok(mwl)
+}
+
+/// Get Maximum Read Length from a device (GETMRL).
+///
+/// Returns `(mrl, max_ibi_len)`; the third response byte is present only for
+/// targets whose BCR advertises an IBI payload (the attached entry's BCR
+/// decides how many bytes are requested). Mirrors the values into the
+/// attached-device entry.
+pub fn ccc_getmrl<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    da: u8,
+) -> Result<(u16, Option<u8>), I3cError>
+where
+    H: HardwareInterface,
+{
+    let has_ibi_byte = config
+        .attached
+        .find_dev_idx_by_addr(da)
+        .and_then(|idx| config.attached.devices.get(idx))
+        .map(|d| u32::from(d.bcr) & I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE != 0)
+        .unwrap_or(false);
+
+    let mut buf = [0u8; 3];
+    let want = if has_ibi_byte { 3 } else { 2 };
+    // `want` is 2 or 3, always within the buffer.
+    let out = buf.get_mut(..want).ok_or(I3cError::Invalid)?;
+    ccc_direct_read(hw, config, I3C_CCC_GETMRL, da, out)?;
+
+    let mrl = u16::from_be_bytes([buf[0], buf[1]]);
+    let ibi_len = has_ibi_byte.then_some(buf[2]);
+    if let Some(idx) = config.attached.find_dev_idx_by_addr(da)
+        && let Some(dev) = config.attached.devices.get_mut(idx)
+    {
+        dev.mrl = mrl;
+        if let Some(n) = ibi_len {
+            dev.max_ibi = n;
+        }
+    }
+    Ok((mrl, ibi_len))
+}
+
+/// Get Max Data Speed from a device (GETMXDS format 1).
+///
+/// Returns `(max_wr, max_rd)` raw speed bytes; mirrored into the
+/// attached-device entry.
+pub fn ccc_getmxds<H>(hw: &mut H, config: &mut I3cConfig, da: u8) -> Result<(u8, u8), I3cError>
+where
+    H: HardwareInterface,
+{
+    let mut buf = [0u8; 2];
+    ccc_direct_read(hw, config, I3C_CCC_GETMXDS, da, &mut buf)?;
+    let (max_wr, max_rd) = (buf[0], buf[1]);
+    if let Some(idx) = config.attached.find_dev_idx_by_addr(da)
+        && let Some(dev) = config.attached.devices.get_mut(idx)
+    {
+        dev.maxwr = max_wr;
+        dev.maxrd = max_rd;
+    }
+    Ok((max_wr, max_rd))
+}
+
+fn bytes_to_pid(bytes: &[u8]) -> u64 {
+    bytes
+        .iter()
+        .take(6)
+        .fold(0u64, |acc, &b| (acc << 8) | u64::from(b))
+}
+
+/// Get PID (Provisional ID) from a device
+pub fn ccc_getpid<H>(hw: &mut H, config: &mut I3cConfig, dyn_addr: u8) -> Result<u64, I3cError>
+where
+    H: HardwareInterface,
+{
+    let mut pid_buf = [0u8; 6];
+
+    let tgt = CccTargetPayload {
+        addr: dyn_addr,
+        rnw: true,
+        data: Some(&mut pid_buf[..]),
+        num_xfer: 0,
+    };
+    let mut tgts = [tgt];
+
+    let ccc = Ccc {
+        id: I3C_CCC_GETPID,
+        data: None,
+        num_xfer: 0,
+    };
+    let mut payload = CccPayload {
+        ccc: Some(ccc),
+        targets: Some(&mut tgts[..]),
+    };
+
+    hw.do_ccc(config, &mut payload)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))?;
+
+    Ok(bytes_to_pid(&pid_buf))
+}
+
+/// Get status from a device
+pub fn ccc_getstatus<H>(
+    hw: &mut H,
+    config: &mut I3cConfig,
+    da: u8,
+    fmt: GetStatusFormat,
+) -> Result<GetStatusResp, I3cError>
+where
+    H: HardwareInterface,
+{
+    let mut data_buf = [0u8; 2];
+    let mut defbyte_buf = [0u8; 1];
+
+    let tgt = CccTargetPayload {
+        addr: da,
+        rnw: true,
+        data: Some(&mut data_buf[..]),
+        num_xfer: 0,
+    };
+
+    let mut ccc = Ccc {
+        id: I3C_CCC_GETSTATUS,
+        data: None,
+        num_xfer: 0,
+    };
+
+    let kind_opt = match fmt {
+        GetStatusFormat::Fmt1 => None,
+        GetStatusFormat::Fmt2(kind) => {
+            defbyte_buf[0] = kind.as_byte();
+            ccc.data = Some(&mut defbyte_buf[..]);
+            Some(kind)
+        }
+    };
+
+    let mut targets_arr = [tgt];
+    let mut payload = CccPayload {
+        ccc: Some(ccc),
+        targets: Some(&mut targets_arr[..]),
+    };
+
+    hw.do_ccc(config, &mut payload)
+        .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))?;
+
+    let val = u16::from_be_bytes(data_buf);
+
+    let resp = match kind_opt {
+        None => GetStatusResp::Fmt1 { status: val },
+        Some(kind) => GetStatusResp::Fmt2 { kind, raw_u16: val },
+    };
+    Ok(resp)
+}
+
+/// Get status (Format 1) from a device
+pub fn ccc_getstatus_fmt1<H>(hw: &mut H, config: &mut I3cConfig, da: u8) -> Result<u16, I3cError>
+where
+    H: HardwareInterface,
+{
+    match ccc_getstatus(hw, config, da, GetStatusFormat::Fmt1) {
+        Ok(GetStatusResp::Fmt1 { status }) => Ok(status),
+        _ => Err(I3cError::CccError(CccErrorKind::Invalid)),
+    }
+}
+
+/// Reset dynamic address assignment for all devices (broadcast)
+pub fn ccc_rstdaa_all<H>(hw: &mut H, config: &mut I3cConfig) -> Result<(), I3cError>
+where
+    H: HardwareInterface,
+{
+    hw.do_ccc(
+        config,
+        &mut CccPayload {
+            ccc: Some(Ccc {
+                id: I3C_CCC_RSTDAA,
+                data: None,
+                num_xfer: 0,
+            }),
+            targets: None,
+        },
+    )
+    .map_err(|_| I3cError::CccError(CccErrorKind::Invalid))
+}
diff --git a/target/ast10x0/peripherals/i3c/config.rs b/target/ast10x0/peripherals/i3c/config.rs
new file mode 100644
index 00000000..2665dab6
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/config.rs
@@ -0,0 +1,702 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C configuration types
+//!
+//! Configuration structures for I3C controller and devices.
+
+use core::marker::PhantomData;
+use heapless::Vec;
+
+use super::error::I3cError;
+use super::types::DevKind;
+
+// =============================================================================
+// Target Configuration
+// =============================================================================
+
+/// Configuration for I3C target mode
+pub struct I3cTargetConfig {
+    /// Target flags
+    pub flags: u8,
+    /// Dynamic address (assigned by controller)
+    pub addr: Option<u8>,
+    /// Mandatory Data Byte for IBI
+    pub mdb: u8,
+}
+
+impl I3cTargetConfig {
+    /// Create a new target configuration
+    #[must_use]
+    pub const fn new(flags: u8, addr: Option<u8>, mdb: u8) -> Self {
+        Self { flags, addr, mdb }
+    }
+}
+
+// =============================================================================
+// Address Book
+// =============================================================================
+
+/// Address allocation and tracking for I3C bus
+pub struct AddrBook {
+    /// Bitmap (128 bits) of addresses currently in use.
+    in_use: [u32; 4],
+    /// Bitmap (128 bits) of reserved addresses (not available for allocation).
+    reserved: [u32; 4],
+}
+
+impl AddrBook {
+    /// Read bit `addr` (0..=127) of a 128-bit map. The `& 3` index keeps this
+    /// panic-free (provably in `0..4`) for the `no_panics` analysis.
+    #[inline]
+    fn bit_get(bits: &[u32; 4], addr: u8) -> bool {
+        let i = addr as usize;
+        (bits[(i >> 5) & 3] >> (i & 31)) & 1 != 0
+    }
+
+    /// Set/clear bit `addr` (0..=127) of a 128-bit map (panic-free).
+    #[inline]
+    fn bit_set(bits: &mut [u32; 4], addr: u8, val: bool) {
+        let i = addr as usize;
+        let mask = 1u32 << (i & 31);
+        if val {
+            bits[(i >> 5) & 3] |= mask;
+        } else {
+            bits[(i >> 5) & 3] &= !mask;
+        }
+    }
+}
+
+impl Default for AddrBook {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl AddrBook {
+    /// Create a new empty address book
+    #[must_use]
+    pub const fn new() -> Self {
+        Self {
+            in_use: [0; 4],
+            reserved: [0; 4],
+        }
+    }
+
+    /// Check if an address is free (not in use and not reserved)
+    #[inline]
+    #[must_use]
+    pub fn is_free(&self, addr: u8) -> bool {
+        !Self::bit_get(&self.in_use, addr) && !Self::bit_get(&self.reserved, addr)
+    }
+
+    /// Reserve default I3C addresses per specification
+    ///
+    /// Reserves addresses 0-7, 0x7E (broadcast), and addresses that
+    /// differ from 0x7E by a single bit.
+    pub fn reserve_defaults(&mut self) {
+        // Reserve addresses 0-7
+        for a in 0u8..=7 {
+            Self::bit_set(&mut self.reserved, a, true);
+        }
+        // Reserve broadcast address
+        Self::bit_set(&mut self.reserved, 0x7E, true);
+        // Reserve addresses differing from 0x7E by single bit
+        for i in 0..=7 {
+            let alt = 0x7E ^ (1u8 << i);
+            if alt <= 0x7E {
+                Self::bit_set(&mut self.reserved, alt, true);
+            }
+        }
+    }
+
+    /// Allocate an address starting from the given value
+    ///
+    /// Returns `Some(addr)` if an address was found, `None` if exhausted.
+    pub fn alloc_from(&mut self, start: u8) -> Option<u8> {
+        let mut addr = start.max(8);
+        while addr < 0x7F {
+            if self.is_free(addr) {
+                return Some(addr);
+            }
+            addr += 1;
+        }
+        None
+    }
+
+    /// Mark an address as used or free
+    #[inline]
+    pub fn mark_use(&mut self, addr: u8, used: bool) {
+        if addr != 0 {
+            Self::bit_set(&mut self.in_use, addr, used);
+        }
+    }
+}
+
+// =============================================================================
+// Device Entry
+// =============================================================================
+
+/// Entry for a device attached to the I3C bus
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub struct DeviceEntry {
+    /// Device type (I3C or I2C)
+    pub kind: DevKind,
+    /// Provisional ID (for I3C devices)
+    pub pid: Option<u64>,
+    /// Static address (for I2C or SETDASA)
+    pub static_addr: u8,
+    /// Current dynamic address
+    pub dyn_addr: u8,
+    /// Desired dynamic address
+    pub desired_da: u8,
+    /// Bus Characteristics Register
+    pub bcr: u8,
+    /// Device Characteristics Register
+    pub dcr: u8,
+    /// Maximum read speed
+    pub maxrd: u8,
+    /// Maximum write speed
+    pub maxwr: u8,
+    /// Maximum read length
+    pub mrl: u16,
+    /// Maximum write length
+    pub mwl: u16,
+    /// Maximum IBI payload size
+    pub max_ibi: u8,
+    /// IBI enabled flag
+    pub ibi_en: bool,
+    /// Position in DAT (Device Address Table)
+    pub pos: Option<u8>,
+    /// Dynamic address verified on the bus (set by DAA once the device's PID
+    /// was read back at its address). Cleared state means the entry is only a
+    /// reservation.
+    pub da_assigned: bool,
+}
+
+impl DeviceEntry {
+    /// Create a new I3C device entry
+    #[must_use]
+    pub const fn new_i3c(pid: u64, desired_da: u8) -> Self {
+        Self {
+            kind: DevKind::I3c,
+            pid: Some(pid),
+            static_addr: 0,
+            dyn_addr: desired_da,
+            desired_da,
+            bcr: 0,
+            dcr: 0,
+            maxrd: 0,
+            maxwr: 0,
+            mrl: 0,
+            mwl: 0,
+            max_ibi: 0,
+            ibi_en: false,
+            pos: None,
+            da_assigned: false,
+        }
+    }
+
+    /// Create a new I2C device entry
+    #[must_use]
+    pub const fn new_i2c(static_addr: u8) -> Self {
+        Self {
+            kind: DevKind::I2c,
+            pid: None,
+            static_addr,
+            dyn_addr: static_addr,
+            desired_da: static_addr,
+            bcr: 0,
+            dcr: 0,
+            maxrd: 0,
+            maxwr: 0,
+            mrl: 0,
+            mwl: 0,
+            max_ibi: 0,
+            ibi_en: false,
+            pos: None,
+            da_assigned: false,
+        }
+    }
+}
+
+// =============================================================================
+// Attached Devices
+// =============================================================================
+
+/// Collection of devices attached to the I3C bus
+pub struct Attached {
+    /// Device entries (max 8 devices)
+    pub devices: Vec<DeviceEntry, 8>,
+    /// Position-to-index mapping
+    pub by_pos: [Option<u8>; 8],
+}
+
+impl Default for Attached {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl Attached {
+    /// Create a new empty attached devices collection
+    #[must_use]
+    pub const fn new() -> Self {
+        Self {
+            devices: Vec::new(),
+            by_pos: [None; 8],
+        }
+    }
+
+    /// Attach a device to the bus
+    ///
+    /// Returns the device index on success.
+    pub fn attach(&mut self, dev: DeviceEntry) -> Result<usize, I3cError> {
+        let idx = self.devices.len();
+        self.devices.push(dev).map_err(|_| I3cError::NoFreeSlot)?;
+        Ok(idx)
+    }
+
+    /// Detach a device by its index
+    pub fn detach(&mut self, dev_idx: usize) {
+        if dev_idx >= self.devices.len() {
+            return;
+        }
+
+        // Clear position mapping if device had one
+        if let Some(pos) = self.devices[dev_idx].pos
+            && let Some(p) = self.by_pos.get_mut(pos as usize)
+        {
+            *p = None;
+        }
+
+        // Remove device and update position mappings
+        self.devices.remove(dev_idx);
+        for bp in &mut self.by_pos {
+            if let Some(idx) = bp {
+                let idx_usize = *idx as usize;
+                if idx_usize > dev_idx && idx_usize > 0 {
+                    // SAFETY: Saturating subtract to prevent panic on underflow
+                    *bp = Some(idx.saturating_sub(1));
+                }
+            }
+        }
+    }
+
+    /// Detach a device by its DAT position
+    pub fn detach_by_pos(&mut self, pos: usize) {
+        if let Some(Some(dev_idx)) = self.by_pos.get(pos) {
+            self.detach(*dev_idx as usize);
+        }
+    }
+
+    /// Get the DAT position of a device by its index
+    #[must_use]
+    pub fn pos_of(&self, dev_idx: usize) -> Option<u8> {
+        let dev_idx_u8 = u8::try_from(dev_idx).ok()?;
+        self.by_pos
+            .iter()
+            .enumerate()
+            .find_map(|(pos, &v)| (v == Some(dev_idx_u8)).then_some(pos))
+            .and_then(|p| u8::try_from(p).ok())
+    }
+
+    /// Find device index by dynamic address
+    #[must_use]
+    pub fn find_dev_idx_by_addr(&self, da: u8) -> Option<usize> {
+        self.devices.iter().position(|d| d.dyn_addr == da)
+    }
+
+    /// Get DAT position by dynamic address
+    #[must_use]
+    pub fn pos_of_addr(&self, da: u8) -> Option<u8> {
+        let dev_idx = self.devices.iter().position(|d| d.dyn_addr == da)?;
+        self.pos_of(dev_idx)
+    }
+
+    /// Get DAT position by PID
+    #[must_use]
+    pub fn pos_of_pid(&self, pid: u64) -> Option<u8> {
+        let dev_idx = self.devices.iter().position(|d| d.pid == Some(pid))?;
+        self.pos_of(dev_idx)
+    }
+
+    /// Find device index by static address (legacy I2C devices)
+    #[must_use]
+    pub fn find_dev_idx_by_static_addr(&self, addr: u8) -> Option<usize> {
+        self.devices
+            .iter()
+            .position(|d| d.kind == DevKind::I2c && d.static_addr == addr)
+    }
+
+    /// Get DAT position by static address (legacy I2C devices)
+    #[must_use]
+    pub fn pos_of_static_addr(&self, addr: u8) -> Option<u8> {
+        let dev_idx = self.find_dev_idx_by_static_addr(addr)?;
+        self.pos_of(dev_idx)
+            .or_else(|| self.devices.get(dev_idx).and_then(|d| d.pos))
+    }
+
+    /// Map a DAT position to a device index
+    #[inline]
+    pub fn map_pos(&mut self, pos: u8, idx: u8) -> bool {
+        if let Some(slot) = self.by_pos.get_mut(pos as usize) {
+            *slot = Some(idx);
+            return true;
+        }
+        false
+    }
+
+    /// Unmap a DAT position
+    #[inline]
+    pub fn unmap_pos(&mut self, pos: u8) {
+        self.by_pos[pos as usize] = None;
+    }
+}
+
+// =============================================================================
+// Common State
+// =============================================================================
+
+/// Common state shared across configurations (placeholder)
+#[derive(Default)]
+pub struct CommonState {
+    _phantom: PhantomData<()>,
+}
+
+/// Common configuration (placeholder)
+#[derive(Default)]
+pub struct CommonCfg {
+    _phantom: PhantomData<()>,
+}
+
+// =============================================================================
+// Reset Specification
+// =============================================================================
+
+/// Reset line specification
+#[derive(Clone, Copy)]
+pub struct ResetSpec {
+    /// Reset line ID
+    pub id: u32,
+    /// Whether reset is active high
+    pub active_high: bool,
+}
+
+// =============================================================================
+// Main Configuration
+// =============================================================================
+
+/// Main I3C bus configuration
+pub struct I3cConfig {
+    /// Common higher-level state
+    pub common: CommonState,
+    /// Target mode configuration (if operating as target)
+    pub target_config: Option<I3cTargetConfig>,
+    /// Address book for dynamic address management
+    pub addrbook: AddrBook,
+    /// Collection of attached devices
+    pub attached: Attached,
+
+    // Clock configuration
+    /// Core clock frequency in Hz (injected by platform)
+    ///
+    /// If `None`, hardware implementation may auto-detect or use a default.
+    /// Providing this value decouples I3C from SCU/clock tree access.
+    pub core_clk_hz: Option<u32>,
+
+    // Timing/PHY parameters (nanoseconds, computed from core_clk_hz)
+    /// Core clock period in ns (computed during init)
+    pub core_period: u32,
+    /// I2C SCL frequency in Hz
+    pub i2c_scl_hz: u32,
+    /// I3C SCL frequency in Hz
+    pub i3c_scl_hz: u32,
+    /// I3C push-pull SCL high period in ns
+    pub i3c_pp_scl_hi_period_ns: u32,
+    /// I3C push-pull SCL low period in ns
+    pub i3c_pp_scl_lo_period_ns: u32,
+    /// I3C open-drain SCL high period in ns
+    pub i3c_od_scl_hi_period_ns: u32,
+    /// I3C open-drain SCL low period in ns
+    pub i3c_od_scl_lo_period_ns: u32,
+    /// SDA TX hold time in ns
+    pub sda_tx_hold_ns: u32,
+    /// Whether this controller is secondary
+    pub is_secondary: bool,
+
+    // Tables/indices
+    /// Maximum number of devices
+    pub maxdevs: u16,
+    /// Bitmap of free DAT positions
+    pub free_pos: u32,
+    /// Bitmap of devices needing dynamic address
+    pub need_da: u32,
+    /// DCR value
+    pub dcr: u32,
+
+    // Target-mode data
+    /// Whether SIR (Slave Interrupt Request) is allowed by software
+    pub sir_allowed_by_sw: bool,
+}
+
+impl Default for I3cConfig {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl I3cConfig {
+    /// Create a new configuration with default values
+    #[must_use]
+    pub fn new() -> Self {
+        Self {
+            common: CommonState::default(),
+            target_config: None,
+            addrbook: AddrBook::new(),
+            attached: Attached::new(),
+            core_clk_hz: None,
+            core_period: 0,
+            i2c_scl_hz: 0,
+            i3c_scl_hz: 0,
+            i3c_pp_scl_hi_period_ns: 0,
+            i3c_pp_scl_lo_period_ns: 0,
+            i3c_od_scl_hi_period_ns: 0,
+            i3c_od_scl_lo_period_ns: 0,
+            sda_tx_hold_ns: 0,
+            is_secondary: false,
+            maxdevs: 8,
+            free_pos: 0,
+            need_da: 0,
+            dcr: 0,
+            sir_allowed_by_sw: false,
+        }
+    }
+
+    /// Initialize runtime fields (address book and attached devices)
+    pub fn init_runtime_fields(&mut self) {
+        self.addrbook = AddrBook::new();
+        self.addrbook.reserve_defaults();
+        self.attached = Attached::new();
+    }
+
+    /// Pick an initial dynamic address for a device
+    ///
+    /// Tries `desired` first, then `static_addr`, then allocates from pool.
+    pub fn pick_initial_da(&mut self, static_addr: u8, desired: u8) -> Option<u8> {
+        if desired != 0 && self.addrbook.is_free(desired) {
+            self.addrbook.mark_use(desired, true);
+            return Some(desired);
+        }
+        if static_addr != 0 && self.addrbook.is_free(static_addr) {
+            self.addrbook.mark_use(static_addr, true);
+            return Some(static_addr);
+        }
+        // Mark the fallback allocation too (`alloc_from` is a pure scan), or
+        // the next caller would be handed the same "initial" address.
+        let addr = self.addrbook.alloc_from(8)?;
+        self.addrbook.mark_use(addr, true);
+        Some(addr)
+    }
+
+    /// Reassign a device's dynamic address
+    pub fn reassign_da(&mut self, from: u8, to: u8) -> Result<(), I3cError> {
+        if from == to {
+            return Ok(());
+        }
+        if !self.addrbook.is_free(to) {
+            return Err(I3cError::AddrInUse);
+        }
+
+        self.addrbook.mark_use(from, false);
+        self.addrbook.mark_use(to, true);
+
+        if let Some((i, mut e)) = self
+            .attached
+            .devices
+            .iter()
+            .enumerate()
+            .find_map(|(i, d)| (d.dyn_addr == from).then_some((i, *d)))
+        {
+            e.dyn_addr = to;
+            self.attached.devices[i] = e;
+            Ok(())
+        } else {
+            Err(I3cError::DevNotFound)
+        }
+    }
+}
+
+// =============================================================================
+// Builder Pattern for I3cConfig
+// =============================================================================
+
+impl I3cConfig {
+    /// Set core clock frequency in Hz
+    ///
+    /// This decouples the I3C driver from SCU/clock tree access.
+    /// The platform layer should provide the actual clock rate.
+    ///
+    /// # I3C Timing Requirements (MIPI I3C Spec v1.1)
+    ///
+    /// | Mode | Min Clock | Typical | Notes |
+    /// |------|-----------|---------|-------|
+    /// | SDR | 12.5 `MHz` | 100-200 `MHz` | For 12.5 `MHz` SCL |
+    /// | HDR | 25 `MHz` | 100-200 `MHz` | For 25 `MHz` SCL |
+    ///
+    /// # Example
+    ///
+    /// ```rust,ignore
+    /// let config = I3cConfig::new()
+    ///     .core_clk_hz(200_000_000)  // 200 MHz from platform
+    ///     .i3c_scl_hz(12_500_000);   // 12.5 MHz SCL
+    /// ```
+    #[must_use]
+    pub fn core_clk_hz(mut self, hz: u32) -> Self {
+        self.core_clk_hz = Some(hz);
+        self
+    }
+
+    /// Set I2C SCL frequency
+    #[must_use]
+    pub fn i2c_scl_hz(mut self, hz: u32) -> Self {
+        self.i2c_scl_hz = hz;
+        self
+    }
+
+    /// Set I3C SCL frequency
+    #[must_use]
+    pub fn i3c_scl_hz(mut self, hz: u32) -> Self {
+        self.i3c_scl_hz = hz;
+        self
+    }
+
+    /// Set as secondary controller
+    #[must_use]
+    pub fn secondary(mut self, is_secondary: bool) -> Self {
+        self.is_secondary = is_secondary;
+        self
+    }
+
+    /// Set DCR (Device Characteristics Register)
+    #[must_use]
+    pub fn dcr(mut self, dcr: u8) -> Self {
+        self.dcr = u32::from(dcr);
+        self
+    }
+
+    /// Set target configuration
+    #[must_use]
+    pub fn target_config(mut self, config: I3cTargetConfig) -> Self {
+        self.target_config = Some(config);
+        self
+    }
+
+    /// Set I3C Push-Pull SCL high period in ns
+    #[must_use]
+    pub fn i3c_pp_scl_hi_period_ns(mut self, ns: u32) -> Self {
+        self.i3c_pp_scl_hi_period_ns = ns;
+        self
+    }
+
+    /// Set I3C Push-Pull SCL low period in ns
+    #[must_use]
+    pub fn i3c_pp_scl_lo_period_ns(mut self, ns: u32) -> Self {
+        self.i3c_pp_scl_lo_period_ns = ns;
+        self
+    }
+
+    /// Set I3C Open-Drain SCL high period in ns
+    #[must_use]
+    pub fn i3c_od_scl_hi_period_ns(mut self, ns: u32) -> Self {
+        self.i3c_od_scl_hi_period_ns = ns;
+        self
+    }
+
+    /// Set I3C Open-Drain SCL low period in ns
+    #[must_use]
+    pub fn i3c_od_scl_lo_period_ns(mut self, ns: u32) -> Self {
+        self.i3c_od_scl_lo_period_ns = ns;
+        self
+    }
+
+    /// Set SDA TX hold time in ns
+    #[must_use]
+    pub fn sda_tx_hold_ns(mut self, ns: u32) -> Self {
+        self.sda_tx_hold_ns = ns;
+        self
+    }
+}
+
+// =============================================================================
+// Clock Validation
+// =============================================================================
+
+/// Minimum core clock for I3C SDR mode (Hz)
+/// Required to achieve 12.5 `MHz` SCL with proper timing margins
+pub const I3C_MIN_CORE_CLK_SDR: u32 = 12_500_000;
+
+/// Minimum core clock for I3C HDR mode (Hz)
+/// Required to achieve 25 `MHz` SCL with proper timing margins
+pub const I3C_MIN_CORE_CLK_HDR: u32 = 25_000_000;
+
+/// Maximum supported core clock (Hz)
+pub const I3C_MAX_CORE_CLK: u32 = 400_000_000;
+
+impl I3cConfig {
+    /// Validate clock configuration
+    ///
+    /// Checks that the configured clock frequencies are achievable per
+    /// MIPI I3C specification timing requirements.
+    ///
+    /// # Timing Requirements (MIPI I3C Basic Spec v1.1.1)
+    ///
+    /// | Parameter | SDR Mode | HDR-DDR Mode | Unit |
+    /// |-----------|----------|--------------|------|
+    /// | fSCL max  | 12.5     | 12.5         | `MHz`  |
+    /// | tLOW min  | 32       | 32           | ns   |
+    /// | tHIGH min | 32       | 32           | ns   |
+    ///
+    /// For reliable operation, core clock should be at least 4x the SCL frequency
+    /// to allow proper timing register resolution.
+    ///
+    /// # Returns
+    ///
+    /// - `Ok(())` if configuration is valid
+    /// - `Err(I3cError::InvalidParam)` if configuration is invalid
+    ///
+    /// # Example
+    ///
+    /// ```rust,ignore
+    /// let config = I3cConfig::new()
+    ///     .core_clk_hz(200_000_000)
+    ///     .i3c_scl_hz(12_500_000);
+    ///
+    /// config.validate_clock()?;
+    /// ```
+    pub fn validate_clock(&self) -> Result<(), I3cError> {
+        if let Some(core_hz) = self.core_clk_hz {
+            // Check core clock range
+            if core_hz < I3C_MIN_CORE_CLK_SDR {
+                return Err(I3cError::InvalidParam);
+            }
+            if core_hz > I3C_MAX_CORE_CLK {
+                return Err(I3cError::InvalidParam);
+            }
+
+            // Check I3C SCL achievability (need ~4x core clock for timing
+            // resolution). `saturating_mul`: an absurd SCL must fail
+            // validation, not overflow-panic inside the validator.
+            if self.i3c_scl_hz > 0 && core_hz < self.i3c_scl_hz.saturating_mul(4) {
+                return Err(I3cError::InvalidParam);
+            }
+
+            // Check I2C SCL achievability
+            if self.i2c_scl_hz > 0 && core_hz < self.i2c_scl_hz.saturating_mul(4) {
+                return Err(I3cError::InvalidParam);
+            }
+        }
+
+        Ok(())
+    }
+}
diff --git a/target/ast10x0/peripherals/i3c/constants.rs b/target/ast10x0/peripherals/i3c/constants.rs
new file mode 100644
index 00000000..354aefa8
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/constants.rs
@@ -0,0 +1,370 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C hardware constants and register definitions
+//!
+//! # Register Map
+//! | Offset | Register              | Description                    |
+//! |--------|-----------------------|--------------------------------|
+//! | 0x0C   | COMMAND_QUEUE_PORT    | Command queue port             |
+//! | 0x10   | RESPONSE_QUEUE_PORT   | Response queue port            |
+//! | 0x18   | IBI_QUEUE_STATUS      | IBI queue status               |
+//! | 0x3C   | INTR_STATUS           | Interrupt status               |
+//! | 0x40   | INTR_STATUS_EN        | Interrupt status enable        |
+//! | 0x44   | INTR_SIGNAL_EN        | Interrupt signal enable        |
+
+// =============================================================================
+// Message Flags
+// =============================================================================
+
+/// I3C message write flag
+pub const I3C_MSG_WRITE: u8 = 0x0;
+/// I3C message read flag
+pub const I3C_MSG_READ: u8 = 0x1;
+/// I3C message stop flag
+pub const I3C_MSG_STOP: u8 = 0x2;
+
+// =============================================================================
+// I2C Timing Constants (nanoseconds)
+// =============================================================================
+
+// Standard mode (100 kHz)
+pub const I3C_BUS_I2C_STD_TLOW_MIN_NS: u32 = 4_700;
+pub const I3C_BUS_I2C_STD_THIGH_MIN_NS: u32 = 4_000;
+pub const I3C_BUS_I2C_STD_TR_MAX_NS: u32 = 1_000;
+pub const I3C_BUS_I2C_STD_TF_MAX_NS: u32 = 300;
+
+// Fast mode (400 kHz)
+pub const I3C_BUS_I2C_FM_TLOW_MIN_NS: u32 = 1_300;
+pub const I3C_BUS_I2C_FM_THIGH_MIN_NS: u32 = 600;
+pub const I3C_BUS_I2C_FM_TR_MAX_NS: u32 = 300;
+pub const I3C_BUS_I2C_FM_TF_MAX_NS: u32 = 300;
+
+// Fast mode plus (1 MHz)
+pub const I3C_BUS_I2C_FMP_TLOW_MIN_NS: u32 = 500;
+pub const I3C_BUS_I2C_FMP_THIGH_MIN_NS: u32 = 260;
+pub const I3C_BUS_I2C_FMP_TR_MAX_NS: u32 = 120;
+pub const I3C_BUS_I2C_FMP_TF_MAX_NS: u32 = 120;
+
+// I3C timing
+pub const I3C_BUS_THIGH_MAX_NS: u32 = 41;
+
+/// Nanoseconds per second
+pub const NSEC_PER_SEC: u32 = 1_000_000_000;
+/// Microseconds per second
+pub const USEC_PER_SEC: u32 = 1_000_000;
+
+// =============================================================================
+// SDA TX Hold Configuration
+// =============================================================================
+
+pub const SDA_TX_HOLD_MIN: u32 = 0b001;
+pub const SDA_TX_HOLD_MAX: u32 = 0b111;
+pub const SDA_TX_HOLD_MASK: u32 = 0x0007_0000; // bits 18:16
+
+// =============================================================================
+// Slave Configuration
+// =============================================================================
+
+pub const SLV_DCR_MASK: u32 = 0x0000_ff00;
+pub const SLV_EVENT_CTRL: u32 = 0x38;
+pub const SLV_EVENT_CTRL_MWL_UPD: u32 = bit(7);
+pub const SLV_EVENT_CTRL_MRL_UPD: u32 = bit(6);
+pub const SLV_EVENT_CTRL_HJ_REQ: u32 = bit(3);
+pub const SLV_EVENT_CTRL_SIR_EN: u32 = bit(0);
+
+// =============================================================================
+// I3C Global Register Bits
+// =============================================================================
+
+pub const I3CG_REG1_SCL_IN_SW_MODE_VAL: u32 = bit(23);
+pub const I3CG_REG1_SDA_IN_SW_MODE_VAL: u32 = bit(27);
+pub const I3CG_REG1_SCL_IN_SW_MODE_EN: u32 = bit(28);
+pub const I3CG_REG1_SDA_IN_SW_MODE_EN: u32 = bit(29);
+
+// =============================================================================
+// Transfer Status
+// =============================================================================
+
+pub const CM_TFR_STS_MASTER_HALT: u8 = 0xf;
+pub const CM_TFR_STS_TARGET_HALT: u8 = 0x6;
+
+// =============================================================================
+// Command Queue Port (0x0C)
+// =============================================================================
+
+pub const COMMAND_QUEUE_PORT: u32 = 0x0c;
+
+// Command port bit flags
+pub const COMMAND_PORT_PEC: u32 = bit(31);
+pub const COMMAND_PORT_TOC: u32 = bit(30);
+pub const COMMAND_PORT_READ_TRANSFER: u32 = bit(28);
+pub const COMMAND_PORT_SDAP: u32 = bit(27);
+pub const COMMAND_PORT_ROC: u32 = bit(26);
+pub const COMMAND_PORT_DBP: u32 = bit(25);
+pub const COMMAND_PORT_CP: u32 = bit(15);
+
+// Command port field masks
+pub const COMMAND_PORT_SPEED: u32 = bits(23, 21);
+pub const COMMAND_PORT_DEV_INDEX: u32 = bits(20, 16);
+pub const COMMAND_PORT_CMD: u32 = bits(14, 7);
+pub const COMMAND_PORT_TID: u32 = bits(6, 3);
+pub const COMMAND_PORT_ARG_DB: u32 = bits(15, 8);
+pub const COMMAND_PORT_ARG_DATA_LEN: u32 = bits(31, 16);
+pub const COMMAND_PORT_ATTR: u32 = bits(2, 0);
+pub const COMMAND_PORT_DEV_COUNT: u32 = bits(25, 21);
+
+// =============================================================================
+// Transaction IDs
+// =============================================================================
+
+pub const TID_TARGET_IBI: u32 = 0x1;
+pub const TID_TARGET_RD_DATA: u32 = 0x2;
+pub const TID_TARGET_MASTER_WR: u32 = 0x8;
+pub const TID_TARGET_MASTER_DEF: u32 = 0xf;
+
+// =============================================================================
+// Command Attributes
+// =============================================================================
+
+pub const COMMAND_ATTR_XFER_CMD: u32 = 0;
+pub const COMMAND_ATTR_XFER_ARG: u32 = 1;
+pub const COMMAND_ATTR_SHORT_ARG: u32 = 2;
+pub const COMMAND_ATTR_ADDR_ASSGN_CMD: u32 = 3;
+pub const COMMAND_ATTR_SLAVE_DATA_CMD: u32 = 0;
+
+// =============================================================================
+// Device Address Table
+// =============================================================================
+
+pub const DEV_ADDR_TABLE_LEGACY_I2C_DEV: u32 = bit(31);
+pub const DEV_ADDR_TABLE_DYNAMIC_ADDR: u32 = bits(23, 16);
+pub const DEV_ADDR_TABLE_MR_REJECT: u32 = bit(14);
+pub const DEV_ADDR_TABLE_SIR_REJECT: u32 = bit(13);
+pub const DEV_ADDR_TABLE_IBI_MDB: u32 = bit(12);
+pub const DEV_ADDR_TABLE_IBI_PEC: u32 = bit(11);
+pub const DEV_ADDR_TABLE_STATIC_ADDR: u32 = bits(6, 0);
+
+// =============================================================================
+// IBI Queue Status (0x18)
+// =============================================================================
+
+pub const IBI_QUEUE_STATUS: u32 = 0x18;
+pub const IBIQ_STATUS_IBI_ID: u32 = bits(15, 8);
+pub const IBIQ_STATUS_IBI_ID_SHIFT: u32 = 8;
+pub const IBIQ_STATUS_IBI_DATA_LEN: u32 = bits(7, 0);
+pub const IBIQ_STATUS_IBI_DATA_LEN_SHIFT: u32 = 0;
+
+// =============================================================================
+// Reset Control
+// =============================================================================
+
+pub const RESET_CTRL_IBI_QUEUE: u32 = bit(5);
+pub const RESET_CTRL_RX_FIFO: u32 = bit(4);
+pub const RESET_CTRL_TX_FIFO: u32 = bit(3);
+pub const RESET_CTRL_RESP_QUEUE: u32 = bit(2);
+pub const RESET_CTRL_CMD_QUEUE: u32 = bit(1);
+pub const RESET_CTRL_SOFT: u32 = bit(0);
+
+pub const RESET_CTRL_ALL: u32 = RESET_CTRL_IBI_QUEUE
+    | RESET_CTRL_RX_FIFO
+    | RESET_CTRL_TX_FIFO
+    | RESET_CTRL_RESP_QUEUE
+    | RESET_CTRL_CMD_QUEUE
+    | RESET_CTRL_SOFT;
+
+pub const RESET_CTRL_QUEUES: u32 = RESET_CTRL_IBI_QUEUE
+    | RESET_CTRL_RX_FIFO
+    | RESET_CTRL_TX_FIFO
+    | RESET_CTRL_RESP_QUEUE
+    | RESET_CTRL_CMD_QUEUE;
+
+pub const RESET_CTRL_XFER_QUEUES: u32 =
+    RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE;
+
+// =============================================================================
+// Response Queue Port (0x10)
+// =============================================================================
+
+pub const RESPONSE_QUEUE_PORT: u32 = 0x10;
+pub const RESPONSE_PORT_ERR_STATUS_SHIFT: u32 = 28;
+pub const RESPONSE_PORT_ERR_STATUS_MASK: u32 = genmask(31, 28);
+pub const RESPONSE_PORT_TID_SHIFT: u32 = 24;
+pub const RESPONSE_PORT_TID_MASK: u32 = genmask(27, 24);
+pub const RESPONSE_PORT_DATA_LEN_SHIFT: u32 = 0;
+pub const RESPONSE_PORT_DATA_LEN_MASK: u32 = genmask(15, 0);
+
+// Response error codes
+pub const RESPONSE_NO_ERROR: u32 = 0;
+pub const RESPONSE_ERROR_CRC: u32 = 1;
+pub const RESPONSE_ERROR_PARITY: u32 = 2;
+pub const RESPONSE_ERROR_FRAME: u32 = 3;
+pub const RESPONSE_ERROR_IBA_NACK: u32 = 4;
+pub const RESPONSE_ERROR_ADDRESS_NACK: u32 = 5;
+pub const RESPONSE_ERROR_OVER_UNDER_FLOW: u32 = 6;
+pub const RESPONSE_ERROR_TRANSF_ABORT: u32 = 8;
+pub const RESPONSE_ERROR_I2C_W_NACK_ERR: u32 = 9;
+pub const RESPONSE_ERROR_EARLY_TERMINATE: u32 = 10;
+pub const RESPONSE_ERROR_PEC_ERR: u32 = 12;
+
+// =============================================================================
+// Interrupt Registers (0x3C - 0x48)
+// =============================================================================
+
+pub const INTR_STATUS: u32 = 0x3c;
+pub const INTR_STATUS_EN: u32 = 0x40;
+pub const INTR_SIGNAL_EN: u32 = 0x44;
+pub const INTR_FORCE: u32 = 0x48;
+
+// Interrupt status bits
+pub const INTR_BUSOWNER_UPDATE_STAT: u32 = bit(13);
+pub const INTR_IBI_UPDATED_STAT: u32 = bit(12);
+pub const INTR_READ_REQ_RECV_STAT: u32 = bit(11);
+pub const INTR_DEFSLV_STAT: u32 = bit(10);
+pub const INTR_TRANSFER_ERR_STAT: u32 = bit(9);
+pub const INTR_DYN_ADDR_ASSGN_STAT: u32 = bit(8);
+pub const INTR_CCC_UPDATED_STAT: u32 = bit(6);
+pub const INTR_TRANSFER_ABORT_STAT: u32 = bit(5);
+pub const INTR_RESP_READY_STAT: u32 = bit(4);
+pub const INTR_CMD_QUEUE_READY_STAT: u32 = bit(3);
+pub const INTR_IBI_THLD_STAT: u32 = bit(2);
+pub const INTR_RX_THLD_STAT: u32 = bit(1);
+pub const INTR_TX_THLD_STAT: u32 = bit(0);
+
+// BCR bits
+pub const I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE: u32 = bit(2);
+
+// =============================================================================
+// Address Constants
+// =============================================================================
+
+/// I3C broadcast address
+pub const I3C_BROADCAST_ADDR: u8 = 0x7E;
+/// Maximum I3C address
+pub const I3C_MAX_ADDR: u8 = 0x7F;
+
+// =============================================================================
+// Hardware Limits
+// =============================================================================
+
+/// Maximum number of commands in a single transfer (hardware command-FIFO
+/// depth).
+pub const MAX_CMDS: usize = 32;
+/// Maximum number of commands in a single *private* transfer.
+///
+/// The command/response transfer-ID field (`COMMAND_PORT_TID` /
+/// `RESPONSE_PORT_TID_MASK`) is 4 bits wide, so only 16 distinct IDs exist.
+/// A batch using the message index as the TID must stay below this bound:
+/// indices >= 16 alias earlier commands once `field_prep` masks the TID,
+/// which mis-routes responses. Necessarily smaller than [`MAX_CMDS`].
+pub const MAX_PRIV_XFER_CMDS: usize = 16;
+/// Maximum data length encodable in a command.
+///
+/// `COMMAND_PORT_ARG_DATA_LEN` is a 16-bit field; a longer length truncates
+/// silently in `field_prep`, so transfers must validate against this bound.
+pub const MAX_XFER_DATA_LEN: usize = 0xffff;
+/// Maximum number of I3C buses supported
+pub const MAX_BUSES: usize = 4;
+/// Maximum devices per bus
+pub const MAX_DEVICES_PER_BUS: usize = 8;
+
+// =============================================================================
+// Driver Policy / Bring-up Defaults
+// =============================================================================
+
+/// Default static address programmed into the controller during init.
+pub const I3C_DEFAULT_STATIC_ADDR: u8 = 0x74;
+/// One-second operation timeout expressed in microseconds.
+pub const I3C_OP_TIMEOUT_US: u32 = USEC_PER_SEC;
+/// Bring-up reset poll delay between iterations in nanoseconds.
+pub const I3C_INIT_POLL_DELAY_NS: u32 = 100_000;
+/// Generic bounded-poll iteration ceiling used by controller bring-up waits.
+pub const I3C_POLL_MAX_ITERS: u32 = 1_000_000;
+/// Queue reset / halt / IBI enable poll delay in nanoseconds.
+pub const I3C_CTRL_POLL_DELAY_NS: u32 = 10_000;
+/// Program the maximum IBI data threshold supported by the controller.
+pub const I3C_IBI_DATA_THRESHOLD_MAX: u8 = 31;
+/// Global I3C reset deassert bit in `SCU054`.
+pub const I3C_GLOBAL_RESET_DEASSERT_MASK: u32 = 0x80;
+/// Write-one-to-clear mask for all interrupt-status bits.
+pub const I3C_INTR_STATUS_ALL_BITS: u32 = u32::MAX;
+/// Bring-up value for `BUS_FREE_TIMING` (`i3cd0d4`).
+pub const I3C_BUS_FREE_TIMING_RESET: u32 = 0xffff_007c;
+/// AST10x0 target MIPI manufacturer identifier.
+pub const I3C_AST10X0_MIPI_MANUF_ID: u16 = 0x03f6;
+
+// =============================================================================
+// CCC (Common Command Code) Constants
+// =============================================================================
+
+pub const I3C_CCC_RSTDAA: u8 = 0x06;
+pub const I3C_CCC_ENTDAA: u8 = 0x07;
+/// SETMWL broadcast form.
+pub const I3C_CCC_SETMWL_BC: u8 = 0x09;
+/// SETMRL broadcast form.
+pub const I3C_CCC_SETMRL_BC: u8 = 0x0A;
+pub const I3C_CCC_SETHID: u8 = 0x61;
+pub const I3C_CCC_DEVCTRL: u8 = 0x62;
+pub const I3C_CCC_SETDASA: u8 = 0x87;
+pub const I3C_CCC_SETNEWDA: u8 = 0x88;
+/// SETMWL direct form.
+pub const I3C_CCC_SETMWL: u8 = 0x89;
+/// SETMRL direct form.
+pub const I3C_CCC_SETMRL: u8 = 0x8A;
+pub const I3C_CCC_GETMWL: u8 = 0x8B;
+pub const I3C_CCC_GETMRL: u8 = 0x8C;
+pub const I3C_CCC_GETPID: u8 = 0x8D;
+pub const I3C_CCC_GETBCR: u8 = 0x8E;
+pub const I3C_CCC_GETDCR: u8 = 0x8F;
+pub const I3C_CCC_GETSTATUS: u8 = 0x90;
+pub const I3C_CCC_GETMXDS: u8 = 0x94;
+
+// CCC event bits
+pub const I3C_CCC_EVT_INTR: u8 = 1 << 0;
+pub const I3C_CCC_EVT_CR: u8 = 1 << 1;
+pub const I3C_CCC_EVT_HJ: u8 = 1 << 3;
+pub const I3C_CCC_EVT_ALL: u8 = I3C_CCC_EVT_INTR | I3C_CCC_EVT_CR | I3C_CCC_EVT_HJ;
+
+// =============================================================================
+// Helper Functions
+// =============================================================================
+
+/// Create a single bit mask at position `n`
+#[inline]
+#[must_use]
+pub const fn bit(n: u32) -> u32 {
+    1 << n
+}
+
+/// Create a bit mask from bit `l` to bit `h` (inclusive)
+#[inline]
+#[must_use]
+pub const fn bits(h: u32, l: u32) -> u32 {
+    ((1u32 << (h - l + 1)) - 1) << l
+}
+
+/// Prepare a value for a masked field
+#[inline]
+#[must_use]
+pub const fn field_prep(mask: u32, val: u32) -> u32 {
+    (val << mask.trailing_zeros()) & mask
+}
+
+/// Extract a value from a masked field
+#[inline]
+#[must_use]
+pub const fn field_get(val: u32, mask: u32, shift: u32) -> u32 {
+    (val & mask) >> shift
+}
+
+/// Generate a mask from MSB to LSB
+#[inline]
+#[must_use]
+pub const fn genmask(msb: u32, lsb: u32) -> u32 {
+    let width = msb - lsb + 1;
+    if width >= 32 {
+        u32::MAX
+    } else {
+        ((1u32 << width) - 1) << lsb
+    }
+}
diff --git a/target/ast10x0/peripherals/i3c/controller.rs b/target/ast10x0/peripherals/i3c/controller.rs
new file mode 100644
index 00000000..4325ad22
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/controller.rs
@@ -0,0 +1,930 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C Controller
+//!
+//! Main hardware abstraction for I3C bus controller.
+//!
+//! # Lifecycle
+//!
+//! Two states, matching the SMC peripheral's `Uninitialized -> Ready`
+//! precedent:
+//!
+//! | State | Entered by | Available operations |
+//! |-------|-----------|----------------------|
+//! | [`Uninitialized`] | [`I3cController::new`] | [`start()`](I3cController::start) |
+//! | [`Ready`] | `start()` (IRQ trampoline claimed + hardware programmed) | bus operations |
+//!
+//! After `start()` the integration layer unmasks the NVIC line it owns (it
+//! selected the bus, so it knows the matching platform interrupt line);
+//! the driver never touches the NVIC.
+//!
+//! # ISR decoupling
+//!
+//! The ISR shares **no** `&mut` state with this controller: at `start()` the
+//! driver parks an ISR-owned register handle plus the role flag in the
+//! per-bus registry (`hardware::register_i3c_irq_handler`), and the ISR
+//! communicates back exclusively through per-bus atomics and the global IBI
+//! work rings (the SMC flag-and-defer model). The controller is therefore a
+//! plain owned value — no pinning, no `'static` storage, no raw context
+//! pointer.
+//!
+//! # Example
+//!
+//! ```rust,ignore
+//! // === BOOT/INIT CODE (runs once) ===
+//! // Platform init first (clocks, resets - not part of i3c_core)
+//! scu.enable_i3c_clock(bus);
+//! scu.deassert_i3c_reset(bus);
+//!
+//! let hw = unsafe { Ast1060I3c::new(bus, yield_fn) }.ok_or(...)?;
+//! let mut ctrl = I3cController::new(hw, &mut config)
+//!     .start()?;            // register ISR ctx (single-shot) + program hardware
+//!
+//! // Integration layer owns the NVIC line; unmask it now.
+//! unsafe { NVIC::unmask(integration_owned_irq_line) };
+//!
+//! ctrl.priv_write(pid, &mut data)?;
+//! ```
+
+use core::marker::PhantomData;
+
+use super::ccc;
+use super::config::{DeviceEntry, I3cConfig, I3cTargetConfig};
+use super::constants::I3C_BROADCAST_ADDR;
+use super::error::I3cError;
+use super::hardware::HardwareInterface;
+use super::types::{DevKind, I2cOp, I3cIbi, I3cIbiType, I3cMsg};
+use embedded_hal::i2c::SevenBitAddress;
+
+// =============================================================================
+// Lifecycle states
+// =============================================================================
+
+/// Initial state: nothing registered, no I/O done.
+pub struct Uninitialized;
+/// IRQ trampoline claimed and hardware programmed; bus operations available.
+/// The integration layer unmasks the NVIC line it owns after entering this
+/// state.
+pub struct Ready;
+
+// =============================================================================
+// Controller shell
+// =============================================================================
+
+/// I3C controller: a plain owned value over the hardware driver, borrowing
+/// the caller's configuration. No pinning or `'static` storage is required —
+/// the ISR never holds a pointer into this object (see the module docs).
+///
+/// The configuration is **borrowed** (`&'c mut I3cConfig`), not owned: the
+/// config embeds the device tables (~0.5 KiB), and the typestate transition
+/// (`start(self) -> Self<Ready>`) moves the controller by value — owning the
+/// config would transiently stack two copies inside one frame, which the
+/// 2 KiB kernel bootstrap stack cannot afford. Borrowing keeps exactly one
+/// config alive, wherever the caller placed it.
+pub struct I3cController<'c, H: HardwareInterface, S = Uninitialized> {
+    hw: H,
+    config: &'c mut I3cConfig,
+    _state: PhantomData<S>,
+}
+
+impl<'c, H: HardwareInterface, S> I3cController<'c, H, S> {
+    /// Split-borrow helper for operations that drive `hw` with `config`.
+    #[inline]
+    fn parts(&mut self) -> (&mut H, &mut I3cConfig) {
+        (&mut self.hw, &mut *self.config)
+    }
+
+    /// Return this controller's bus number.
+    #[inline]
+    #[must_use]
+    pub fn bus_num(&self) -> u8 {
+        self.hw.bus_num()
+    }
+}
+
+impl<'c, H: HardwareInterface> I3cController<'c, H, Uninitialized> {
+    /// Bundle hardware and a borrowed configuration. No I/O, no registration.
+    #[must_use]
+    pub fn new(hw: H, config: &'c mut I3cConfig) -> Self {
+        Self {
+            hw,
+            config,
+            _state: PhantomData,
+        }
+    }
+
+    /// Bring the controller up: park this bus's ISR context in the registry
+    /// (single-shot per bus) and program the hardware.
+    ///
+    /// The target/kernel owns the top-level interrupt vector; its ISR calls
+    /// [`dispatch_i3c_irq`](super::hardware::dispatch_i3c_irq), which services
+    /// the bus through the registered context. On return the device may
+    /// assert its IRQ line; nothing is delivered until the integration layer
+    /// unmasks the NVIC line it owns.
+    ///
+    /// Returns [`I3cError::Busy`] if the bus's IRQ slot was already claimed by
+    /// another controller, or [`I3cError::Timeout`] if the hardware's initial
+    /// queue-reset poll timed out.
+    pub fn start(mut self) -> Result<I3cController<'c, H, Ready>, I3cError> {
+        let bus = self.hw.bus_num() as usize;
+        let ctx = self.hw.isr_ctx(self.config.is_secondary);
+        if !super::hardware::register_i3c_irq_handler(bus, ctx) {
+            return Err(I3cError::Busy);
+        }
+
+        if let Err(e) = self.hw.init(self.config) {
+            // Release the just-claimed slot, or every retry of `start()`
+            // would fail with `Busy` against a controller that never came up.
+            super::hardware::unregister_i3c_irq_handler(bus);
+            return Err(e);
+        }
+        // Memory barrier so init writes are visible before the integration
+        // layer unmasks the IRQ line.
+        cortex_m::asm::dmb();
+
+        Ok(I3cController {
+            hw: self.hw,
+            config: self.config,
+            _state: PhantomData,
+        })
+    }
+}
+
+// =============================================================================
+// Bus operations (Ready)
+// =============================================================================
+
+impl<'c, H: HardwareInterface> I3cController<'c, H, Ready> {
+    // =========================================================================
+    // Device Management
+    // =========================================================================
+
+    /// Attach an I3C device to the bus
+    ///
+    /// # Arguments
+    /// * `pid` - Provisional ID of the device
+    /// * `desired_da` - Desired dynamic address
+    /// * `slot` - DAT slot to use
+    pub fn attach_i3c_dev(&mut self, pid: u64, desired_da: u8, slot: u8) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        if desired_da == 0 || desired_da >= I3C_BROADCAST_ADDR {
+            return Err(I3cError::InvalidArgs);
+        }
+        // Bound the DAT slot: `by_pos` would silently ignore an out-of-range
+        // slot while the register facade aliases positions > 7 onto the last
+        // DAT register, corrupting whatever device lives there.
+        if usize::from(slot) >= super::constants::MAX_DEVICES_PER_BUS {
+            return Err(I3cError::InvalidArgs);
+        }
+        if config
+            .attached
+            .by_pos
+            .get(usize::from(slot))
+            .copied()
+            .flatten()
+            .is_some()
+        {
+            return Err(I3cError::DevAlreadyAttached);
+        }
+
+        let dev = DeviceEntry {
+            kind: DevKind::I3c,
+            pid: Some(pid),
+            static_addr: 0,
+            dyn_addr: desired_da,
+            desired_da,
+            bcr: 0,
+            dcr: 0,
+            maxrd: 0,
+            maxwr: 0,
+            mrl: 0,
+            mwl: 0,
+            max_ibi: 0,
+            ibi_en: false,
+            pos: Some(slot),
+            da_assigned: false,
+        };
+
+        let idx = config
+            .attached
+            .attach(dev)
+            .map_err(|_| I3cError::AddrInUse)?;
+        config
+            .attached
+            .map_pos(slot, u8::try_from(idx).map_err(|_| I3cError::InvalidArgs)?);
+        config.addrbook.mark_use(desired_da, true);
+
+        hw.attach_i3c_dev(slot.into(), desired_da)
+            .map_err(|_| I3cError::AddrInUse)
+    }
+
+    /// Attach a legacy I2C device to the bus.
+    ///
+    /// The DAT slot is programmed with the device's static address and the
+    /// legacy-I2C marker; transfers then go through
+    /// [`i2c_write`](Self::i2c_write)/[`i2c_read`](Self::i2c_read)/
+    /// [`i2c_write_read`](Self::i2c_write_read) or the
+    /// `embedded_hal::i2c::I2c` impl. Detach with
+    /// [`detach_i3c_dev`](Self::detach_i3c_dev) (by slot) or
+    /// [`detach_i3c_dev_by_idx`](Self::detach_i3c_dev_by_idx).
+    pub fn attach_i2c_dev(&mut self, static_addr: u8, slot: u8) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        if static_addr == 0 || static_addr >= I3C_BROADCAST_ADDR {
+            return Err(I3cError::InvalidArgs);
+        }
+        if usize::from(slot) >= super::constants::MAX_DEVICES_PER_BUS {
+            return Err(I3cError::InvalidArgs);
+        }
+        if config
+            .attached
+            .by_pos
+            .get(usize::from(slot))
+            .copied()
+            .flatten()
+            .is_some()
+        {
+            return Err(I3cError::DevAlreadyAttached);
+        }
+
+        let mut dev = DeviceEntry::new_i2c(static_addr);
+        dev.pos = Some(slot);
+        let idx = config
+            .attached
+            .attach(dev)
+            .map_err(|_| I3cError::NoFreeSlot)?;
+        config
+            .attached
+            .map_pos(slot, u8::try_from(idx).map_err(|_| I3cError::InvalidArgs)?);
+        // The static address occupies the same 7-bit space as dynamic ones.
+        config.addrbook.mark_use(static_addr, true);
+
+        hw.attach_i2c_dev(slot.into(), static_addr)
+    }
+
+    /// Write to a legacy I2C device (by static address).
+    pub fn i2c_write(&mut self, static_addr: u8, data: &[u8]) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        let pos = config
+            .attached
+            .pos_of_static_addr(static_addr)
+            .ok_or(I3cError::NoSuchDev)?;
+        let mut ops = [I2cOp::Write(data)];
+        hw.i2c_priv_xfer(config, pos, &mut ops)
+    }
+
+    /// Read from a legacy I2C device (by static address). `out` is filled
+    /// completely on success.
+    pub fn i2c_read(&mut self, static_addr: u8, out: &mut [u8]) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        let pos = config
+            .attached
+            .pos_of_static_addr(static_addr)
+            .ok_or(I3cError::NoSuchDev)?;
+        let mut ops = [I2cOp::Read(out)];
+        hw.i2c_priv_xfer(config, pos, &mut ops)
+    }
+
+    /// Write then read (repeated START between) on a legacy I2C device.
+    pub fn i2c_write_read(
+        &mut self,
+        static_addr: u8,
+        data: &[u8],
+        out: &mut [u8],
+    ) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        let pos = config
+            .attached
+            .pos_of_static_addr(static_addr)
+            .ok_or(I3cError::NoSuchDev)?;
+        let mut ops = [I2cOp::Write(data), I2cOp::Read(out)];
+        hw.i2c_priv_xfer(config, pos, &mut ops)
+    }
+
+    /// Detach an I3C device by DAT position
+    pub fn detach_i3c_dev(&mut self, pos: usize) {
+        let (hw, config) = self.parts();
+        // Release the dynamic address (parity with `detach_i3c_dev_by_idx`),
+        // or detaching by position would leak it in the address book forever.
+        let da = config
+            .attached
+            .by_pos
+            .get(pos)
+            .copied()
+            .flatten()
+            .and_then(|idx| config.attached.devices.get(usize::from(idx)))
+            .map(|dev| dev.dyn_addr);
+        if let Some(da) = da
+            && da != 0
+        {
+            config.addrbook.mark_use(da, false);
+        }
+        config.attached.detach_by_pos(pos);
+        hw.detach_i3c_dev(pos);
+    }
+
+    /// Detach an I3C device by device index
+    pub fn detach_i3c_dev_by_idx(&mut self, dev_idx: usize) {
+        let (hw, config) = self.parts();
+        // `get` (not `[dev_idx]`) keeps this panic-free for the `no_panics`
+        // analysis; an out-of-range index is simply a no-op.
+        let Some(dev) = config.attached.devices.get(dev_idx) else {
+            return;
+        };
+
+        if dev.dyn_addr != 0 {
+            let dyn_addr = dev.dyn_addr;
+            config.addrbook.mark_use(dyn_addr, false);
+        }
+
+        let dev_pos = config.attached.devices.get(dev_idx).and_then(|dev| dev.pos);
+        if let Some(pos) = dev_pos {
+            hw.detach_i3c_dev(pos.into());
+        }
+
+        config.attached.detach(dev_idx);
+    }
+
+    // =========================================================================
+    // Bus Recovery
+    // =========================================================================
+
+    /// Recover the I3C bus from a stuck state
+    ///
+    /// Performs bus recovery sequence:
+    /// 1. Enter software (bit-bang) mode
+    /// 2. Toggle SCL to clear stuck slaves
+    /// 3. Generate STOP condition
+    /// 4. Exit software mode
+    ///
+    /// # Arguments
+    /// * `scl_toggles` - Number of SCL toggles (typically 9 to clear a stuck byte)
+    ///
+    /// # When to Use
+    ///
+    /// - Bus appears hung (transfers timing out)
+    /// - Device not responding after partial transfer
+    /// - After detecting SDA stuck low
+    ///
+    /// # Example
+    ///
+    /// ```rust,ignore
+    /// // Standard recovery with 9 SCL clocks
+    /// ctrl.recover_bus(9);
+    ///
+    /// // More aggressive recovery
+    /// ctrl.recover_bus(18);
+    /// ```
+    pub fn recover_bus(&mut self, scl_toggles: u32) {
+        let (hw, _) = self.parts();
+        hw.enter_sw_mode();
+        hw.i3c_toggle_scl_in(scl_toggles);
+        hw.gen_internal_stop();
+        hw.exit_sw_mode();
+    }
+
+    /// Perform full bus recovery with controller reset
+    ///
+    /// More aggressive recovery that also resets controller FIFOs:
+    /// 1. Bus recovery (SCL toggle + STOP)
+    /// 2. Reset TX/RX FIFOs
+    /// 3. Reset command queue
+    ///
+    /// # Arguments
+    /// * `reset_mask` - Controller components to reset (use `RESET_CTRL_*` constants)
+    ///
+    /// # Example
+    ///
+    /// ```rust,ignore
+    /// use aspeed_rust::i3c_core::{RESET_CTRL_RX_FIFO, RESET_CTRL_TX_FIFO, RESET_CTRL_CMD_QUEUE};
+    ///
+    /// // Full recovery with FIFO reset
+    /// let reset = RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | RESET_CTRL_CMD_QUEUE;
+    /// ctrl.recover_bus_full(reset)?;
+    /// ```
+    ///
+    /// # Errors
+    ///
+    /// [`I3cError::Timeout`] if the controller reset bits did not self-clear —
+    /// the engine is wedged beyond what software recovery can fix.
+    pub fn recover_bus_full(&mut self, reset_mask: u32) -> Result<(), I3cError> {
+        self.recover_bus(8);
+        let (hw, _) = self.parts();
+        hw.reset_ctrl(reset_mask)
+    }
+
+    // =========================================================================
+    // Accessors
+    // =========================================================================
+
+    /// Allocate a dynamic address from `start_addr`.
+    #[inline]
+    pub fn alloc_dynamic_address_from(&mut self, start_addr: u8) -> Option<u8> {
+        let (_, config) = self.parts();
+        config.addrbook.alloc_from(start_addr)
+    }
+
+    /// Return the currently assigned target dynamic address, if any.
+    ///
+    /// The address is assigned by the bus master and latched by the ISR into
+    /// the per-bus event block; the locally configured address (if any) is
+    /// the fallback.
+    #[inline]
+    #[must_use]
+    pub fn target_dynamic_address(&self) -> Option<u8> {
+        super::hardware::isr_events(self.hw.bus_num() as usize)
+            .dyn_addr()
+            .or_else(|| self.config.target_config.as_ref().and_then(|t| t.addr))
+    }
+
+    /// Max read/write lengths `(mrl, mwl)` the bus master pushed to this
+    /// target via SETMRL/SETMWL, if any update was observed (latched by the
+    /// ISR from `SLV_MAX_LEN`). Target mode only.
+    #[inline]
+    #[must_use]
+    pub fn target_max_lengths(&self) -> Option<(u16, u16)> {
+        super::hardware::isr_events(self.hw.bus_num() as usize).max_len()
+    }
+
+    /// Set the device's IBI mandatory data byte and enable IBI delivery for `addr`.
+    pub fn enable_ibi(&mut self, addr: u8, mdb: u8) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        hw.set_ibi_mdb(mdb);
+        hw.ibi_enable(config, addr)
+    }
+
+    /// Disable IBI delivery for `addr` (DISEC + reject its SIRs).
+    pub fn disable_ibi(&mut self, addr: u8) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        hw.ibi_disable(config, addr)
+    }
+
+    /// Re-run the full hardware initialization on a live controller.
+    ///
+    /// Recovery hammer for an engine wedged beyond what
+    /// [`recover_bus_full`](Self::recover_bus_full) can fix (the vendor C
+    /// driver's `target_rst_worker` equivalent). The ISR registration is left
+    /// untouched. Side effects: in target mode the dynamic address is dropped
+    /// (the bus master must re-run DAA) and SIRs are blocked until the next
+    /// DA assignment; in master mode the DAT slots of attached devices are
+    /// re-programmed from the bookkeeping (the bus targets keep their
+    /// addresses — only this controller was reset), but IBIs must be
+    /// re-enabled via [`enable_ibi`](Self::enable_ibi).
+    pub fn reinit(&mut self) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        hw.init(config)?;
+        for i in 0..config.attached.devices.len() {
+            let Some(dev) = config.attached.devices.get(i) else {
+                continue;
+            };
+            if let Some(pos) = dev.pos {
+                let _ = hw.attach_i3c_dev(pos.into(), dev.dyn_addr);
+            }
+        }
+        cortex_m::asm::dmb();
+        Ok(())
+    }
+
+    /// Issue a private read to `pid`, returning the number of received bytes.
+    pub fn priv_read(&mut self, pid: u64, out: &mut [u8]) -> Result<u32, I3cError> {
+        let (hw, config) = self.parts();
+        let actual_len = u32::try_from(out.len()).map_err(|_| I3cError::InvalidArgs)?;
+        let mut msgs = [I3cMsg {
+            buf: Some(out),
+            actual_len,
+            num_xfer: 0,
+            flags: super::constants::I3C_MSG_READ | super::constants::I3C_MSG_STOP,
+            hdr_mode: 0,
+            hdr_cmd_mode: 0,
+        }];
+        hw.priv_xfer(config, pid, &mut msgs)?;
+        Ok(msgs[0].actual_len)
+    }
+
+    /// Issue a private write to `pid`.
+    pub fn priv_write(&mut self, pid: u64, data: &mut [u8]) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        let actual_len = u32::try_from(data.len()).map_err(|_| I3cError::InvalidArgs)?;
+        let mut msgs = [I3cMsg {
+            buf: Some(data),
+            actual_len,
+            num_xfer: 0,
+            flags: super::constants::I3C_MSG_WRITE | super::constants::I3C_MSG_STOP,
+            hdr_mode: 0,
+            hdr_cmd_mode: 0,
+        }];
+        hw.priv_xfer(config, pid, &mut msgs)
+    }
+
+    /// Raise a hot-join request from the target side.
+    pub fn target_raise_hot_join(&mut self) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        hw.target_ibi_raise_hj(config)
+    }
+
+    // =========================================================================
+    // Master / Target operations  (Delta D1)
+    // =========================================================================
+    //
+    // The reference exposed these through `proposed_traits::i3c_master::I3c`
+    // and the `proposed_traits` target traits (`aspeed-rust/src/i3c/hal_impl.rs`).
+    // That crate is unavailable in openprot and embedded-hal 1.0 defines no I3C
+    // trait, so — as the I2C port did for `proposed_traits::i2c_target` — the
+    // logic is preserved verbatim here as **inherent methods**. The only change
+    // is that `ErrorKind`-mapped errors become direct `I3cError` variants
+    // (`DynamicAddressConflict` -> `AddrInUse`, `InvalidCcc` -> `Invalid`).
+
+    /// Assign a dynamic address to the device at `static_address` via ENTDAA,
+    /// then read back PID/BCR and enable IBI. Returns the assigned address.
+    pub fn assign_dynamic_address(
+        &mut self,
+        static_address: SevenBitAddress,
+    ) -> Result<SevenBitAddress, I3cError> {
+        let (hw, config) = self.parts();
+        let slot = config
+            .attached
+            .pos_of_addr(static_address)
+            .ok_or(I3cError::AddrInUse)?;
+
+        hw.do_entdaa(config, slot.into())
+            .map_err(|_| I3cError::AddrInUse)?;
+
+        let pid = ccc::ccc_getpid(hw, config, static_address).map_err(|_| I3cError::Invalid)?;
+
+        let dev_idx = config
+            .attached
+            .find_dev_idx_by_addr(static_address)
+            .ok_or(I3cError::Other)?;
+
+        let old_pid = config
+            .attached
+            .devices
+            .get(dev_idx)
+            .ok_or(I3cError::Other)?
+            .pid;
+
+        if let Some(op) = old_pid
+            && pid != op
+        {
+            return Err(I3cError::Other);
+        }
+
+        let bcr = ccc::ccc_getbcr(hw, config, static_address).map_err(|_| I3cError::Invalid)?;
+        // DCR is informational — a device that NACKs GETDCR still works.
+        let dcr = ccc::ccc_getdcr(hw, config, static_address).unwrap_or(0);
+
+        {
+            let dev = config
+                .attached
+                .devices
+                .get_mut(dev_idx)
+                .ok_or(I3cError::Other)?;
+
+            dev.pid = Some(pid);
+            dev.bcr = bcr;
+            dev.dcr = dcr;
+            dev.da_assigned = true;
+        }
+
+        let dyn_addr: SevenBitAddress = config
+            .attached
+            .devices
+            .get(dev_idx)
+            .ok_or(I3cError::Other)?
+            .dyn_addr;
+
+        hw.ibi_enable(config, dyn_addr)
+            .map_err(|_| I3cError::Other)?;
+
+        Ok(dyn_addr)
+    }
+
+    /// Run dynamic address assignment for every attached I3C device.
+    ///
+    /// Multi-device ENTDAA orchestration ported from the vendor C driver's
+    /// `aspeed_i3c_do_daa`. Walks the DAT slots that still need a verified
+    /// assignment, lets one device win each ENTDAA, reads its PID back and
+    /// corrects the two failure shapes the single-device
+    /// [`assign_dynamic_address`](Self::assign_dynamic_address) cannot:
+    ///
+    /// - **Mis-assignment**: with several unassigned targets on the bus, any
+    ///   of them may answer the ENTDAA issued for another device's slot (bus
+    ///   arbitration picks the winner). The winner is moved to its own
+    ///   expected address via SETNEWDA and the slot is retried for its
+    ///   intended owner.
+    /// - **Unsolicited device**: a target whose PID matches no attached entry
+    ///   is parked on a freshly allocated address so it stops answering
+    ///   subsequent ENTDAAs.
+    ///
+    /// Returns the number of devices verified in this run. Exits when ENTDAA
+    /// reports no more unassigned devices (NACK/timeout). IBIs are not
+    /// enabled here — call [`enable_ibi`](Self::enable_ibi) per device
+    /// afterwards.
+    pub fn bus_daa(&mut self) -> Result<u32, I3cError> {
+        let (hw, config) = self.parts();
+        let ndevs = config.attached.by_pos.len();
+
+        // DAT positions still needing a verified assignment.
+        let mut need: u32 = 0;
+        for idx in 0..config.attached.devices.len() {
+            let Some(dev) = config.attached.devices.get(idx) else {
+                continue;
+            };
+            if dev.kind == DevKind::I3c
+                && dev.pid.is_some()
+                && !dev.da_assigned
+                && let Some(pos) = dev.pos
+            {
+                // pos < 8 enforced by attach_i3c_dev.
+                need |= 1u32 << pos;
+            }
+        }
+
+        let mut verified = 0u32;
+        let mut pos = 0usize;
+        // Hang guard only: every lap either clears a `need` bit, parks an
+        // unsolicited device (finite), or exits via the ENTDAA break below.
+        let mut budget = 8 * (ndevs as u32);
+        while need != 0 && budget != 0 {
+            budget -= 1;
+
+            if need & (1u32 << pos) == 0 {
+                pos = (pos + 1) % ndevs;
+                continue;
+            }
+
+            // The address the ENTDAA winner will latch: the DAT slot was
+            // programmed with its owner's desired address at attach time.
+            let Some(addr) = config
+                .attached
+                .by_pos
+                .get(pos)
+                .copied()
+                .flatten()
+                .and_then(|idx| config.attached.devices.get(usize::from(idx)))
+                .map(|d| d.desired_da)
+            else {
+                // Stale bit with no mapped device — drop it.
+                need &= !(1u32 << pos);
+                pos = (pos + 1) % ndevs;
+                continue;
+            };
+
+            if hw.do_entdaa(config, pos as u32).is_err() {
+                // NACK/timeout: nothing unassigned left on the bus.
+                break;
+            }
+
+            let Ok(pid) = ccc::ccc_getpid(hw, config, addr) else {
+                // Winner could not be identified; retry this slot next lap.
+                pos = (pos + 1) % ndevs;
+                continue;
+            };
+
+            let owner = config
+                .attached
+                .devices
+                .iter()
+                .position(|d| d.pid == Some(pid));
+            match owner {
+                Some(idx) => {
+                    let expected = config
+                        .attached
+                        .devices
+                        .get(idx)
+                        .map_or(addr, |d| d.desired_da);
+                    if expected == addr {
+                        // The intended device answered its own slot.
+                        let bcr = ccc::ccc_getbcr(hw, config, addr).unwrap_or(0);
+                        let dcr = ccc::ccc_getdcr(hw, config, addr).unwrap_or(0);
+                        if let Some(dev) = config.attached.devices.get_mut(idx) {
+                            dev.bcr = bcr;
+                            dev.dcr = dcr;
+                            dev.da_assigned = true;
+                        }
+                        need &= !(1u32 << pos);
+                        verified += 1;
+                    } else if ccc::ccc_setnewda_bus_only(hw, config, addr, expected).is_ok() {
+                        // Wrong device won this slot: it now sits on its own
+                        // expected address (its own DAT slot already holds
+                        // that address), so it is done...
+                        let bcr = ccc::ccc_getbcr(hw, config, expected).unwrap_or(0);
+                        let dcr = ccc::ccc_getdcr(hw, config, expected).unwrap_or(0);
+                        if let Some(dev) = config.attached.devices.get_mut(idx) {
+                            dev.bcr = bcr;
+                            dev.dcr = dcr;
+                            dev.da_assigned = true;
+                        }
+                        if let Some(own_pos) = config
+                            .attached
+                            .pos_of(idx)
+                            .or_else(|| config.attached.devices.get(idx).and_then(|d| d.pos))
+                        {
+                            need &= !(1u32 << u32::from(own_pos));
+                        }
+                        verified += 1;
+                        // ...and this slot's bit stays set so its intended
+                        // owner gets the next ENTDAA here.
+                    }
+                }
+                None => {
+                    // Unknown PID: park it on a fresh address so it stops
+                    // answering ENTDAA for slots it does not own.
+                    let Some(park) = config.addrbook.alloc_from(8) else {
+                        break;
+                    };
+                    config.addrbook.mark_use(park, true);
+                    if ccc::ccc_setnewda_bus_only(hw, config, addr, park).is_err() {
+                        config.addrbook.mark_use(park, false);
+                    }
+                    // Retry this slot without advancing.
+                    continue;
+                }
+            }
+
+            pos = (pos + 1) % ndevs;
+        }
+
+        Ok(verified)
+    }
+
+    /// Acknowledge an IBI from `address` (validates the device is known).
+    pub fn acknowledge_ibi(&mut self, address: SevenBitAddress) -> Result<(), I3cError> {
+        let (_, config) = self.parts();
+        let dev_idx = config
+            .attached
+            .find_dev_idx_by_addr(address)
+            .ok_or(I3cError::Other)?;
+
+        // `get` (not `[dev_idx]`) keeps this panic-free for the `no_panics`
+        // analysis; `find_dev_idx_by_addr` already returns a valid index.
+        let dev = config
+            .attached
+            .devices
+            .get(dev_idx)
+            .ok_or(I3cError::Other)?;
+        if dev.pid.is_none() {
+            return Err(I3cError::Other);
+        }
+
+        Ok(())
+    }
+
+    /// Hot-join handler hook. Call [`assign_dynamic_address`](Self::assign_dynamic_address)
+    /// after receiving a hot-join IBI; nothing else is required here.
+    #[allow(clippy::unused_self)]
+    pub fn handle_hot_join(&mut self) -> Result<(), I3cError> {
+        Ok(())
+    }
+
+    /// Bus speed is fixed on the AST1060 controller; this is a no-op.
+    #[allow(clippy::unused_self)]
+    pub fn set_bus_speed(&mut self) -> Result<(), I3cError> {
+        Ok(())
+    }
+
+    /// The AST1060 controller does not support multi-master; this is a no-op.
+    #[allow(clippy::unused_self)]
+    pub fn request_mastership(&mut self) -> Result<(), I3cError> {
+        Ok(())
+    }
+
+    // --- Target (secondary) mode callbacks ---
+
+    /// Initialize target mode with `own_addr` (sets the static/target address).
+    pub fn target_init(&mut self, own_addr: u8) {
+        let (_, config) = self.parts();
+        if let Some(t) = config.target_config.as_mut() {
+            if t.addr.is_none() {
+                t.addr = Some(own_addr);
+            }
+        } else {
+            config.target_config =
+                Some(I3cTargetConfig::new(0, Some(own_addr), /* mdb */ 0xae));
+        }
+    }
+
+    /// Returns `true` if `addr` matches this target's assigned address.
+    #[must_use]
+    pub fn target_on_address_match(&self, addr: u8) -> bool {
+        self.target_dynamic_address() == Some(addr)
+    }
+
+    /// Record that the controller assigned this target a dynamic address; SIRs
+    /// are then permitted by software. Also syncs the ISR-latched address into
+    /// the thread-owned target config.
+    ///
+    /// **Timing caveat (vendor C driver parity):** the C driver delays this
+    /// permission by one second after the DA assignment (`target_worker`),
+    /// because a controller that has not yet finished ENTDAA/DISEC sequencing
+    /// can be confused by an immediate SIR. This port has no timer, so the
+    /// caller owns that delay — wait ~1 s after the `TargetDaAssignment` work
+    /// item before calling this if the bus master is slow to settle.
+    pub fn target_on_dynamic_address_assigned(&mut self) {
+        let da = super::hardware::isr_events(self.hw.bus_num() as usize).dyn_addr();
+        if let (Some(da), Some(tc)) = (da, self.config.target_config.as_mut()) {
+            tc.addr = Some(da);
+        }
+        self.config.sir_allowed_by_sw = true;
+    }
+
+    /// This target always wants to raise IBIs when it has data.
+    #[must_use]
+    #[allow(clippy::unused_self)]
+    pub fn target_wants_ibi(&self) -> bool {
+        true
+    }
+
+    /// Build and submit the IBI payload `[mdb, crc8_ccitt(addr_rnw, mdb)]` for a
+    /// pending target read, returning the number of bytes made available.
+    pub fn target_get_ibi_payload(&mut self, buffer: &mut [u8]) -> Result<usize, I3cError> {
+        let (hw, config) = self.parts();
+        let (da, mdb) = match config.target_config.as_ref() {
+            Some(t) => (
+                match t.addr {
+                    Some(da) => da,
+                    None => return Ok(0),
+                },
+                t.mdb,
+            ),
+            None => return Ok(0),
+        };
+
+        let addr_rnw = (da << 1) | 0x1;
+        let mut crc = crc8_ccitt(0, &[addr_rnw]);
+        crc = crc8_ccitt(crc, &[mdb]);
+
+        let payload = [mdb, crc];
+        let mut ibi = I3cIbi {
+            ibi_type: I3cIbiType::TargetIntr,
+            payload: Some(&payload),
+        };
+        let rc = hw.target_pending_read_notify(config, buffer, &mut ibi);
+
+        match rc {
+            Ok(()) => Ok(buffer.len() + payload.len()),
+            _ => Ok(0),
+        }
+    }
+}
+
+// =============================================================================
+// embedded-hal I2C bus implementation (legacy I2C devices on the I3C bus)
+// =============================================================================
+
+impl<'c, H: HardwareInterface> embedded_hal::i2c::ErrorType for I3cController<'c, H, Ready> {
+    type Error = I3cError;
+}
+
+impl<'c, H: HardwareInterface> embedded_hal::i2c::I2c for I3cController<'c, H, Ready> {
+    /// Execute an I2C transaction against an attached legacy I2C device.
+    ///
+    /// The device must have been attached with
+    /// [`attach_i2c_dev`](Self::attach_i2c_dev) first (the controller
+    /// addresses devices through DAT slots, not free-form). Consecutive
+    /// operations are joined by repeated START; the last one ends with STOP.
+    fn transaction(
+        &mut self,
+        address: SevenBitAddress,
+        operations: &mut [embedded_hal::i2c::Operation<'_>],
+    ) -> Result<(), I3cError> {
+        let (hw, config) = self.parts();
+        let pos = config
+            .attached
+            .pos_of_static_addr(address)
+            .ok_or(I3cError::NoSuchDev)?;
+
+        if operations.is_empty() {
+            return Ok(());
+        }
+
+        let mut ops: heapless::Vec<I2cOp<'_>, { super::constants::MAX_PRIV_XFER_CMDS }> =
+            heapless::Vec::new();
+        for op in operations.iter_mut() {
+            let mapped = match op {
+                embedded_hal::i2c::Operation::Write(b) => I2cOp::Write(b),
+                embedded_hal::i2c::Operation::Read(b) => I2cOp::Read(core::mem::take(b)),
+            };
+            ops.push(mapped).map_err(|_| I3cError::TooManyMsgs)?;
+        }
+
+        hw.i2c_priv_xfer(config, pos, ops.as_mut_slice())
+    }
+}
+
+/// CRC-8 CCITT calculation (ported from `hal_impl.rs`).
+#[inline]
+fn crc8_ccitt(mut crc: u8, data: &[u8]) -> u8 {
+    for &b in data {
+        let mut x = crc ^ b;
+        for _ in 0..8 {
+            x = if (x & 0x80) != 0 {
+                (x << 1) ^ 0x07
+            } else {
+                x << 1
+            };
+        }
+        crc = x;
+    }
+    crc
+}
diff --git a/target/ast10x0/peripherals/i3c/error.rs b/target/ast10x0/peripherals/i3c/error.rs
new file mode 100644
index 00000000..ae34a3de
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/error.rs
@@ -0,0 +1,117 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C error types
+//!
+//! Consolidated error types for the I3C subsystem.
+//!
+//! Ported from `aspeed-rust/src/i3c/error.rs` @ ce3b567. The
+//! `proposed_traits::i3c_master::Error` impl is dropped (Delta D1): that trait
+//! is unavailable in openprot, and the master operations are exposed as
+//! inherent methods that return `I3cError` directly.
+
+use core::fmt;
+
+/// Primary error type for I3C operations
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+pub enum I3cError {
+    /// No DAT (Device Address Table) position available
+    NoDatPos,
+    /// No messages provided for transfer
+    NoMsgs,
+    /// Too many messages for single transfer
+    TooManyMsgs,
+    /// Invalid arguments provided
+    InvalidArgs,
+    /// Operation timed out
+    Timeout,
+    /// Device not found
+    NoSuchDev,
+    /// Access denied or not permitted
+    Access,
+    /// Generic I/O error
+    IoError,
+    /// Invalid operation or state
+    Invalid,
+    /// Address already in use
+    AddrInUse,
+    /// Address space exhausted
+    AddrExhausted,
+    /// No free slot available
+    NoFreeSlot,
+    /// Device not found in attached list
+    DevNotFound,
+    /// Device already attached
+    DevAlreadyAttached,
+    /// Invalid parameter
+    InvalidParam,
+    /// CCC (Common Command Code) error
+    CccError(CccErrorKind),
+    /// Resource (bus IRQ slot) already claimed by another controller
+    Busy,
+    /// Other unspecified error
+    Other,
+}
+
+impl fmt::Display for I3cError {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        match self {
+            Self::NoDatPos => write!(f, "no DAT position available"),
+            Self::NoMsgs => write!(f, "no messages provided"),
+            Self::TooManyMsgs => write!(f, "too many messages"),
+            Self::InvalidArgs => write!(f, "invalid arguments"),
+            Self::Timeout => write!(f, "operation timed out"),
+            Self::NoSuchDev | Self::DevNotFound => write!(f, "device not found"),
+            Self::Access => write!(f, "access denied"),
+            Self::IoError => write!(f, "I/O error"),
+            Self::Invalid => write!(f, "invalid operation"),
+            Self::AddrInUse => write!(f, "address in use"),
+            Self::AddrExhausted => write!(f, "address space exhausted"),
+            Self::NoFreeSlot => write!(f, "no free slot"),
+            Self::DevAlreadyAttached => write!(f, "device already attached"),
+            Self::InvalidParam => write!(f, "invalid parameter"),
+            Self::CccError(kind) => write!(f, "CCC error: {kind:?}"),
+            Self::Busy => write!(f, "resource busy"),
+            Self::Other => write!(f, "other error"),
+        }
+    }
+}
+
+/// CCC-specific error kinds
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+pub enum CccErrorKind {
+    /// Invalid parameter for CCC
+    InvalidParam,
+    /// Target not found
+    NotFound,
+    /// No free slot for CCC operation
+    NoFreeSlot,
+    /// Invalid CCC response or operation
+    Invalid,
+}
+
+/// Convenience Result type for I3C operations
+pub type Result<T> = core::result::Result<T, I3cError>;
+
+impl From<CccErrorKind> for I3cError {
+    #[inline]
+    fn from(kind: CccErrorKind) -> Self {
+        Self::CccError(kind)
+    }
+}
+
+/// Implement embedded-hal I2C error trait for interoperability
+impl embedded_hal::i2c::Error for I3cError {
+    fn kind(&self) -> embedded_hal::i2c::ErrorKind {
+        match self {
+            Self::Timeout => embedded_hal::i2c::ErrorKind::NoAcknowledge(
+                embedded_hal::i2c::NoAcknowledgeSource::Unknown,
+            ),
+            Self::NoSuchDev | Self::DevNotFound => embedded_hal::i2c::ErrorKind::NoAcknowledge(
+                embedded_hal::i2c::NoAcknowledgeSource::Address,
+            ),
+            Self::IoError | Self::Access => embedded_hal::i2c::ErrorKind::Bus,
+            _ => embedded_hal::i2c::ErrorKind::Other,
+        }
+    }
+}
diff --git a/target/ast10x0/peripherals/i3c/hardware.rs b/target/ast10x0/peripherals/i3c/hardware.rs
new file mode 100644
index 00000000..2d34cd47
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/hardware.rs
@@ -0,0 +1,2135 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C Hardware Interface
+//!
+//! Defines the hardware abstraction traits and IRQ handling infrastructure.
+//!
+//! # Trait Hierarchy
+//!
+//! The hardware interface is split into focused sub-traits:
+//!
+//! ```text
+//! HardwareInterface (supertrait)
+//! ├── HardwareCore      - Init, IRQ, enable/disable
+//! ├── HardwareClock     - Clock configuration
+//! ├── HardwareFifo      - FIFO operations
+//! ├── HardwareTransfer  - Transfers, CCC, device management
+//! ├── HardwareRecovery  - SW mode, bus recovery
+//! └── HardwareTarget    - Target mode operations
+//! ```
+//!
+//! # Platform Initialization
+//!
+//! SCU operations (clock enable, reset control) are **not** part of these traits.
+//! They should be performed by the platform/board layer before creating the
+//! I3C controller.
+
+use core::cell::UnsafeCell;
+use critical_section::Mutex;
+
+use super::ccc::{ccc_events_set, CccPayload};
+use super::config::{I3cConfig, I3C_MIN_CORE_CLK_SDR};
+use super::constants::{
+    bit, field_get, field_prep, CM_TFR_STS_MASTER_HALT, CM_TFR_STS_TARGET_HALT,
+    COMMAND_ATTR_ADDR_ASSGN_CMD, COMMAND_ATTR_SLAVE_DATA_CMD, COMMAND_ATTR_XFER_ARG,
+    COMMAND_ATTR_XFER_CMD, COMMAND_PORT_ARG_DATA_LEN, COMMAND_PORT_ARG_DB, COMMAND_PORT_ATTR,
+    COMMAND_PORT_CMD, COMMAND_PORT_CP, COMMAND_PORT_DBP, COMMAND_PORT_DEV_COUNT,
+    COMMAND_PORT_DEV_INDEX, COMMAND_PORT_READ_TRANSFER, COMMAND_PORT_ROC, COMMAND_PORT_SPEED,
+    COMMAND_PORT_TID, COMMAND_PORT_TOC, DEV_ADDR_TABLE_IBI_MDB, DEV_ADDR_TABLE_IBI_PEC,
+    DEV_ADDR_TABLE_LEGACY_I2C_DEV, DEV_ADDR_TABLE_MR_REJECT, DEV_ADDR_TABLE_STATIC_ADDR,
+    DEV_ADDR_TABLE_SIR_REJECT, I3CG_REG1_SCL_IN_SW_MODE_EN, I3CG_REG1_SCL_IN_SW_MODE_VAL,
+    I3CG_REG1_SDA_IN_SW_MODE_EN, I3CG_REG1_SDA_IN_SW_MODE_VAL, I3C_AST10X0_MIPI_MANUF_ID,
+    I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE, I3C_BUS_FREE_TIMING_RESET, I3C_BUS_I2C_FMP_TF_MAX_NS,
+    I3C_BUS_I2C_FMP_THIGH_MIN_NS, I3C_BUS_I2C_FMP_TLOW_MIN_NS, I3C_BUS_I2C_FMP_TR_MAX_NS,
+    I3C_BUS_I2C_FM_TF_MAX_NS, I3C_BUS_I2C_FM_THIGH_MIN_NS, I3C_BUS_I2C_FM_TLOW_MIN_NS,
+    I3C_BUS_I2C_FM_TR_MAX_NS, I3C_BUS_I2C_STD_TF_MAX_NS, I3C_BUS_I2C_STD_THIGH_MIN_NS,
+    I3C_BUS_I2C_STD_TLOW_MIN_NS, I3C_BUS_I2C_STD_TR_MAX_NS, I3C_BUS_THIGH_MAX_NS, I3C_CCC_DEVCTRL,
+    I3C_CCC_ENTDAA, I3C_CCC_EVT_INTR, I3C_CCC_SETHID, I3C_CTRL_POLL_DELAY_NS,
+    I3C_DEFAULT_STATIC_ADDR, I3C_GLOBAL_RESET_DEASSERT_MASK, I3C_IBI_DATA_THRESHOLD_MAX,
+    I3C_INIT_POLL_DELAY_NS, I3C_INTR_STATUS_ALL_BITS, I3C_MSG_READ, I3C_OP_TIMEOUT_US,
+    I3C_POLL_MAX_ITERS, IBIQ_STATUS_IBI_DATA_LEN, IBIQ_STATUS_IBI_DATA_LEN_SHIFT,
+    SLV_EVENT_CTRL_MRL_UPD, SLV_EVENT_CTRL_MWL_UPD,
+    IBIQ_STATUS_IBI_ID, IBIQ_STATUS_IBI_ID_SHIFT, INTR_CCC_UPDATED_STAT, INTR_DYN_ADDR_ASSGN_STAT,
+    INTR_IBI_THLD_STAT, INTR_RESP_READY_STAT, INTR_TRANSFER_ABORT_STAT, INTR_TRANSFER_ERR_STAT,
+    MAX_CMDS, MAX_PRIV_XFER_CMDS, MAX_XFER_DATA_LEN, NSEC_PER_SEC, RESET_CTRL_ALL,
+    RESET_CTRL_QUEUES, RESET_CTRL_XFER_QUEUES, RESPONSE_ERROR_IBA_NACK,
+    RESPONSE_PORT_DATA_LEN_MASK, RESPONSE_PORT_DATA_LEN_SHIFT, RESPONSE_PORT_ERR_STATUS_MASK,
+    RESPONSE_PORT_ERR_STATUS_SHIFT, RESPONSE_PORT_TID_MASK, RESPONSE_PORT_TID_SHIFT,
+    SDA_TX_HOLD_MASK, SDA_TX_HOLD_MAX, SDA_TX_HOLD_MIN, SLV_DCR_MASK, SLV_EVENT_CTRL_SIR_EN,
+};
+use super::error::I3cError as I3cDrvError;
+use super::error::I3cError;
+use super::ibi as ibi_workq;
+use super::types::{Completion, I2cOp, I3cCmd, I3cIbi, I3cMsg, I3cXfer, SpeedI2c, SpeedI3c, Tid};
+
+use super::registers::I3cRegisters;
+use core::sync::atomic::{AtomicBool, AtomicU32, Ordering};
+
+// =============================================================================
+// IRQ Handler Infrastructure
+// =============================================================================
+//
+// The ISR fabricates NO `&mut` over any thread-owned object. It works only
+// with:
+//   - its own `I3cRegisters` handle (all methods take `&self`), stored in the
+//     per-bus registry below;
+//   - the per-bus `ISR_EVENTS` atomics;
+//   - the global IBI work rings (`ibi.rs`).
+// Master transfer completion is flag-and-defer (the ISR masks the sources and
+// latches the status; the polling thread drains the response queue itself),
+// so there is no ISR/thread `&mut` aliasing and no transfer-pointer handoff.
+
+/// Everything the ISR needs for one bus. Built by
+/// [`Ast1060I3c::isr_ctx`] and parked in the per-bus registry at
+/// [`I3cController::start`](super::controller::I3cController::start).
+pub struct IsrCtx {
+    /// ISR-side register handle. A second `I3cRegisters` for the same bus as
+    /// the driver's own — sound for MMIO (no Rust memory is aliased), and
+    /// device-access serialization holds because the single-core ISR runs
+    /// atomically with respect to the thread.
+    regs: I3cRegisters,
+    /// Role selected at `start()` (the ISR must not read the thread-owned
+    /// config).
+    is_secondary: bool,
+}
+
+// SAFETY: `IsrCtx` holds raw MMIO pointers (valid from any execution context
+// on this single-address-space target) and a bool; parking it in the
+// critical-section-guarded registry below is sound.
+unsafe impl Send for IsrCtx {}
+
+// INTENTIONAL EXCEPTION to borrow-arbitrated exclusivity: this per-bus
+// dispatch table is process-global mutable state, because an ISR cannot
+// borrow a stack-owned controller — the global registry is the structural
+// price of IRQ dispatch (same rationale as `IBI_RINGS` in `ibi.rs`, ADR-3).
+// It is bounded (one slot per bus, claimed once via the single-shot
+// `register_i3c_irq_handler`) and serialized by the critical section.
+//
+// `UnsafeCell` (not `RefCell`): mutual exclusion comes from the critical
+// section, and the access helpers below are leaf functions (no caller code
+// runs while the reference is live), so the `RefCell` runtime borrow flag
+// would only add a reachable panic path that the `no_panics` analysis must
+// reject.
+static BUS_ISR: [Mutex<UnsafeCell<Option<IsrCtx>>>; 4] = [
+    Mutex::new(UnsafeCell::new(None)),
+    Mutex::new(UnsafeCell::new(None)),
+    Mutex::new(UnsafeCell::new(None)),
+    Mutex::new(UnsafeCell::new(None)),
+];
+
+/// Per-bus ISR↔thread signal block: plain atomics, written by the ISR and
+/// consumed by the polling thread. Part of the same intentional global-state
+/// exception as the registry above.
+pub(crate) struct IsrEvents {
+    /// Latched interrupt-status bits deferred to the thread (master
+    /// completion path).
+    pending: AtomicU32,
+    /// Dynamic address assigned by the bus master; bit 8 = valid.
+    dyn_addr: AtomicU32,
+    /// Raw `SLV_MAX_LEN` (MRL in bits 31:16, MWL in bits 15:0) latched by the
+    /// ISR when the bus master updates it via SETMRL/SETMWL.
+    slv_max_len: AtomicU32,
+    /// `slv_max_len` holds a master-written value (not reset state).
+    slv_max_len_valid: AtomicBool,
+    /// A deferred fault: the ISR observed a halted/errored engine and left
+    /// recovery (halt/resume sequencing needs the wait policy) to the thread.
+    fault: AtomicBool,
+    /// Target mode: the SIR (IBI) command completed.
+    pub(crate) target_ibi_done: Completion,
+    /// Target mode: the pending-read data was fetched by the master.
+    pub(crate) target_data_done: Completion,
+}
+
+impl IsrEvents {
+    const fn new() -> Self {
+        Self {
+            pending: AtomicU32::new(0),
+            dyn_addr: AtomicU32::new(0),
+            slv_max_len: AtomicU32::new(0),
+            slv_max_len_valid: AtomicBool::new(false),
+            fault: AtomicBool::new(false),
+            target_ibi_done: Completion::new(),
+            target_data_done: Completion::new(),
+        }
+    }
+
+    /// Atomically take (read-and-clear) the latched status bits.
+    pub(crate) fn take_pending(&self) -> u32 {
+        self.pending.swap(0, Ordering::AcqRel)
+    }
+
+    /// Atomically take (read-and-clear) the deferred-fault flag.
+    pub(crate) fn take_fault(&self) -> bool {
+        self.fault.swap(false, Ordering::AcqRel)
+    }
+
+    /// Dynamic address assigned by the master, if any.
+    pub(crate) fn dyn_addr(&self) -> Option<u8> {
+        let v = self.dyn_addr.load(Ordering::Acquire);
+        if v & 0x100 != 0 {
+            Some((v & 0x7f) as u8)
+        } else {
+            None
+        }
+    }
+
+    /// Max read/write lengths `(mrl, mwl)` the bus master set via
+    /// SETMRL/SETMWL, if any update was observed.
+    pub(crate) fn max_len(&self) -> Option<(u16, u16)> {
+        if !self.slv_max_len_valid.load(Ordering::Acquire) {
+            return None;
+        }
+        let v = self.slv_max_len.load(Ordering::Acquire);
+        Some(((v >> 16) as u16, (v & 0xffff) as u16))
+    }
+}
+
+static ISR_EVENTS: [IsrEvents; 4] = [
+    IsrEvents::new(),
+    IsrEvents::new(),
+    IsrEvents::new(),
+    IsrEvents::new(),
+];
+
+/// Per-bus ISR event block (clamps an out-of-range bus to 0, which a
+/// constructed driver can never pass).
+#[inline]
+pub(crate) fn isr_events(bus: usize) -> &'static IsrEvents {
+    ISR_EVENTS.get(bus).unwrap_or(&ISR_EVENTS[0])
+}
+
+/// Register the ISR context for an I3C bus.
+///
+/// Single-shot per bus: the first registration claims the slot, mirroring the
+/// one-controller-per-physical-bus contract of [`Ast1060I3c::new`]. Returns
+/// `false` (and leaves the existing context in place) if `bus` is out of range
+/// or the slot is already claimed.
+///
+/// Once claimed the slot is normally held for the program's lifetime; the only
+/// release is the bring-up failure path via [`unregister_i3c_irq_handler`], so
+/// a subsequent registration can succeed after a failed `start()`.
+#[must_use]
+pub fn register_i3c_irq_handler(bus: usize, ctx: IsrCtx) -> bool {
+    let Some(slot) = BUS_ISR.get(bus) else {
+        return false;
+    };
+    critical_section::with(|cs| {
+        // SAFETY: the critical section excludes ISR/thread concurrency, and
+        // the `&mut` never escapes this leaf function, so this is the only
+        // live reference to the slot.
+        let parked: &mut Option<IsrCtx> = unsafe { &mut *slot.borrow(cs).get() };
+        if parked.is_some() {
+            return false;
+        }
+        *parked = Some(ctx);
+        true
+    })
+}
+
+/// Release a bus's ISR slot.
+///
+/// Only for the bring-up failure path: `I3cController::start` claims the slot
+/// *before* programming the hardware (the claim is the exclusivity gate), so
+/// if `init` then fails the claim must be released or every retry would see
+/// [`I3cError::Busy`](super::error::I3cError::Busy) forever.
+///
+/// # Caution
+///
+/// This clears the slot by bus alone — it does *not* verify which controller
+/// owns the parked context. Call it only from the failure path of the same
+/// `start()` that claimed the slot; calling it once a controller is live would
+/// drop the in-use ISR context. Kept `pub(crate)` for that reason.
+pub(crate) fn unregister_i3c_irq_handler(bus: usize) {
+    let Some(slot) = BUS_ISR.get(bus) else {
+        return;
+    };
+    critical_section::with(|cs| {
+        // SAFETY: same argument as `register_i3c_irq_handler` — the critical
+        // section excludes ISR/thread concurrency and the `&mut` never
+        // escapes this leaf function.
+        let parked: &mut Option<IsrCtx> = unsafe { &mut *slot.borrow(cs).get() };
+        *parked = None;
+    });
+}
+
+// NVIC ownership (Delta D6): the driver does not touch the NVIC and exposes
+// no interrupt-line mapping. The kernel/integration layer owns the top-level
+// vector *and* the line mask; it selects the bus, so it also knows the line
+// (the platform interrupt line) to unmask after `start()` and to mask on
+// teardown. This keeps the driver above the register facade entirely free of
+// PAC types.
+
+/// Dispatch IRQ for a specific bus.
+///
+/// Called by the actual IRQ entry points (defined in the kernel integration
+/// layer). Runs the service routine inside the critical section: we are
+/// already in interrupt context, so no thread can be blocked by it, and the
+/// section guarantees the registry slot is not concurrently replaced.
+#[inline]
+pub fn dispatch_i3c_irq(bus: usize) {
+    critical_section::with(|cs| {
+        let Some(slot) = BUS_ISR.get(bus) else {
+            return;
+        };
+        // SAFETY: the critical section excludes the writer
+        // (`register_i3c_irq_handler`); the shared reference never escapes
+        // this leaf closure.
+        let parked: &Option<IsrCtx> = unsafe { &*slot.borrow(cs).get() };
+        if let Some(ctx) = parked {
+            isr_service(ctx);
+        }
+    });
+}
+
+// =============================================================================
+// ISR service routines — `&self`/atomics only, no `&mut` anywhere
+// =============================================================================
+
+/// Top-level I3C interrupt service. Touches only the ISR-side register
+/// handle, the per-bus atomics, and the global IBI rings.
+fn isr_service(ctx: &IsrCtx) {
+    let regs = &ctx.regs;
+    let status = regs.read_intr_status();
+    if status == 0 {
+        return;
+    }
+    let bus = regs.bus() as usize;
+    let events = isr_events(bus);
+
+    if ctx.is_secondary {
+        if status & INTR_DYN_ADDR_ASSGN_STAT != 0 {
+            let da = u32::from(regs.dynamic_addr());
+            events.dyn_addr.store(0x100 | da, Ordering::Release);
+            let _ = ibi_workq::i3c_ibi_work_enqueue_target_da_assignment(bus);
+        }
+
+        if (status & INTR_RESP_READY_STAT) != 0 {
+            isr_target_responses(regs, events, bus);
+        }
+
+        if (status & INTR_CCC_UPDATED_STAT) != 0 {
+            // Read-and-clear the event; if the engine halted, defer the
+            // resume sequencing (it needs the wait policy) to the thread.
+            let event = regs.read_slv_event_ctrl();
+            // Latch SETMRL/SETMWL updates before the write-back clears the
+            // update flags (the thread reads them via `max_len`).
+            if event & (SLV_EVENT_CTRL_MRL_UPD | SLV_EVENT_CTRL_MWL_UPD) != 0 {
+                events
+                    .slv_max_len
+                    .store(regs.read_slv_max_len(), Ordering::Release);
+                events.slv_max_len_valid.store(true, Ordering::Release);
+            }
+            regs.write_slv_event_ctrl(event);
+            if regs.xfer_status() == CM_TFR_STS_TARGET_HALT {
+                events.fault.store(true, Ordering::Release);
+            }
+        }
+    } else {
+        if (status & (INTR_RESP_READY_STAT | INTR_TRANSFER_ERR_STAT | INTR_TRANSFER_ABORT_STAT))
+            != 0
+        {
+            // Flag-and-defer (the SMC model): mask the sources so the level
+            // status cannot refire, latch the bits; the polling thread drains
+            // the response queue itself and re-enables the sources.
+            regs.mask_master_xfer_irqs();
+            events.pending.fetch_or(
+                status & (INTR_RESP_READY_STAT | INTR_TRANSFER_ERR_STAT | INTR_TRANSFER_ABORT_STAT),
+                Ordering::AcqRel,
+            );
+        }
+
+        if (status & INTR_IBI_THLD_STAT) != 0 {
+            isr_master_ibis(regs, bus);
+        }
+    }
+
+    regs.clear_intr_status(status);
+}
+
+/// Target mode: service the response queue from the ISR (master writes and
+/// SIR/read completions arrive whether or not a thread is waiting, and the
+/// hardware queues are shallow — this is the IBI plane that cannot defer).
+fn isr_target_responses(regs: &I3cRegisters, events: &IsrEvents, bus: usize) {
+    let nresp = regs.resp_buf_level();
+
+    for _ in 0..nresp {
+        let resp = regs.pop_response();
+
+        let tid = field_get(resp, RESPONSE_PORT_TID_MASK, RESPONSE_PORT_TID_SHIFT) as usize;
+        let rx_len = field_get(
+            resp,
+            RESPONSE_PORT_DATA_LEN_MASK,
+            RESPONSE_PORT_DATA_LEN_SHIFT,
+        ) as usize;
+        let err = field_get(
+            resp,
+            RESPONSE_PORT_ERR_STATUS_MASK,
+            RESPONSE_PORT_ERR_STATUS_SHIFT,
+        );
+
+        if err != 0 {
+            // Recovery needs halt/resume sequencing (wait policy) — defer.
+            // The errored response's data must still be drained here: the
+            // deferred recovery may run much later (next SIR attempt), and
+            // leftover words would misalign every subsequent RX FIFO read.
+            events.fault.store(true, Ordering::Release);
+            if rx_len != 0 {
+                regs.rx_fifo_drain(rx_len);
+            }
+            continue;
+        }
+
+        if rx_len != 0 {
+            // Bounce buffer sized to the work-item payload (NOT 256): this
+            // runs on the kernel handler stack, and together with the
+            // by-value `IbiWork` copies in the enqueue path a larger buffer
+            // HardFaulted the AST1060 ISR stack. Anything beyond the
+            // work-item capacity would be truncated at enqueue anyway; the
+            // drain below keeps the FIFO aligned for the excess.
+            let mut buf = [0u8; ibi_workq::IBI_MWR_DATA_MAX];
+            // Bound `rx_len` (a raw hardware field) to the buffer via `get`:
+            // an oversized length must not panic in handler mode.
+            let n = rx_len.min(buf.len());
+            if let Some(dst) = buf.get_mut(..n) {
+                regs.rx_fifo_read(dst);
+            }
+            // An oversized write leaves words beyond the bounce buffer in the
+            // RX FIFO; pop them so the next response's data stays aligned
+            // (`n` is word-aligned at 256, so the byte count maps 1:1).
+            if rx_len > n {
+                regs.rx_fifo_drain(rx_len - n);
+            }
+            let _ = ibi_workq::i3c_ibi_work_enqueue_target_master_write(
+                bus,
+                buf.get(..n).unwrap_or(&[]),
+            );
+        }
+
+        if tid == Tid::TargetIbi as usize {
+            events.target_ibi_done.complete();
+        }
+
+        if tid == Tid::TargetRdData as usize {
+            events.target_data_done.complete();
+        }
+    }
+}
+
+/// Master mode: drain the IBI status queue into the global work rings.
+///
+/// Porting delta: the reference validated the SIR address against the
+/// attached-device table here; that table is thread-owned, so the check moves
+/// to the consumer (`acknowledge_ibi` already validates before acting).
+fn isr_master_ibis(regs: &I3cRegisters, bus: usize) {
+    let nibis = regs.ibi_status_count();
+    if nibis == 0 {
+        return;
+    }
+
+    for _ in 0..nibis {
+        let reg = regs.ibi_fifo_pop();
+
+        let ibi_id = field_get(reg, IBIQ_STATUS_IBI_ID, IBIQ_STATUS_IBI_ID_SHIFT);
+        let ibi_data_len = field_get(
+            reg,
+            IBIQ_STATUS_IBI_DATA_LEN,
+            IBIQ_STATUS_IBI_DATA_LEN_SHIFT,
+        ) as usize;
+        let ibi_addr = (ibi_id >> 1) & 0x7F;
+        let rnw = (ibi_id & 1) != 0;
+
+        if ibi_addr != 2 && rnw {
+            // SIR
+            let mut ibi_buf: [u8; 2] = [0u8; 2];
+            let take = core::cmp::min(ibi_data_len, ibi_buf.len());
+            if let Some(dst) = ibi_buf.get_mut(..take) {
+                regs.ibi_fifo_read(dst);
+            }
+            // The read above consumed `take` rounded up to a whole queue word;
+            // a payload longer than the bounce buffer leaves further words in
+            // the IBI queue, where they would be misparsed as the next entry's
+            // status word. Pop the remainder to keep the queue aligned.
+            let consumed = take.div_ceil(4) * 4;
+            if ibi_data_len > consumed {
+                regs.ibi_fifo_drain(ibi_data_len - consumed);
+            }
+            let _ = ibi_workq::i3c_ibi_work_enqueue_target_irq(
+                bus,
+                ibi_addr as u8,
+                ibi_buf.get(..take).unwrap_or(&[]),
+            );
+        } else if ibi_addr == 2 && !rnw {
+            // hot-join
+            let _ = ibi_workq::i3c_ibi_work_enqueue_hotjoin(bus);
+        } else {
+            // normal ibi
+            regs.ibi_fifo_drain(ibi_data_len);
+        }
+    }
+}
+
+// =============================================================================
+// Sub-trait: Core Operations
+// =============================================================================
+
+/// Core hardware operations: init, IRQ, enable/disable
+pub trait HardwareCore {
+    /// Initialize the I3C controller hardware.
+    /// `Err(I3cError::Timeout)` if the initial queue-reset poll timed out.
+    fn init(&mut self, config: &mut I3cConfig) -> Result<(), I3cError>;
+
+    /// Get the bus number for this instance
+    fn bus_num(&self) -> u8;
+
+    /// Enable the I3C controller
+    fn i3c_enable(&mut self, config: &I3cConfig);
+
+    /// Disable the I3C controller
+    fn i3c_disable(&mut self, is_secondary: bool);
+
+    /// Set the controller role (primary/secondary)
+    fn set_role(&mut self, is_secondary: bool);
+
+    /// Build the ISR context to park in the per-bus registry
+    /// (see [`register_i3c_irq_handler`]).
+    fn isr_ctx(&self, is_secondary: bool) -> IsrCtx;
+}
+
+// =============================================================================
+// Sub-trait: Clock Configuration
+// =============================================================================
+
+/// Clock and timing configuration
+pub trait HardwareClock {
+    /// Initialize clock timing parameters
+    ///
+    /// Implementations should use `config.core_clk_hz` if set, falling back
+    /// to [`get_clock_rate()`](Self::get_clock_rate) for auto-detection.
+    fn init_clock(&mut self, config: &mut I3cConfig);
+
+    /// Calculate I2C clock dividers for given SCL frequency
+    fn calc_i2c_clk(&mut self, fscl_hz: u32) -> (u32, u32);
+
+    /// Initialize the PID (Provisional ID) for this controller
+    fn init_pid(&mut self, config: &mut I3cConfig);
+}
+
+// =============================================================================
+// Sub-trait: FIFO Operations
+// =============================================================================
+
+/// FIFO read/write operations
+pub trait HardwareFifo {
+    /// Write to TX FIFO
+    fn wr_tx_fifo(&mut self, bytes: &[u8]);
+
+    /// Read `out.len()` bytes from the RX FIFO
+    fn rd_rx_fifo(&mut self, out: &mut [u8]);
+
+    /// Read `out.len()` bytes from the IBI FIFO
+    fn rd_ibi_fifo(&mut self, out: &mut [u8]);
+}
+
+// =============================================================================
+// Sub-trait: Transfer Operations
+// =============================================================================
+
+/// Transfer, CCC, and device management operations
+pub trait HardwareTransfer {
+    /// Set the IBI Mandatory Data Byte
+    fn set_ibi_mdb(&mut self, mdb: u8);
+
+    /// Exit halt state. `Err(I3cError::Timeout)` if the engine did not leave
+    /// the halt state within the poll budget.
+    fn exit_halt(&mut self, config: &mut I3cConfig) -> Result<(), I3cError>;
+
+    /// Enter halt state. `Err(I3cError::Timeout)` if the engine did not reach
+    /// the halt state within the poll budget.
+    fn enter_halt(&mut self, by_sw: bool, config: &mut I3cConfig) -> Result<(), I3cError>;
+
+    /// Reset controller components (FIFOs, queues, etc.).
+    /// `Err(I3cError::Timeout)` if the reset bits did not self-clear within
+    /// the poll budget.
+    fn reset_ctrl(&mut self, reset: u32) -> Result<(), I3cError>;
+
+    /// Enable IBI for a device
+    fn ibi_enable(&mut self, config: &mut I3cConfig, addr: u8) -> Result<(), I3cError>;
+
+    /// Disable IBI for a device (DISEC + reject its SIRs at the controller)
+    fn ibi_disable(&mut self, config: &mut I3cConfig, addr: u8) -> Result<(), I3cError>;
+
+    /// Start a transfer. Overlap is structurally impossible: the transfer is
+    /// thread-owned for its whole life (`&mut` exclusivity), and the ISR only
+    /// latches completion flags — there is no in-flight pointer to clobber.
+    fn start_xfer(&mut self, config: &mut I3cConfig, xfer: &mut I3cXfer);
+
+    /// Wait (bounded, cooperative-yield) for the transfer the ISR flagged,
+    /// then drain the response queue into `xfer` on the thread side.
+    /// Returns `false` on timeout (after halt/reset recovery).
+    fn wait_xfer_complete(
+        &mut self,
+        config: &mut I3cConfig,
+        xfer: &mut I3cXfer,
+        timeout_us: u32,
+    ) -> bool;
+
+    /// Detach a device by DAT position
+    fn detach_i3c_dev(&mut self, pos: usize);
+
+    /// Attach a device to a DAT position
+    fn attach_i3c_dev(&mut self, pos: usize, addr: u8) -> Result<(), I3cError>;
+
+    /// Attach a legacy I2C device to a DAT position (static address,
+    /// `LEGACY_I2C_DEV` marked, SIR/MR rejected).
+    fn attach_i2c_dev(&mut self, pos: usize, static_addr: u8) -> Result<(), I3cError>;
+
+    /// Execute a legacy-I2C transaction against the device at DAT `pos`.
+    ///
+    /// Consecutive operations are joined by repeated START; the last ends
+    /// with STOP. **Consumes each `Read` buffer** (left empty in the slice,
+    /// same contract as [`priv_xfer`](HardwareTransfer::priv_xfer)); the data
+    /// lands in the caller-owned memory the reborrow came from.
+    fn i2c_priv_xfer<'a>(
+        &mut self,
+        config: &mut I3cConfig,
+        pos: u8,
+        ops: &mut [I2cOp<'a>],
+    ) -> Result<(), I3cError>;
+
+    /// Execute a CCC
+    fn do_ccc(&mut self, config: &mut I3cConfig, ccc: &mut CccPayload) -> Result<(), I3cError>;
+
+    /// Execute ENTDAA (Enter Dynamic Address Assignment)
+    fn do_entdaa(&mut self, config: &mut I3cConfig, index: u32) -> Result<(), I3cError>;
+
+    /// Build commands for private transfer.
+    ///
+    /// **Consumes each message's buffer.** On success every `msgs[i].buf` is
+    /// moved into the corresponding command and left `None`; the caller must
+    /// re-fill the descriptor (`buf`) before reusing the same `msgs` slice for
+    /// another transfer. On error no buffer is taken (all-or-nothing): the
+    /// whole `msgs` slice is left untouched. The underlying caller-owned
+    /// memory is never modified — only the descriptor's `Option` is cleared.
+    fn priv_xfer_build_cmds<'a>(
+        &mut self,
+        cmds: &mut [I3cCmd<'a>],
+        msgs: &mut [I3cMsg<'a>],
+        pos: u8,
+    ) -> Result<(), I3cError>;
+
+    /// Execute a private transfer.
+    ///
+    /// **Consumes each message's buffer** (see [`priv_xfer_build_cmds`]): once
+    /// the command build succeeds every `msgs[i].buf` is left `None` and stays
+    /// `None` for the rest of the call, *including the error paths* below
+    /// (timeout / non-zero response status). Only a failure in the build step
+    /// itself leaves the slice untouched (the build is all-or-nothing). The
+    /// buffers are not restored on a transfer error — the TX side downgrades
+    /// the caller's `&mut` to a shared borrow during build and cannot be put
+    /// back — so a caller retrying the same descriptors must re-fill `buf`
+    /// first regardless of how the previous call returned.
+    ///
+    /// [`priv_xfer_build_cmds`]: HardwareTransfer::priv_xfer_build_cmds
+    fn priv_xfer(
+        &mut self,
+        config: &mut I3cConfig,
+        pid: u64,
+        msgs: &mut [I3cMsg],
+    ) -> Result<(), I3cError>;
+}
+
+// =============================================================================
+// Sub-trait: Recovery / Software Mode
+// =============================================================================
+
+/// Software mode and bus recovery operations
+pub trait HardwareRecovery {
+    /// Enter software mode for manual bus control
+    fn enter_sw_mode(&mut self);
+
+    /// Exit software mode
+    fn exit_sw_mode(&mut self);
+
+    /// Toggle SCL line in software mode
+    fn i3c_toggle_scl_in(&mut self, count: u32);
+
+    /// Generate an internal STOP condition
+    fn gen_internal_stop(&mut self);
+
+    /// Calculate even parity for a byte
+    fn even_parity(byte: u8) -> bool;
+}
+
+// =============================================================================
+// Sub-trait: Target Mode Operations
+// =============================================================================
+
+/// Target (secondary) mode operations
+pub trait HardwareTarget {
+    /// Write data to target TX buffer
+    fn target_tx_write(&mut self, buf: &[u8]);
+
+    /// Raise a Hot-Join IBI (target mode)
+    fn target_ibi_raise_hj(&self, config: &mut I3cConfig) -> Result<(), I3cError>;
+
+    /// Notify pending read in target mode
+    fn target_pending_read_notify(
+        &mut self,
+        config: &mut I3cConfig,
+        buf: &[u8],
+        notifier: &mut I3cIbi,
+    ) -> Result<(), I3cError>;
+}
+
+// =============================================================================
+// Supertrait: Full Hardware Interface
+// =============================================================================
+
+/// Complete hardware abstraction for I3C controllers
+///
+/// This is a supertrait combining all sub-traits. Implementors must provide
+/// all operations.
+///
+/// # Sub-traits
+///
+/// - [`HardwareCore`] - Init, IRQ, enable/disable
+/// - [`HardwareClock`] - Clock configuration
+/// - [`HardwareFifo`] - FIFO operations
+/// - [`HardwareTransfer`] - Transfers, CCC, device management
+/// - [`HardwareRecovery`] - SW mode, bus recovery
+/// - [`HardwareTarget`] - Target mode operations
+pub trait HardwareInterface:
+    HardwareCore + HardwareClock + HardwareFifo + HardwareTransfer + HardwareRecovery + HardwareTarget
+{
+}
+
+// Blanket implementation: any type implementing all sub-traits implements HardwareInterface
+impl<T> HardwareInterface for T where
+    T: HardwareCore
+        + HardwareClock
+        + HardwareFifo
+        + HardwareTransfer
+        + HardwareRecovery
+        + HardwareTarget
+{
+}
+/// I3C bus 0 interrupt handler - call this from your ISR
+#[inline]
+pub fn i3c_irq_handler() {
+    dispatch_i3c_irq(0);
+}
+
+/// I3C bus 1 interrupt handler - call this from your ISR
+#[inline]
+pub fn i3c1_irq_handler() {
+    dispatch_i3c_irq(1);
+}
+
+/// I3C bus 2 interrupt handler - call this from your ISR
+#[inline]
+pub fn i3c2_irq_handler() {
+    dispatch_i3c_irq(2);
+}
+
+/// I3C bus 3 interrupt handler - call this from your ISR
+#[inline]
+pub fn i3c3_irq_handler() {
+    dispatch_i3c_irq(3);
+}
+
+// Delta D6: the reference's `#[cfg(feature = "isr-handlers")] #[no_mangle]
+// extern "C" fn i3c{,1,2,3}()` symbol exports are dropped here. openprot is the
+// kernel-integration target: the kernel owns the interrupt vector and calls
+// `dispatch_i3c_irq(bus)` (via the `i3c*_irq_handler` helpers above), which is
+// exactly the case the reference gated those exports OFF for. Carrying a
+// never-enabled `isr-handlers` feature would only risk a symbol clash with the
+// kernel ISR and an `unexpected_cfgs` lint, with no observable difference in
+// the deployed (feature-off) build.
+
+/// Concrete AST1060 I3C hardware implementation: the per-bus
+/// [`I3cRegisters`] façade (Delta D3 — all MMIO `unsafe` confined there)
+/// plus a Cooperative-Yield wait policy (Delta D2).
+///
+/// One driver type manages any of the bus instances — the bus is selected at
+/// **runtime** in [`new`](Self::new), so several controllers (one per bus)
+/// share this single type. `Y` is the caller-injected yield closure invoked
+/// between completion polls (see [`super::types::Completion::wait_for_us`]);
+/// pass `|_| core::hint::spin_loop()` for a bare-metal busy-wait.
+///
+/// Not `Copy`/`Clone`: this value owns the (also non-`Copy`) registers
+/// wrapper, so bus exclusivity follows from ownership.
+pub struct Ast1060I3c<Y: FnMut(u32)> {
+    regs: I3cRegisters,
+    /// Cooperative yield hook invoked between status polls. Argument is the
+    /// suggested wait window in nanoseconds (advisory). Private so external
+    /// code cannot swap the wait policy out from under an active driver.
+    yield_fn: Y,
+}
+
+impl<Y: FnMut(u32)> Ast1060I3c<Y> {
+    /// Create the I3C hardware driver for `bus` (0..=3). Returns `None` if
+    /// `bus` is out of range.
+    ///
+    /// # Safety
+    ///
+    /// Delegates the [`I3cRegisters::new`] contract — the entire MMIO
+    /// `unsafe` perimeter:
+    /// - the AST1060 PAC singleton pointers are valid for the program's
+    ///   lifetime (they are on AST1060 hardware);
+    /// - access to the returned instance is serialized by the caller (the
+    ///   device is `!Sync`); only one `Ast1060I3c` per physical bus may be
+    ///   active at a time.
+    pub unsafe fn new(bus: u8, yield_fn: Y) -> Option<Self> {
+        // SAFETY: forwarded — see this function's contract above.
+        let regs = unsafe { I3cRegisters::new(bus) }?;
+        Some(Self { regs, yield_fn })
+    }
+
+    /// Bus index this driver was constructed for.
+    #[inline]
+    fn bus(&self) -> u8 {
+        self.regs.bus()
+    }
+}
+
+/// Debug logging is dropped in the openprot port (Delta D4): the reference's
+/// `Logger`/`heapless::String` path is removed. This no-op still evaluates the
+/// format arguments (via `format_args!`) so the surrounding `let reg = …`
+/// bindings stay "used", but performs no formatting or I/O. The leading
+/// `$logger` fragment is captured and ignored (never expanded), so the absent
+/// `logger` field is never referenced.
+macro_rules! i3c_debug {
+    ($logger:expr, $($arg:tt)*) => {{
+        let _ = format_args!($($arg)*);
+    }};
+}
+
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum PollError {
+    Timeout,
+}
+
+/// Bounded poll loop (Cooperative-Yield Bounded-Poll Device, Delta D2).
+///
+/// The reference took a `&mut D: DelayNs`; here the wait policy is the
+/// caller-injected, type-erased `yield_fn`, invoked once per non-completing
+/// poll with an advisory wait window (`delay_ns`). Exhausting `max_iters`
+/// returns a typed [`PollError::Timeout`] — never an unbounded spin.
+pub fn poll_with_timeout<F, C>(
+    mut read_reg: F,
+    mut condition: C,
+    yield_fn: &mut dyn FnMut(u32),
+    delay_ns: u32,
+    max_iters: u32,
+) -> Result<u32, PollError>
+where
+    F: FnMut() -> u32,
+    C: FnMut(u32) -> bool,
+{
+    for _ in 0..max_iters {
+        let val = read_reg();
+        if condition(val) {
+            return Ok(val);
+        }
+        yield_fn(delay_ns);
+    }
+    Err(PollError::Timeout)
+}
+
+impl<Y: FnMut(u32)> Ast1060I3c<Y> {
+    fn toggle_scl_in(&mut self, count: u32) {
+        for _ in 0..count {
+            self.regs.i3cg_reg1_clear_bits(I3CG_REG1_SCL_IN_SW_MODE_VAL);
+            self.regs.i3cg_reg1_set_bits(I3CG_REG1_SCL_IN_SW_MODE_VAL);
+        }
+    }
+
+    fn gen_internal_stop(&mut self) {
+        self.regs.i3cg_reg1_clear_bits(I3CG_REG1_SCL_IN_SW_MODE_VAL);
+        self.regs.i3cg_reg1_clear_bits(I3CG_REG1_SDA_IN_SW_MODE_VAL);
+        self.regs.i3cg_reg1_set_bits(I3CG_REG1_SCL_IN_SW_MODE_VAL);
+        self.regs.i3cg_reg1_set_bits(I3CG_REG1_SDA_IN_SW_MODE_VAL);
+    }
+
+    fn enter_sw_mode(&mut self) {
+        i3c_debug!(self.logger, "enter sw mode");
+        let mut reg = self.regs.i3cg_read_reg1();
+        reg |= I3CG_REG1_SCL_IN_SW_MODE_VAL | I3CG_REG1_SDA_IN_SW_MODE_VAL;
+        self.regs.i3cg_reg1_overwrite(reg);
+        reg |= I3CG_REG1_SCL_IN_SW_MODE_EN | I3CG_REG1_SDA_IN_SW_MODE_EN;
+        self.regs.i3cg_reg1_overwrite(reg);
+    }
+
+    fn exit_sw_mode(&mut self) {
+        let mut reg = self.regs.i3cg_read_reg1();
+        reg &= !(I3CG_REG1_SCL_IN_SW_MODE_EN | I3CG_REG1_SDA_IN_SW_MODE_EN);
+        self.regs.i3cg_reg1_overwrite(reg);
+    }
+
+    /// Thread-side response drain — the old ISR `end_xfer`, minus the
+    /// transfer-pointer handoff: the ISR only latched completion (see
+    /// [`isr_service`]), so this runs with the thread's own `&mut xfer` and
+    /// no `unsafe`.
+    fn process_responses(&mut self, config: &mut I3cConfig, xfer: &mut I3cXfer) {
+        let nresp = self.regs.resp_buf_level();
+
+        for _ in 0..nresp {
+            let resp = self.regs.pop_response();
+
+            let tid = field_get(resp, RESPONSE_PORT_TID_MASK, RESPONSE_PORT_TID_SHIFT) as usize;
+            let rx_len = field_get(
+                resp,
+                RESPONSE_PORT_DATA_LEN_MASK,
+                RESPONSE_PORT_DATA_LEN_SHIFT,
+            ) as usize;
+            let err = field_get(
+                resp,
+                RESPONSE_PORT_ERR_STATUS_MASK,
+                RESPONSE_PORT_ERR_STATUS_SHIFT,
+            );
+
+            i3c_debug!(
+                self.logger,
+                "process_responses: tid={}, rx_len={}, err={}",
+                tid,
+                rx_len,
+                err
+            );
+            if tid >= xfer.cmds.len() {
+                if rx_len > 0 {
+                    self.regs.rx_fifo_drain(rx_len);
+                }
+                continue;
+            }
+
+            // `get_mut` (not `[tid]`) keeps the scatter path panic-free for the
+            // `no_panics` analysis; `tid < len` is already guaranteed above.
+            let Some(cmd) = xfer.cmds.get_mut(tid) else {
+                continue;
+            };
+            cmd.rx_len = u32::try_from(rx_len).unwrap_or(0);
+            cmd.ret = i32::try_from(err).unwrap_or(-1);
+
+            if rx_len == 0 {
+                continue;
+            }
+
+            if err == 0 {
+                // `get_mut(..rx_len)` guards a malformed hardware length that
+                // would otherwise panic on `rx_buf[..rx_len]`; on mismatch the
+                // bytes are drained instead.
+                if let Some(dst) = cmd.rx.as_deref_mut().and_then(|b| b.get_mut(..rx_len)) {
+                    self.regs.rx_fifo_read(dst);
+                } else {
+                    self.regs.rx_fifo_drain(rx_len);
+                }
+            } else if rx_len > 0 {
+                self.regs.rx_fifo_drain(rx_len);
+            }
+        }
+
+        let mut ret = 0;
+        for i in 0..nresp {
+            if let Some(c) = xfer.cmds.get(i)
+                && c.ret != 0
+            {
+                ret = c.ret;
+            }
+        }
+
+        if ret != 0 {
+            // Best-effort recovery; the transfer error is already being
+            // reported via `xfer.ret`, so a recovery timeout on top of it has
+            // no separate observable outcome. `RESET_CTRL_XFER_QUEUES` (not
+            // `RESET_CTRL_QUEUES`) follows the vendor C driver
+            // (`aspeed_i3c_end_xfer`): this is the master completion path, and
+            // resetting the IBI queue here would silently drop IBIs that
+            // arrived during the failed transfer.
+            let _ = self.enter_halt(false, config);
+            let _ = self.reset_ctrl(RESET_CTRL_XFER_QUEUES);
+            let _ = self.exit_halt(config);
+        }
+
+        xfer.ret = ret;
+    }
+}
+
+impl<Y: FnMut(u32)> HardwareCore for Ast1060I3c<Y> {
+    fn init(&mut self, config: &mut I3cConfig) -> Result<(), I3cError> {
+        i3c_debug!(self.logger, "i3c init");
+
+        self.regs
+            .global_reset_deassert(I3C_GLOBAL_RESET_DEASSERT_MASK);
+
+        self.regs.i3cg_program_reg1(I3C_DEFAULT_STATIC_ADDR);
+        let reg = self.regs.i3cg_read_reg1();
+        i3c_debug!(self.logger, "i3cg_reg1: {:#x}", reg);
+
+        self.regs.i3cg_write_reg0(0x0);
+        let reg = self.regs.i3cg_read_reg0();
+        i3c_debug!(self.logger, "i3cg_reg0: {:#x}", reg);
+
+        self.regs.core_reset_assert();
+        self.regs.clock_on();
+        self.regs.core_reset_deassert();
+        self.i3c_disable(config.is_secondary);
+
+        i3c_debug!(
+            self.logger,
+            "bus num: {}, is_secondary: {}",
+            self.bus(),
+            config.is_secondary
+        );
+
+        self.regs.assert_all_queue_resets();
+
+        let regs = &self.regs;
+        poll_with_timeout(
+            || regs.read_reset_ctrl(),
+            |val| val == 0,
+            &mut self.yield_fn,
+            I3C_INIT_POLL_DELAY_NS,
+            I3C_POLL_MAX_ITERS,
+        )
+        .map_err(|_| I3cError::Timeout)?;
+
+        self.set_role(config.is_secondary);
+        self.init_clock(config);
+
+        self.regs.clear_intr_status(I3C_INTR_STATUS_ALL_BITS);
+        if config.is_secondary {
+            self.regs.enable_target_irqs();
+        } else {
+            self.regs.enable_master_irqs();
+        }
+
+        config.sir_allowed_by_sw = false;
+
+        self.regs.set_ibi_data_threshold(I3C_IBI_DATA_THRESHOLD_MAX);
+        self.regs.set_rx_buf_threshold(0);
+
+        self.init_pid(config);
+
+        config.maxdevs = self.regs.dat_depth();
+        config.free_pos = if config.maxdevs == 32 {
+            u32::MAX
+        } else {
+            (1u32 << config.maxdevs) - 1
+        };
+        config.need_da = 0;
+
+        for i in 0..(config.maxdevs) {
+            self.regs.dat_set_reject(i.into());
+        }
+
+        self.regs.write_mr_reject(I3C_INTR_STATUS_ALL_BITS);
+        self.regs.write_sir_reject(I3C_INTR_STATUS_ALL_BITS);
+        self.regs.set_hot_join_nack(true);
+
+        if config.is_secondary {
+            self.regs.program_secondary_static_addr(9);
+        } else {
+            self.regs.program_primary_dynamic_addr(8);
+        }
+
+        self.i3c_enable(config);
+
+        i3c_debug!(self.logger, "i3c enabled");
+        if !config.is_secondary {
+            self.regs.enable_ibi_thld_irq();
+        }
+        self.regs.set_hot_join_nack(false);
+        i3c_debug!(self.logger, "i3c init done");
+
+        // Safety: Ensure memory barrier and init completion before interrupts are enabled by the caller
+        core::sync::atomic::compiler_fence(Ordering::SeqCst);
+        Ok(())
+    }
+
+    fn bus_num(&self) -> u8 {
+        self.bus()
+    }
+
+    fn i3c_disable(&mut self, is_secondary: bool) {
+        i3c_debug!(self.logger, "i3c disable");
+        if !self.regs.controller_enabled() {
+            return;
+        }
+
+        if is_secondary {
+            self.enter_sw_mode();
+        }
+        self.regs.disable_controller();
+
+        if is_secondary {
+            self.toggle_scl_in(8);
+            self.gen_internal_stop();
+            self.exit_sw_mode();
+        }
+    }
+
+    fn i3c_enable(&mut self, config: &I3cConfig) {
+        i3c_debug!(self.logger, "i3c enable");
+        if config.is_secondary {
+            i3c_debug!(self.logger, "i3c enable as secondary");
+            self.regs.write_slv_event_ctrl(0);
+            self.enter_sw_mode();
+            self.regs.enable_controller_secondary();
+            let wait_cnt = self.regs.ibi_free_cycles();
+            let wait_ns = wait_cnt * config.core_period;
+            (self.yield_fn)(wait_ns * 100_u32);
+            self.toggle_scl_in(8);
+            if self.regs.controller_enabled() {
+                self.gen_internal_stop();
+            }
+            self.exit_sw_mode();
+        } else {
+            self.regs.enable_controller_primary();
+        }
+    }
+
+    fn set_role(&mut self, is_secondary: bool) {
+        self.regs.set_dev_op_mode(u8::from(is_secondary));
+    }
+
+    fn isr_ctx(&self, is_secondary: bool) -> IsrCtx {
+        // SAFETY: the ISR runs atomically with respect to the thread on this
+        // single-core target, so device access through the alias stays
+        // serialized (see `I3cRegisters::isr_alias`).
+        let regs = unsafe { self.regs.isr_alias() };
+        IsrCtx { regs, is_secondary }
+    }
+}
+
+impl<Y: FnMut(u32)> HardwareClock for Ast1060I3c<Y> {
+    fn init_clock(&mut self, config: &mut I3cConfig) {
+        // `unwrap_or` + `.max(1)` (not `.expect()` / raw divides) keep this
+        // panic-free for the `no_panics` analysis: a missing/zero core clock
+        // cannot trigger an `expect` panic or a divide-by-zero. For a valid
+        // config the values are unchanged. `period` is a local clamped `>= 1`
+        // so the compiler proves every `div_ceil(period)` divisor non-zero.
+        let clk_rate = config.core_clk_hz.unwrap_or(I3C_MIN_CORE_CLK_SDR).max(1);
+        i3c_debug!(self.logger, "i3c clock rate: {} Hz", clk_rate);
+        config.core_period = (NSEC_PER_SEC).div_ceil(clk_rate);
+        let period = config.core_period.max(1);
+
+        let ns_to_cnt_u8 = |ns: u32| -> u8 { u8::try_from(ns.div_ceil(period)).unwrap_or(u8::MAX) };
+        let ns_to_cnt_u16 =
+            |ns: u32| -> u16 { u16::try_from(ns.div_ceil(period)).unwrap_or(u16::MAX) };
+
+        // I2C FM
+        let (fm_hi_ns, fm_lo_ns) = self.calc_i2c_clk(config.i2c_scl_hz);
+        self.regs
+            .set_i2c_fm_timing(ns_to_cnt_u16(fm_hi_ns), ns_to_cnt_u16(fm_lo_ns));
+
+        // I2C FMP
+        let (i2c_fmp_hi_ns, i2c_fmp_lo_ns) = self.calc_i2c_clk(1_000_000);
+        self.regs
+            .set_i2c_fmp_timing(ns_to_cnt_u8(i2c_fmp_hi_ns), ns_to_cnt_u16(i2c_fmp_lo_ns));
+
+        // I3C OD
+        let (od_hi_ns, od_lo_ns) =
+            if config.i3c_od_scl_hi_period_ns != 0 && config.i3c_od_scl_lo_period_ns != 0 {
+                (
+                    config.i3c_od_scl_hi_period_ns,
+                    config.i3c_od_scl_lo_period_ns,
+                )
+            } else {
+                (i2c_fmp_hi_ns, i2c_fmp_lo_ns)
+            };
+        self.regs
+            .set_od_timing(ns_to_cnt_u8(od_hi_ns), ns_to_cnt_u8(od_lo_ns));
+
+        // I3C PP
+        let (i3c_pp_hi_ns, i3c_pp_lo_ns) =
+            if config.i3c_pp_scl_hi_period_ns != 0 && config.i3c_pp_scl_lo_period_ns != 0 {
+                (
+                    config.i3c_pp_scl_hi_period_ns,
+                    config.i3c_pp_scl_lo_period_ns,
+                )
+            } else {
+                let total_ns = NSEC_PER_SEC.div_ceil(config.i3c_scl_hz.max(1));
+                let hi_ns = core::cmp::min(I3C_BUS_THIGH_MAX_NS, total_ns.saturating_sub(1));
+                let lo_ns = total_ns.saturating_sub(hi_ns).max(1);
+                (hi_ns, lo_ns)
+            };
+        self.regs
+            .set_pp_timing(ns_to_cnt_u8(i3c_pp_hi_ns), ns_to_cnt_u8(i3c_pp_lo_ns));
+
+        // SDA TX hold time (`period` is the clamped, provably-non-zero divisor)
+        let hold_steps = (config.sda_tx_hold_ns)
+            .div_ceil(period)
+            .clamp(SDA_TX_HOLD_MIN, SDA_TX_HOLD_MAX);
+        let mut reg = self.regs.read_sda_hold();
+        reg = (reg & !SDA_TX_HOLD_MASK) | ((hold_steps & 0x7) << 16);
+        self.regs.write_sda_hold(reg);
+
+        // BUS_FREE_TIMING
+        self.regs.write_bus_free_timing(I3C_BUS_FREE_TIMING_RESET);
+    }
+
+    fn calc_i2c_clk(&mut self, fscl_hz: u32) -> (u32, u32) {
+        use core::cmp::max;
+
+        // `.max(1)` on both the SCL frequency and the resulting period keeps the
+        // downstream `div_ceil(period_ns)` divisors provably non-zero (panic-free
+        // for the `no_panics` analysis); a valid `fscl_hz` is unaffected.
+        let period_ns: u32 = (1_000_000_000u32).div_ceil(fscl_hz.max(1)).max(1);
+
+        let (lo_min, hi_min): (u32, u32) = if fscl_hz <= 100_000 {
+            (
+                (I3C_BUS_I2C_STD_TLOW_MIN_NS + I3C_BUS_I2C_STD_TF_MAX_NS).div_ceil(period_ns),
+                (I3C_BUS_I2C_STD_THIGH_MIN_NS + I3C_BUS_I2C_STD_TR_MAX_NS).div_ceil(period_ns),
+            )
+        } else if fscl_hz <= 400_000 {
+            (
+                (I3C_BUS_I2C_FM_TLOW_MIN_NS + I3C_BUS_I2C_FM_TF_MAX_NS).div_ceil(period_ns),
+                (I3C_BUS_I2C_FM_THIGH_MIN_NS + I3C_BUS_I2C_FM_TR_MAX_NS).div_ceil(period_ns),
+            )
+        } else {
+            (
+                (I3C_BUS_I2C_FMP_TLOW_MIN_NS + I3C_BUS_I2C_FMP_TF_MAX_NS).div_ceil(period_ns),
+                (I3C_BUS_I2C_FMP_THIGH_MIN_NS + I3C_BUS_I2C_FMP_TR_MAX_NS).div_ceil(period_ns),
+            )
+        };
+
+        let leftover = period_ns.saturating_sub(lo_min + hi_min);
+        let lo = lo_min + leftover / 2;
+        let hi = max(period_ns.saturating_sub(lo), hi_min);
+
+        (hi, lo)
+    }
+
+    fn init_pid(&mut self, config: &mut I3cConfig) {
+        let bus = self.bus();
+        self.regs.set_pid_mfg_id(I3C_AST10X0_MIPI_MANUF_ID);
+
+        let rev_id: u32 = self.regs.hw_rev_id();
+        let mut reg: u32 = rev_id << 16 | u32::from(bus) << 12;
+        reg |= 0xa000_0000;
+        self.regs.write_slv_pid_value(reg);
+        let mut reg: u32 = self.regs.read_slv_char_ctrl();
+        reg &= !SLV_DCR_MASK;
+        reg |= (config.dcr << 8) | 0x66;
+        self.regs.write_slv_char_ctrl(reg);
+    }
+}
+
+impl<Y: FnMut(u32)> HardwareFifo for Ast1060I3c<Y> {
+    fn wr_tx_fifo(&mut self, bytes: &[u8]) {
+        self.regs.tx_fifo_write(bytes);
+    }
+
+    fn rd_rx_fifo(&mut self, out: &mut [u8]) {
+        self.regs.rx_fifo_read(out);
+    }
+
+    fn rd_ibi_fifo(&mut self, out: &mut [u8]) {
+        self.regs.ibi_fifo_read(out);
+    }
+}
+
+impl<Y: FnMut(u32)> HardwareRecovery for Ast1060I3c<Y> {
+    fn enter_sw_mode(&mut self) {
+        self.enter_sw_mode();
+    }
+
+    fn exit_sw_mode(&mut self) {
+        self.exit_sw_mode();
+    }
+
+    fn i3c_toggle_scl_in(&mut self, count: u32) {
+        self.toggle_scl_in(count);
+    }
+
+    fn gen_internal_stop(&mut self) {
+        self.gen_internal_stop();
+    }
+
+    fn even_parity(byte: u8) -> bool {
+        let mut parity = false;
+        let mut b = byte;
+
+        while b != 0 {
+            parity = !parity;
+            b &= b - 1;
+        }
+
+        !parity
+    }
+}
+
+impl<Y: FnMut(u32)> HardwareTransfer for Ast1060I3c<Y> {
+    fn set_ibi_mdb(&mut self, mdb: u8) {
+        self.regs.set_ibi_mdb(mdb);
+    }
+
+    fn exit_halt(&mut self, config: &mut I3cConfig) -> Result<(), I3cError> {
+        let state = self.regs.xfer_status();
+        let expected = if config.is_secondary {
+            CM_TFR_STS_TARGET_HALT
+        } else {
+            CM_TFR_STS_MASTER_HALT
+        };
+
+        if state != expected {
+            return Ok(());
+        }
+
+        self.regs.resume();
+
+        let regs = &self.regs;
+        let rc = poll_with_timeout(
+            || u32::from(regs.xfer_status()),
+            |val| val != u32::from(expected),
+            &mut self.yield_fn,
+            I3C_CTRL_POLL_DELAY_NS,
+            I3C_POLL_MAX_ITERS,
+        );
+
+        if rc.is_err() {
+            i3c_debug!(self.logger, "exit_halt: timeout");
+            return Err(I3cError::Timeout);
+        }
+        Ok(())
+    }
+
+    fn enter_halt(&mut self, by_sw: bool, config: &mut I3cConfig) -> Result<(), I3cError> {
+        let expected = if config.is_secondary {
+            CM_TFR_STS_TARGET_HALT
+        } else {
+            CM_TFR_STS_MASTER_HALT
+        };
+
+        if by_sw {
+            self.regs.abort();
+        }
+
+        let regs = &self.regs;
+        let rc = poll_with_timeout(
+            || u32::from(regs.xfer_status()),
+            |val| val == u32::from(expected),
+            &mut self.yield_fn,
+            I3C_CTRL_POLL_DELAY_NS,
+            I3C_POLL_MAX_ITERS,
+        );
+
+        if rc.is_err() {
+            i3c_debug!(self.logger, "enter_halt: timeout");
+            return Err(I3cError::Timeout);
+        }
+        Ok(())
+    }
+
+    fn reset_ctrl(&mut self, reset: u32) -> Result<(), I3cError> {
+        let reg = reset & RESET_CTRL_ALL;
+
+        if reg == 0 {
+            return Ok(());
+        }
+
+        self.regs.write_reset_ctrl(reg);
+        let regs = &self.regs;
+        let rc = poll_with_timeout(
+            || regs.read_reset_ctrl(),
+            |val| val == 0,
+            &mut self.yield_fn,
+            I3C_CTRL_POLL_DELAY_NS,
+            I3C_POLL_MAX_ITERS,
+        );
+
+        if rc.is_err() {
+            i3c_debug!(self.logger, "reset_ctrl: timeout");
+            return Err(I3cError::Timeout);
+        }
+        Ok(())
+    }
+
+    fn ibi_enable(&mut self, config: &mut I3cConfig, addr: u8) -> Result<(), I3cDrvError> {
+        let dev_idx = config
+            .attached
+            .find_dev_idx_by_addr(addr)
+            .ok_or(I3cDrvError::NoSuchDev)?;
+        i3c_debug!(self.logger, "ibi_enable: dev_idx={}", dev_idx);
+        // `get(dev_idx)` (not `[dev_idx]`) keeps this path panic-free for the
+        // `no_panics` analysis; `find_dev_idx_by_addr` already returns a valid
+        // index.
+        let pos_opt = config
+            .attached
+            .pos_of(dev_idx)
+            .or_else(|| config.attached.devices.get(dev_idx).and_then(|d| d.pos));
+
+        let pos: u8 = pos_opt.ok_or(I3cDrvError::NoDatPos)?;
+        i3c_debug!(self.logger, "ibi_enable: pos={}", pos);
+        let dev = config
+            .attached
+            .devices
+            .get(dev_idx)
+            .ok_or(I3cDrvError::NoSuchDev)?;
+        let tgt_bcr: u32 = u32::from(dev.bcr);
+        let mut reg = self.regs.dat_read(pos.into());
+        reg &= !DEV_ADDR_TABLE_SIR_REJECT;
+        if tgt_bcr & I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE != 0 {
+            reg |= DEV_ADDR_TABLE_IBI_MDB | DEV_ADDR_TABLE_IBI_PEC;
+        }
+
+        self.regs.dat_write_raw(pos.into(), reg);
+
+        let mut sir_reject = self.regs.read_sir_reject();
+        sir_reject &= !bit(pos.into());
+        self.regs.write_sir_reject(sir_reject);
+
+        self.regs.enable_ibi_thld_irq();
+
+        let events = I3C_CCC_EVT_INTR;
+        // ccc_events_set requires HardwareTransfer trait bound on Self.
+        // We are inside HardwareTransfer impl for Ast1060I3c.
+        // Rust might have trouble inferring if Self: HardwareTransfer is not fully established yet?
+        // But Ast1060I3c implements HardwareTransfer (this block).
+        // However, ccc_events_set takes `&mut impl HardwareInterface`.
+        // Ast1060I3c implements HardwareInterface (blanket impl over all sub-traits).
+        // So this call should be valid.
+        let _ = ccc_events_set(self, config, dev.dyn_addr, true, events);
+
+        i3c_debug!(self.logger, "i3cd030 (SIR reject) = {:#x}", sir_reject);
+        i3c_debug!(
+            self.logger,
+            "i3cd040 (IBI thld) = {:#x}",
+            self.regs.read_intr_status_en()
+        );
+        i3c_debug!(
+            self.logger,
+            "i3cd044 (IBI thld sig) = {:#x}",
+            self.regs.read_intr_signal_en()
+        );
+        i3c_debug!(
+            self.logger,
+            "i3cd280 dat_addr[{}] = {:#x}",
+            pos,
+            self.regs.dat_read(pos.into())
+        );
+        i3c_debug!(self.logger, "ibi_enable done");
+        Ok(())
+    }
+
+    fn ibi_disable(&mut self, config: &mut I3cConfig, addr: u8) -> Result<(), I3cDrvError> {
+        let dev_idx = config
+            .attached
+            .find_dev_idx_by_addr(addr)
+            .ok_or(I3cDrvError::NoSuchDev)?;
+        let pos_opt = config
+            .attached
+            .pos_of(dev_idx)
+            .or_else(|| config.attached.devices.get(dev_idx).and_then(|d| d.pos));
+        let pos: u8 = pos_opt.ok_or(I3cDrvError::NoDatPos)?;
+        let dyn_addr = config
+            .attached
+            .devices
+            .get(dev_idx)
+            .ok_or(I3cDrvError::NoSuchDev)?
+            .dyn_addr;
+
+        // Tell the device to stop raising SIRs first (DISEC), while the
+        // controller still ACKs its IBIs; best-effort, mirroring ibi_enable.
+        let _ = ccc_events_set(self, config, dyn_addr, false, I3C_CCC_EVT_INTR);
+
+        // Then reject at the controller: DAT slot + SIR-reject mask.
+        let mut reg = self.regs.dat_read(pos.into());
+        reg |= DEV_ADDR_TABLE_SIR_REJECT;
+        reg &= !(DEV_ADDR_TABLE_IBI_MDB | DEV_ADDR_TABLE_IBI_PEC);
+        self.regs.dat_write_raw(pos.into(), reg);
+
+        let mut sir_reject = self.regs.read_sir_reject();
+        sir_reject |= bit(pos.into());
+        self.regs.write_sir_reject(sir_reject);
+
+        Ok(())
+    }
+
+    fn start_xfer(&mut self, config: &mut I3cConfig, xfer: &mut I3cXfer) {
+        let _ = config;
+        xfer.ret = -1;
+
+        // Clear any stale completion flag and drain any stale responses left
+        // by an earlier timed-out transfer (the old ISR-side null-pointer
+        // drain, now done on the thread before the next submission).
+        let _ = isr_events(self.bus() as usize).take_pending();
+        let nresp = self.regs.resp_buf_level();
+        for _ in 0..nresp {
+            let _ = self.regs.pop_response();
+        }
+        // Re-arm the completion IRQ sources. If a late response (e.g. from a
+        // transfer that timed out) arrived with no waiter, the ISR masked the
+        // sources and nobody unmasked them — without this, the new transfer's
+        // completion would never be latched and would falsely time out.
+        self.regs.unmask_master_xfer_irqs();
+
+        for cmd in xfer.cmds.iter() {
+            if let Some(tx) = cmd.tx {
+                let take = tx.len().min(cmd.tx_len as usize);
+                if take > 0 {
+                    i3c_debug!(self.logger, "start_xfer: write {} bytes", take);
+                    self.wr_tx_fifo(&tx[..take]);
+                }
+            }
+        }
+        self.regs
+            .set_resp_buf_threshold(u8::try_from(xfer.cmds.len().saturating_sub(1)).unwrap_or(0));
+
+        for cmd in xfer.cmds.iter() {
+            i3c_debug!(
+                self.logger,
+                "start_xfer: cmd: cmd_hi={:#x}, cmd_lo={:#x}",
+                cmd.cmd_hi,
+                cmd.cmd_lo
+            );
+            self.regs.push_cmd(cmd.cmd_hi);
+            self.regs.push_cmd(cmd.cmd_lo);
+        }
+    }
+
+    fn wait_xfer_complete(
+        &mut self,
+        config: &mut I3cConfig,
+        xfer: &mut I3cXfer,
+        timeout_us: u32,
+    ) -> bool {
+        let events = isr_events(self.bus() as usize);
+
+        // Cooperative-yield bounded poll (Delta D2) on the ISR's latched
+        // status; the ISR masked the sources, so on a hit this thread owns
+        // the response queue and drains it into its own `xfer` — no `&mut`
+        // ever crosses the ISR boundary.
+        let mut left = timeout_us;
+        loop {
+            let pending = events.take_pending();
+            if pending & (INTR_RESP_READY_STAT | INTR_TRANSFER_ERR_STAT | INTR_TRANSFER_ABORT_STAT)
+                != 0
+            {
+                self.process_responses(config, xfer);
+                self.regs.unmask_master_xfer_irqs();
+                return true;
+            }
+            if left == 0 {
+                break;
+            }
+            (self.yield_fn)(1_000);
+            left -= 1;
+        }
+
+        // Timeout: recover the engine and re-arm the IRQ sources. Recovery is
+        // best-effort — the `false` return already reports the timeout.
+        i3c_debug!(self.logger, "wait_xfer_complete: timeout");
+        let _ = self.enter_halt(true, config);
+        let _ = self.reset_ctrl(RESET_CTRL_XFER_QUEUES);
+        let _ = self.exit_halt(config);
+        self.regs.unmask_master_xfer_irqs();
+        false
+    }
+
+    fn detach_i3c_dev(&mut self, pos: usize) {
+        self.regs.dat_set_reject(pos);
+    }
+
+    fn attach_i3c_dev(&mut self, pos: usize, addr: u8) -> Result<(), I3cDrvError> {
+        let mut da_with_parity = addr;
+        if Self::even_parity(addr) {
+            da_with_parity |= 1 << 7;
+        }
+
+        self.regs.dat_program_addr(pos, da_with_parity);
+
+        Ok(())
+    }
+
+    fn attach_i2c_dev(&mut self, pos: usize, static_addr: u8) -> Result<(), I3cDrvError> {
+        // Legacy I2C entry: static address in the low field, the LEGACY bit
+        // routes transfers through the controller's I2C engine; SIR/MR stay
+        // rejected (an I2C device cannot raise them).
+        let raw = DEV_ADDR_TABLE_LEGACY_I2C_DEV
+            | DEV_ADDR_TABLE_SIR_REJECT
+            | DEV_ADDR_TABLE_MR_REJECT
+            | field_prep(DEV_ADDR_TABLE_STATIC_ADDR, u32::from(static_addr));
+        self.regs.dat_write_raw(pos, raw);
+        Ok(())
+    }
+
+    fn i2c_priv_xfer<'a>(
+        &mut self,
+        config: &mut I3cConfig,
+        pos: u8,
+        ops: &mut [I2cOp<'a>],
+    ) -> Result<(), I3cDrvError> {
+        if ops.is_empty() {
+            return Ok(());
+        }
+        // Same TID-width bound as private I3C transfers.
+        if ops.len() > MAX_PRIV_XFER_CMDS {
+            return Err(I3cDrvError::TooManyMsgs);
+        }
+        // Pre-validate every length before consuming any buffer
+        // (all-or-nothing, mirroring priv_xfer_build_cmds).
+        for op in ops.iter() {
+            let len = match op {
+                I2cOp::Write(b) => b.len(),
+                I2cOp::Read(b) => b.len(),
+            };
+            if len == 0 || len > MAX_XFER_DATA_LEN {
+                return Err(I3cDrvError::Invalid);
+            }
+        }
+
+        // The DAT entry marks the device as legacy I2C, so the SPEED field
+        // selects between the I2C timing sets programmed by init_clock.
+        let speed = if config.i2c_scl_hz > 400_000 {
+            SpeedI2c::Fmp
+        } else {
+            SpeedI2c::Fm
+        } as u32;
+
+        let mut cmds: heapless::Vec<I3cCmd<'a>, MAX_CMDS> = heapless::Vec::new();
+        let nops = ops.len();
+        for (i, op) in ops.iter_mut().enumerate() {
+            let mut cmd = I3cCmd::new();
+            let len = match op {
+                I2cOp::Write(b) => b.len(),
+                I2cOp::Read(b) => b.len(),
+            };
+            cmd.cmd_hi = field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_XFER_ARG)
+                | field_prep(
+                    COMMAND_PORT_ARG_DATA_LEN,
+                    u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?,
+                );
+            cmd.cmd_lo = field_prep(
+                COMMAND_PORT_TID,
+                u32::try_from(i).map_err(|_| I3cDrvError::Invalid)?,
+            ) | field_prep(COMMAND_PORT_DEV_INDEX, u32::from(pos))
+                | field_prep(COMMAND_PORT_SPEED, speed)
+                | COMMAND_PORT_ROC;
+
+            match op {
+                I2cOp::Write(b) => {
+                    cmd.tx = Some(*b);
+                    cmd.tx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?;
+                }
+                I2cOp::Read(b) => {
+                    // Move the caller's reborrow into the command (same
+                    // consume contract as priv_xfer); `take` leaves an empty
+                    // slice behind.
+                    let buf: &'a mut [u8] = core::mem::take(b);
+                    cmd.rx = Some(buf);
+                    cmd.rx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?;
+                    cmd.cmd_lo |= COMMAND_PORT_READ_TRANSFER;
+                }
+            }
+
+            if i + 1 == nops {
+                cmd.cmd_lo |= COMMAND_PORT_TOC;
+            }
+            cmds.push(cmd).map_err(|_| I3cDrvError::TooManyMsgs)?;
+        }
+
+        let mut xfer = I3cXfer::new(cmds.as_mut_slice());
+        self.start_xfer(config, &mut xfer);
+
+        if !self.wait_xfer_complete(config, &mut xfer, I3C_OP_TIMEOUT_US) {
+            return Err(I3cDrvError::Timeout);
+        }
+
+        match xfer.ret {
+            0 => Ok(()),
+            _ => Err(I3cDrvError::IoError),
+        }
+    }
+
+    #[allow(clippy::too_many_lines)]
+    fn do_ccc(
+        &mut self,
+        config: &mut I3cConfig,
+        payload: &mut CccPayload<'_, '_>,
+    ) -> Result<(), I3cDrvError> {
+        let mut cmds = [I3cCmd {
+            cmd_lo: 0,
+            cmd_hi: 0,
+            tx: None,
+            rx: None,
+            tx_len: 0,
+            rx_len: 0,
+            ret: 0,
+        }];
+
+        let mut pos = 0;
+        let mut rnw: bool = false;
+        let mut is_broadcast = false;
+
+        let (id, data_len) = {
+            let Some(ccc) = payload.ccc.as_ref() else {
+                return Err(I3cDrvError::Invalid);
+            };
+            (ccc.id, ccc.data.as_deref().map_or(0, <[u8]>::len))
+        };
+
+        let dbp_is_direct = id > 0x7F;
+        let db: u8 = if dbp_is_direct && data_len > 0 {
+            payload
+                .ccc
+                .as_ref()
+                .and_then(|c| c.data.as_deref())
+                .map_or(0, |d| d[0])
+        } else {
+            0
+        };
+
+        {
+            let cmd = &mut cmds[0];
+
+            if id <= 0x7F {
+                is_broadcast = true;
+
+                if data_len > 0
+                    && let Some(d) = payload.ccc.as_ref().and_then(|c| c.data.as_deref())
+                {
+                    cmd.tx = Some(d);
+                    cmd.tx_len = u32::try_from(data_len).map_err(|_| I3cDrvError::Invalid)?;
+                }
+            } else {
+                let Some(tgt_addr) = payload
+                    .targets
+                    .as_ref()
+                    .and_then(|ts| ts.first())
+                    .map(|t| t.addr)
+                else {
+                    return Err(I3cDrvError::Invalid);
+                };
+                let pos_ops = config.attached.pos_of_addr(tgt_addr);
+                i3c_debug!(
+                    self.logger,
+                    "do_ccc: tgt_addr=0x{:02x}, pos_ops={:?}",
+                    tgt_addr,
+                    pos_ops
+                );
+                pos = match pos_ops {
+                    Some(p) => p,
+                    None => return Err(I3cDrvError::Invalid),
+                };
+                i3c_debug!(
+                    self.logger,
+                    "do_ccc: tgt_addr=0x{:02x}, pos={}",
+                    tgt_addr,
+                    pos
+                );
+
+                let Some(tp) = payload.targets.as_deref_mut().and_then(|ts| ts.first_mut()) else {
+                    return Err(I3cDrvError::Invalid);
+                };
+
+                rnw = tp.rnw;
+
+                if rnw {
+                    let len = tp.data.as_deref().map_or(0, <[u8]>::len);
+                    if len == 0 {
+                        return Err(I3cDrvError::Invalid);
+                    }
+                    cmd.rx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?;
+                    cmd.rx = tp.data.as_deref_mut();
+                } else {
+                    let (d_opt, len) = match tp.data.as_deref() {
+                        Some(d) => (Some(d), d.len()),
+                        None => (None, 0),
+                    };
+                    cmd.tx = d_opt;
+                    cmd.tx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?;
+                    tp.num_xfer = len;
+                }
+            }
+        }
+
+        let cmd = &mut cmds[0];
+        cmd.cmd_hi = field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_XFER_ARG);
+
+        if dbp_is_direct && data_len > 0 {
+            cmd.cmd_lo |= COMMAND_PORT_DBP;
+            cmd.cmd_hi |= field_prep(COMMAND_PORT_ARG_DB, db.into());
+        }
+
+        if rnw {
+            cmd.cmd_hi |= field_prep(COMMAND_PORT_ARG_DATA_LEN, cmd.rx_len);
+        } else {
+            cmd.cmd_hi |= field_prep(COMMAND_PORT_ARG_DATA_LEN, cmd.tx_len);
+        }
+
+        cmd.cmd_lo |= field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_XFER_CMD)
+            | field_prep(COMMAND_PORT_CMD, id.into())
+            | field_prep(COMMAND_PORT_READ_TRANSFER, u32::from(rnw))
+            | COMMAND_PORT_CP
+            | COMMAND_PORT_ROC
+            | COMMAND_PORT_TOC;
+
+        if !is_broadcast {
+            cmd.cmd_lo |= field_prep(COMMAND_PORT_DEV_INDEX, u32::from(pos));
+        }
+
+        if id == I3C_CCC_SETHID || id == I3C_CCC_DEVCTRL {
+            cmd.cmd_lo |= field_prep(COMMAND_PORT_SPEED, SpeedI3c::I2cFmAsI3c as u32);
+        }
+
+        let mut xfer = I3cXfer::new(&mut cmds[..]);
+        self.start_xfer(config, &mut xfer);
+
+        // On timeout `wait_xfer_complete` already recovered the engine;
+        // `xfer.ret` stays -1 and falls through to the error mapping below
+        // (same outcome as the reference's timeout path).
+        let _ = self.wait_xfer_complete(config, &mut xfer, I3C_OP_TIMEOUT_US);
+
+        let ret = xfer.ret;
+        if ret == i32::try_from(RESPONSE_ERROR_IBA_NACK).map_err(|_| I3cDrvError::Invalid)? {
+            return Ok(());
+        }
+
+        if is_broadcast && let Some(ccc_rw) = payload.ccc.as_mut() {
+            let num_xfer = ccc_rw.data.as_deref().map(<[u8]>::len);
+            if let Some(n) = num_xfer {
+                ccc_rw.num_xfer = n;
+            }
+        }
+
+        match ret {
+            0 => Ok(()),
+            _ => Err(I3cDrvError::Invalid),
+        }
+    }
+
+    fn do_entdaa(&mut self, config: &mut I3cConfig, pos: u32) -> Result<(), I3cDrvError> {
+        i3c_debug!(self.logger, "do_entdaa: pos={}", pos);
+        let cmd = I3cCmd {
+            cmd_lo: field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_ADDR_ASSGN_CMD)
+                | field_prep(COMMAND_PORT_CMD, u32::from(I3C_CCC_ENTDAA))
+                | field_prep(COMMAND_PORT_DEV_COUNT, 1)
+                | field_prep(COMMAND_PORT_DEV_INDEX, pos)
+                | COMMAND_PORT_ROC
+                | COMMAND_PORT_TOC,
+            cmd_hi: field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_XFER_ARG),
+            tx: None,
+            rx: None,
+            tx_len: 0,
+            rx_len: 0,
+            ret: 0,
+        };
+
+        i3c_debug!(
+            self.logger,
+            "do_entdaa: cmd_lo=0x{:08x}, cmd_hi=0x{:08x}",
+            cmd.cmd_lo,
+            cmd.cmd_hi
+        );
+        let mut cmds = [cmd];
+        let mut xfer = I3cXfer::new(&mut cmds[..]);
+        xfer.ret = -1;
+
+        self.start_xfer(config, &mut xfer);
+
+        // Full operation budget — NOT the C driver's 10 ms. The C timeout is
+        // wall-clock (`k_sem_take(K_MSEC(10))`); this driver's timeout unit is
+        // cooperative-yield ticks, and a fast `yield_fn` makes the nominal
+        // value run far shorter in real time. A short budget here aborts a
+        // live ENTDAA mid-flight (halt + queue reset), wedging the DAA
+        // handshake. An ENTDAA nobody answers still exits early via NACK.
+        if !self.wait_xfer_complete(config, &mut xfer, I3C_OP_TIMEOUT_US) {
+            return Err(I3cDrvError::Timeout);
+        }
+
+        i3c_debug!(self.logger, "do_entdaa: xfer done");
+        match xfer.ret {
+            0 => Ok(()),
+            _ => Err(I3cDrvError::Invalid),
+        }
+    }
+
+    fn priv_xfer_build_cmds<'a>(
+        &mut self,
+        cmds: &mut [I3cCmd<'a>],
+        msgs: &mut [I3cMsg<'a>],
+        pos: u8,
+    ) -> Result<(), I3cDrvError> {
+        let cmds_len = cmds.len();
+        if cmds_len != msgs.len() {
+            return Err(I3cDrvError::Invalid);
+        }
+
+        // The transfer-ID field is 4 bits, so the message index used as the TID
+        // must stay below `MAX_PRIV_XFER_CMDS`. A larger batch would see indices
+        // >= 16 alias earlier commands once `field_prep` masks the TID, routing
+        // their responses onto the wrong message. Reject before consuming any
+        // buffer so the build stays all-or-nothing.
+        if cmds_len > MAX_PRIV_XFER_CMDS {
+            return Err(I3cDrvError::TooManyMsgs);
+        }
+
+        // Pre-validate every message before taking any buffer, so the build is
+        // all-or-nothing: a bad message late in the batch must not leave the
+        // earlier messages' `buf` already moved out to `None`. Non-consuming
+        // (`as_deref`) — purely a length/presence check. The upper bound is the
+        // 16-bit `COMMAND_PORT_ARG_DATA_LEN` field width; a longer buffer would
+        // truncate silently in `field_prep` (the per-command `u32::try_from`
+        // below only catches lengths above `u32::MAX`).
+        for m in msgs.iter() {
+            match m.buf.as_deref() {
+                Some(b) if !b.is_empty() && b.len() <= MAX_XFER_DATA_LEN => {}
+                _ => return Err(I3cDrvError::Invalid),
+            }
+        }
+
+        // Zip (not parallel `cmds[i]`/`msgs[i]` indexing) so the build loop is
+        // panic-free for the `no_panics` analysis; lengths are equal (checked).
+        for (i, (cmd, m)) in cmds.iter_mut().zip(msgs.iter_mut()).enumerate() {
+            let is_read = (m.flags & I3C_MSG_READ) != 0;
+
+            // Move (`Option::take`) — never alias — the caller's buffer out of
+            // the message and into the command: the one `&'a mut` reborrow is
+            // transferred, so the FIFO scatter path in `process_responses`
+            // holds the only live reference. No `unsafe`, no second `&mut` to
+            // the same memory. The message keeps only the transfer lengths
+            // (`num_xfer`/`actual_len`); `m.buf` is `None` after this call and
+            // no caller reads it post-transfer (the caller still owns the real
+            // buffer the reborrow came from). Pre-validation above guarantees
+            // the `Some(non-empty)` arm here, so no message is ever left with a
+            // half-built (taken) buffer on the error path.
+            let buf = match m.buf.take() {
+                Some(b) if !b.is_empty() => b,
+                other => {
+                    m.buf = other;
+                    return Err(I3cDrvError::Invalid);
+                }
+            };
+            let len = buf.len();
+
+            *cmd = I3cCmd {
+                cmd_hi: field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_XFER_ARG)
+                    | field_prep(
+                        COMMAND_PORT_ARG_DATA_LEN,
+                        u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?,
+                    ),
+                cmd_lo: field_prep(
+                    COMMAND_PORT_TID,
+                    u32::try_from(i).map_err(|_| I3cDrvError::Invalid)?,
+                ) | field_prep(COMMAND_PORT_DEV_INDEX, u32::from(pos))
+                    | COMMAND_PORT_ROC,
+                tx: None,
+                rx: None,
+                tx_len: 0,
+                rx_len: 0,
+                ret: 0,
+            };
+
+            if is_read {
+                cmd.rx = Some(buf);
+                cmd.rx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?;
+                cmd.cmd_lo |= COMMAND_PORT_READ_TRANSFER;
+            } else {
+                m.num_xfer = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?;
+                // Downgrade the moved `&'a mut [u8]` to `&'a [u8]` for the TX
+                // side (a move-coercion, not a reborrow — keeps lifetime `'a`).
+                let tx_slice: &'a [u8] = buf;
+                cmd.tx = Some(tx_slice);
+                cmd.tx_len = u32::try_from(len).map_err(|_| I3cDrvError::Invalid)?;
+            }
+
+            let is_last = i + 1 == cmds_len;
+            if is_last {
+                cmd.cmd_lo |= COMMAND_PORT_TOC;
+            }
+        }
+
+        Ok(())
+    }
+
+    fn priv_xfer(
+        &mut self,
+        config: &mut I3cConfig,
+        pid: u64,
+        msgs: &mut [I3cMsg],
+    ) -> Result<(), I3cDrvError> {
+        let pos_opt = config.attached.pos_of_pid(pid);
+        let pos: u8 = pos_opt.ok_or(I3cDrvError::NoDatPos)?;
+
+        if msgs.len() == 1 {
+            let mut cmd = I3cCmd::new();
+            let cmds = core::slice::from_mut(&mut cmd);
+
+            self.priv_xfer_build_cmds(cmds, msgs, pos)?;
+
+            let mut xfer = I3cXfer::new(cmds);
+            self.start_xfer(config, &mut xfer);
+
+            if !self.wait_xfer_complete(config, &mut xfer, I3C_OP_TIMEOUT_US) {
+                return Err(I3cDrvError::Timeout);
+            }
+
+            if let Some(m) = msgs.first_mut()
+                && (m.flags & I3C_MSG_READ) != 0
+            {
+                m.actual_len = xfer.cmds.first().map_or(0, |c| c.rx_len);
+            }
+
+            return match xfer.ret {
+                0 => Ok(()),
+                _ => Err(I3cDrvError::Timeout),
+            };
+        }
+
+        let mut cmds: heapless::Vec<I3cCmd, MAX_CMDS> = heapless::Vec::new();
+        for _ in 0..msgs.len() {
+            // `?` (not `.unwrap()`) keeps this panic-free; > MAX_CMDS msgs is a
+            // typed error, not a panic.
+            cmds.push(I3cCmd {
+                cmd_lo: 0,
+                cmd_hi: 0,
+                tx: None,
+                rx: None,
+                tx_len: 0,
+                rx_len: 0,
+                ret: 0,
+            })
+            .map_err(|_| I3cDrvError::TooManyMsgs)?;
+        }
+
+        let ret = self.priv_xfer_build_cmds(cmds.as_mut_slice(), msgs, pos);
+        match ret {
+            Ok(()) => {}
+            Err(e) => return Err(e),
+        }
+
+        let mut xfer = I3cXfer::new(cmds.as_mut_slice());
+        self.start_xfer(config, &mut xfer);
+
+        if !self.wait_xfer_complete(config, &mut xfer, I3C_OP_TIMEOUT_US) {
+            return Err(I3cDrvError::Timeout);
+        }
+
+        for (i, m) in msgs.iter_mut().enumerate() {
+            if (m.flags & I3C_MSG_READ) != 0
+                && let Some(c) = xfer.cmds.get(i)
+            {
+                m.actual_len = c.rx_len;
+            }
+        }
+
+        match xfer.ret {
+            0 => Ok(()),
+            _ => Err(I3cDrvError::Timeout),
+        }
+    }
+}
+
+impl<Y: FnMut(u32)> HardwareTarget for Ast1060I3c<Y> {
+    fn target_tx_write(&mut self, buf: &[u8]) {
+        self.wr_tx_fifo(buf);
+        let cmd = field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_SLAVE_DATA_CMD)
+            | field_prep(
+                COMMAND_PORT_ARG_DATA_LEN,
+                u32::try_from(buf.len()).map_or(0, |v| v),
+            )
+            | field_prep(COMMAND_PORT_TID, Tid::TargetRdData as u32);
+
+        self.regs.push_cmd(cmd);
+    }
+
+    fn target_ibi_raise_hj(&self, config: &mut I3cConfig) -> Result<(), I3cDrvError> {
+        if !config.is_secondary {
+            return Err(I3cDrvError::Invalid);
+        }
+        if !self.regs.hj_capable() {
+            return Err(I3cDrvError::Invalid);
+        }
+
+        if self.regs.dynamic_addr_valid() {
+            return Err(I3cDrvError::Access);
+        }
+
+        self.regs.raise_hot_join_request();
+
+        Ok(())
+    }
+
+    fn target_pending_read_notify(
+        &mut self,
+        config: &mut I3cConfig,
+        buf: &[u8],
+        notifier: &mut I3cIbi,
+    ) -> Result<(), I3cDrvError> {
+        let events = isr_events(self.bus() as usize);
+
+        // A fault the ISR deferred (errored response / halted engine after a
+        // CCC): recover here on the thread, where the wait policy lives.
+        if events.take_fault() {
+            // Best-effort: a recovery timeout here must not block the SIR
+            // attempt below, which has its own timeout/recovery path.
+            i3c_debug!(self.logger, "recovering deferred target fault");
+            let _ = self.enter_halt(false, config);
+            let _ = self.reset_ctrl(RESET_CTRL_QUEUES);
+            let _ = self.exit_halt(config);
+        }
+
+        let reg = self.regs.read_slv_event_ctrl();
+        if !(config.sir_allowed_by_sw && (reg & SLV_EVENT_CTRL_SIR_EN != 0)) {
+            return Err(I3cDrvError::Access);
+        }
+
+        let Some(mdb) = notifier.first_byte() else {
+            return Err(I3cDrvError::Invalid);
+        };
+
+        self.set_ibi_mdb(mdb);
+        if let Some(p) = notifier.payload
+            && !p.is_empty()
+        {
+            self.wr_tx_fifo(p);
+        }
+
+        let payload_len = u32::try_from(notifier.payload.map_or(0, <[u8]>::len))
+            .map_err(|_| I3cDrvError::Invalid)?;
+        let cmd: u32 = field_prep(COMMAND_PORT_ATTR, COMMAND_ATTR_SLAVE_DATA_CMD)
+            | field_prep(COMMAND_PORT_ARG_DATA_LEN, payload_len)
+            | field_prep(COMMAND_PORT_TID, Tid::TargetIbi as u32);
+        self.regs.push_cmd(cmd);
+
+        events.target_ibi_done.reset();
+
+        self.regs.set_resp_buf_threshold(0);
+
+        self.target_tx_write(buf);
+        events.target_data_done.reset();
+
+        self.regs.raise_sir();
+
+        if !events
+            .target_ibi_done
+            .wait_for_us(I3C_OP_TIMEOUT_US, &mut self.yield_fn)
+        {
+            // Vendor C driver parity (`target_rst_worker`): an unanswered SIR
+            // means the engine may be wedged beyond a queue reset — re-run the
+            // full controller init. Side effects match the C driver: the
+            // dynamic address is dropped (the bus master must re-run DAA) and
+            // `sir_allowed_by_sw` is cleared until the next DA assignment.
+            // Best-effort; `IoError` below already reports the failure.
+            i3c_debug!(self.logger, "SIR timeout! Reset I3C controller");
+            let _ = self.init(config);
+            return Err(I3cDrvError::IoError);
+        }
+
+        if !events
+            .target_data_done
+            .wait_for_us(I3C_OP_TIMEOUT_US, &mut self.yield_fn)
+        {
+            // Best-effort recovery; `Timeout` below already reports the failure.
+            i3c_debug!(self.logger, "wait master read timeout! Reset queues");
+            self.i3c_disable(config.is_secondary);
+            let _ = self.reset_ctrl(RESET_CTRL_QUEUES);
+            self.i3c_enable(config);
+            return Err(I3cDrvError::Timeout);
+        }
+
+        Ok(())
+    }
+}
diff --git a/target/ast10x0/peripherals/i3c/ibi.rs b/target/ast10x0/peripherals/i3c/ibi.rs
new file mode 100644
index 00000000..c73fddda
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/ibi.rs
@@ -0,0 +1,252 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C In-Band Interrupt (IBI) Work Queue
+//!
+//! Handles IBI events including Hot-Join, SIR (Slave Interrupt Request),
+//! and target dynamic address assignment.
+//!
+//! Ported from `aspeed-rust/src/i3c/ibi.rs` @ ce3b567.
+//!
+//! **Porting delta (queue mechanism).** The reference uses `heapless::spsc`
+//! `Producer`/`Consumer` handles, split once and parked in a global
+//! `Mutex<UnsafeCell<..>>`. On this target (heapless 0.9 + this toolchain) we
+//! observed unstable behavior when those handles were stored in a `static` and
+//! later re-accessed across separate critical sections: a split that read back
+//! `prod=Some, cons=Some` in-place would, after the consumer was taken in a
+//! later critical section, read back `prod=None, cons=Some`. The root cause was
+//! not fully isolated, so this port uses a simpler fixed-size ring buffer whose
+//! aliasing and lifetime rules are easier to audit.
+//!
+//! So the SPSC split is replaced by a plain fixed-size ring buffer of
+//! `Option<IbiWork>` (`IbiWork` is `Copy`, no niche pointers), guarded by the
+//! same `critical_section`. The process-global queue/handler design (goal.md
+//! ADR-3) is preserved — an ISR still cannot borrow a stack-owned device, so
+//! the IBI plane stays global, arbitrated by `critical_section`. The public
+//! API (`i3c_ibi_workq_consumer().dequeue()` + the three enqueue functions) is
+//! unchanged.
+
+use core::cell::UnsafeCell;
+use critical_section::Mutex;
+
+/// IBI queue depth
+const IBIQ_DEPTH: usize = 16;
+/// Maximum IBI payload data size
+const IBI_DATA_MAX: u8 = 16;
+/// Maximum private-write payload captured per [`IbiWork::TargetMasterWrite`].
+///
+/// The vendor C driver delivers the full write (heap-allocated per response);
+/// this port has no heap, so the work item carries an inline buffer instead.
+/// Writes longer than this are truncated (`len` reports the captured length);
+/// the ISR drains the excess so the FIFO stays aligned.
+///
+/// **Sizing is ISR-stack-bound, not RAM-bound.** `IbiWork` is passed by value
+/// through the enqueue path, so the ISR transiently stacks roughly
+/// `2 * (IBI_MWR_DATA_MAX + 8)` bytes per enqueue on top of the ISR's own
+/// bounce buffer (also this size, see `isr_target_responses`). 128 was
+/// empirically enough to HardFault the kernel handler stack on AST1060; 64
+/// keeps the total below the original 256-byte-bounce-buffer footprint while
+/// quadrupling the old 16-byte payload cap. Static cost of the rings is
+/// `(IBI_MWR_DATA_MAX + 8) * IBIQ_DEPTH * 4 buses` (~4.6 KiB at 64).
+pub const IBI_MWR_DATA_MAX: usize = 64;
+
+// =============================================================================
+// IBI Work Item
+// =============================================================================
+
+/// IBI work item representing an interrupt event
+#[derive(Debug, Clone, Copy)]
+pub enum IbiWork {
+    /// Hot-Join request from a device
+    HotJoin,
+    /// Slave Interrupt Request
+    Sirq {
+        /// Address of requesting device
+        addr: u8,
+        /// Length of payload data
+        len: u8,
+        /// Payload data
+        data: [u8; IBI_DATA_MAX as usize],
+    },
+    /// Target dynamic address assignment notification
+    TargetDaAssignment,
+    /// Private write received by this target from the controller.
+    TargetMasterWrite {
+        /// Number of received bytes captured in `data`.
+        len: u8,
+        /// Received data, truncated to [`IBI_MWR_DATA_MAX`].
+        data: [u8; IBI_MWR_DATA_MAX],
+    },
+}
+
+// =============================================================================
+// Static Ring-Buffer Storage
+// =============================================================================
+
+/// Fixed-size single-producer/single-consumer ring of IBI work items.
+///
+/// All access is serialized by the per-bus `critical_section::Mutex`, so the
+/// indices need no atomics; the producer is the I3C ISR and the consumer is the
+/// owning test/driver loop.
+struct IbiRing {
+    buf: [Option<IbiWork>; IBIQ_DEPTH],
+    head: usize,
+    len: usize,
+}
+
+impl IbiRing {
+    const fn new() -> Self {
+        Self {
+            buf: [None; IBIQ_DEPTH],
+            head: 0,
+            len: 0,
+        }
+    }
+
+    fn push(&mut self, work: IbiWork) -> bool {
+        // `get_mut` + modulo keep this panic-free even if the indices were
+        // somehow out of range; `head` is normalized first.
+        self.head %= IBIQ_DEPTH;
+        if self.len >= IBIQ_DEPTH {
+            return false;
+        }
+        let idx = (self.head + self.len) % IBIQ_DEPTH;
+        if let Some(slot) = self.buf.get_mut(idx) {
+            *slot = Some(work);
+            self.len += 1;
+            true
+        } else {
+            false
+        }
+    }
+
+    fn pop(&mut self) -> Option<IbiWork> {
+        self.head %= IBIQ_DEPTH;
+        if self.len == 0 || self.len > IBIQ_DEPTH {
+            // Empty, or a corrupt length — treat as empty (panic-free).
+            return None;
+        }
+        let work = self.buf.get_mut(self.head).and_then(Option::take);
+        self.head = (self.head + 1) % IBIQ_DEPTH;
+        self.len -= 1;
+        work
+    }
+}
+
+// INTENTIONAL EXCEPTION to borrow-arbitrated exclusivity (goal.md ADR-3):
+// the IBI plane is process-global mutable state because the producer is the
+// ISR, which cannot borrow a stack-owned device. Bounded (one fixed-depth
+// ring per bus) and serialized by the critical section; access is via the
+// leaf `ring_push`/`ring_pop` helpers only.
+static IBI_RINGS: [Mutex<UnsafeCell<IbiRing>>; 4] = [
+    Mutex::new(UnsafeCell::new(IbiRing::new())),
+    Mutex::new(UnsafeCell::new(IbiRing::new())),
+    Mutex::new(UnsafeCell::new(IbiRing::new())),
+    Mutex::new(UnsafeCell::new(IbiRing::new())),
+];
+
+/// Push `work` onto the ring for `bus`. Returns `false` if `bus` is out of
+/// range or the ring is full.
+///
+/// The `&mut IbiRing` is confined to this leaf function — no caller-provided
+/// code runs while it is live — so the exclusive borrow cannot be re-entered.
+fn ring_push(bus: usize, work: IbiWork) -> bool {
+    let Some(workq) = IBI_RINGS.get(bus) else {
+        return false;
+    };
+    critical_section::with(|cs| {
+        // SAFETY: the critical section excludes ISR/thread concurrency, and
+        // the `&mut IbiRing` never escapes this function (the ring is only
+        // reachable via `ring_push`/`ring_pop`, neither of which calls back
+        // into caller code), so this is the only live reference.
+        let ring: &mut IbiRing = unsafe { &mut *workq.borrow(cs).get() };
+        ring.push(work)
+    })
+}
+
+/// Pop the next work item from the ring for `bus`, if any.
+///
+/// Same confinement argument as [`ring_push`].
+fn ring_pop(bus: usize) -> Option<IbiWork> {
+    let workq = IBI_RINGS.get(bus)?;
+    critical_section::with(|cs| {
+        // SAFETY: see `ring_push` — critical section + leaf confinement make
+        // this the only live reference to the ring.
+        let ring: &mut IbiRing = unsafe { &mut *workq.borrow(cs).get() };
+        ring.pop()
+    })
+}
+
+// =============================================================================
+// Consumer Handle
+// =============================================================================
+
+/// Consumer handle for a bus's IBI work queue.
+///
+/// Holds no state beyond the bus index; dequeuing reads the shared ring under
+/// the critical section. Returned by [`i3c_ibi_workq_consumer`].
+pub struct IbiConsumer {
+    bus: usize,
+}
+
+impl IbiConsumer {
+    /// Dequeue the next IBI work item, if any.
+    #[must_use]
+    pub fn dequeue(&mut self) -> Option<IbiWork> {
+        ring_pop(self.bus)
+    }
+}
+
+/// Get the IBI work queue consumer for a bus.
+///
+/// Returns `None` if the bus index is out of range.
+#[must_use]
+pub fn i3c_ibi_workq_consumer(bus: usize) -> Option<IbiConsumer> {
+    if bus >= IBI_RINGS.len() {
+        return None;
+    }
+    Some(IbiConsumer { bus })
+}
+
+// =============================================================================
+// Enqueue Functions
+// =============================================================================
+
+/// Enqueue a target dynamic address assignment notification
+#[must_use]
+pub fn i3c_ibi_work_enqueue_target_da_assignment(bus: usize) -> bool {
+    ring_push(bus, IbiWork::TargetDaAssignment)
+}
+
+/// Enqueue a Hot-Join notification
+#[must_use]
+pub fn i3c_ibi_work_enqueue_hotjoin(bus: usize) -> bool {
+    ring_push(bus, IbiWork::HotJoin)
+}
+
+/// Enqueue a target interrupt (SIR) notification
+#[must_use]
+pub fn i3c_ibi_work_enqueue_target_irq(bus: usize, addr: u8, data: &[u8]) -> bool {
+    let mut ibi_buf = [0u8; IBI_DATA_MAX as usize];
+    let take = core::cmp::min(IBI_DATA_MAX as usize, data.len());
+    ibi_buf[..take].copy_from_slice(&data[..take]);
+    let work = IbiWork::Sirq {
+        addr,
+        len: u8::try_from(take).unwrap_or(IBI_DATA_MAX),
+        data: ibi_buf,
+    };
+    ring_push(bus, work)
+}
+
+/// Enqueue a private write received by this target from the controller.
+#[must_use]
+pub fn i3c_ibi_work_enqueue_target_master_write(bus: usize, data: &[u8]) -> bool {
+    let mut buf = [0u8; IBI_MWR_DATA_MAX];
+    let take = core::cmp::min(IBI_MWR_DATA_MAX, data.len());
+    buf[..take].copy_from_slice(&data[..take]);
+    let work = IbiWork::TargetMasterWrite {
+        len: u8::try_from(take).unwrap_or(u8::MAX),
+        data: buf,
+    };
+    ring_push(bus, work)
+}
diff --git a/target/ast10x0/peripherals/i3c/mod.rs b/target/ast10x0/peripherals/i3c/mod.rs
new file mode 100644
index 00000000..a915d804
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/mod.rs
@@ -0,0 +1,94 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! AST1060 I3C bare-metal driver core
+//!
+//! # Overview
+//!
+//! This module provides a hardware abstraction layer for I3C controllers,
+//! supporting both controller (master) and target (secondary) modes. It is a
+//! behavioral-parity port of `aspeed-rust/src/i3c/` @ ce3b567 into the openprot
+//! AST10x0 peripheral HAL. See `plans/goal.md` for the parity standard and the
+//! deltas ledger (notably: confined-`unsafe` façade + injected yield closure on
+//! [`hardware::Ast1060I3c`], and `proposed_traits` replaced by inherent methods
+//! on [`controller::I3cController`]).
+//!
+//! # Architecture
+//!
+//! - [`controller`]: Main I3C controller abstraction + master/target operations
+//! - [`config`]: Configuration types and device management
+//! - [`types`]: Core data types (commands, messages, transfers)
+//! - [`error`]: Error types
+//! - [`constants`]: Hardware register definitions
+//! - [`hardware`]: Hardware interface (traits + AST1060 implementation)
+//! - [`ccc`]: Common Command Code operations
+//! - [`ibi`]: In-Band Interrupt work queue
+//!
+//! # Features
+//!
+//! - I3C SDR and HDR modes
+//! - Dynamic address assignment (ENTDAA)
+//! - In-Band Interrupts (IBI)
+//! - Hot-Join support
+//! - Target mode operation
+//! - Legacy I2C device support
+
+pub mod ccc;
+pub mod config;
+pub mod constants;
+pub mod controller;
+pub mod error;
+pub mod hardware;
+pub mod ibi;
+pub mod registers;
+pub mod types;
+
+// =============================================================================
+// Public Re-exports
+// =============================================================================
+
+// Controller (two-state lifecycle: Uninitialized -> Ready, matching the SMC
+// peripheral's precedent)
+pub use controller::{I3cController, Ready, Uninitialized};
+
+// Error types
+pub use error::{CccErrorKind, I3cError, Result};
+
+// Configuration
+pub use config::{
+    AddrBook, Attached, CommonCfg, CommonState, DeviceEntry, I3cConfig, I3cTargetConfig, ResetSpec,
+    I3C_MAX_CORE_CLK, I3C_MIN_CORE_CLK_HDR, I3C_MIN_CORE_CLK_SDR,
+};
+
+// Core types
+pub use types::{
+    Completion, DevKind, I2cOp, I3cCmd, I3cDeviceId, I3cIbi, I3cIbiType, I3cMsg, I3cPid,
+    I3cStatus, I3cXfer, SpeedI2c, SpeedI3c, Tid,
+};
+
+// Hardware interface
+pub use hardware::{
+    dispatch_i3c_irq, register_i3c_irq_handler, Ast1060I3c, HardwareClock, HardwareCore,
+    HardwareFifo, HardwareInterface, HardwareRecovery, HardwareTarget, HardwareTransfer, IsrCtx,
+};
+
+// Confined-unsafe MMIO façade (runtime bus selection)
+pub use registers::I3cRegisters;
+
+// CCC operations
+pub use ccc::{
+    ccc_events_all_set, ccc_events_set, ccc_getbcr, ccc_getdcr, ccc_getmrl, ccc_getmwl,
+    ccc_getmxds, ccc_getpid, ccc_getstatus, ccc_getstatus_fmt1, ccc_rstact_all, ccc_rstdaa_all,
+    ccc_setmrl, ccc_setmrl_all, ccc_setmwl, ccc_setmwl_all, ccc_setnewda, Ccc, CccPayload,
+    CccRstActDefByte, CccTargetPayload, GetStatusDefByte, GetStatusFormat, GetStatusResp,
+};
+
+// IBI work queue
+pub use ibi::{
+    i3c_ibi_work_enqueue_hotjoin, i3c_ibi_work_enqueue_target_da_assignment,
+    i3c_ibi_work_enqueue_target_irq, i3c_ibi_work_enqueue_target_master_write,
+    i3c_ibi_workq_consumer, IbiConsumer, IbiWork,
+};
+
+// Constants (wildcard export for convenience)
+pub use constants::*;
diff --git a/target/ast10x0/peripherals/i3c/registers.rs b/target/ast10x0/peripherals/i3c/registers.rs
new file mode 100644
index 00000000..33799775
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/registers.rs
@@ -0,0 +1,885 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! Confined-`unsafe` MMIO façade over the per-bus I3C register blocks.
+//!
+//! One driver manages multiple bus instances: the bus is selected at
+//! **runtime** by index (no per-instance type parameter), mirroring the
+//! reference `aspeed-rust` driver. Following the `SmcRegisters` precedent,
+//! **all register operations go through this single point**: the rest of the
+//! driver (`hardware.rs` upward) never touches PAC types or MMIO `unsafe` —
+//! it calls the intent-named methods below.
+//!
+//! Method naming follows the AST1060 PAC convention where an operation maps
+//! to one register (`read_reset_ctrl` ↔ `i3cd034`), and the datasheet's
+//! vocabulary where an operation is a multi-field sequence
+//! (`enable_controller_primary`, `assert_all_queue_resets`).
+
+use core::marker::PhantomData;
+
+use super::constants::MAX_BUSES;
+
+// -----------------------------------------------------------------------------
+// Per-bus register dispatch (private)
+// -----------------------------------------------------------------------------
+//
+// The I3C-global block packs one reg0/reg1 pair per bus, and the DAT is eight
+// identically-shaped registers; the PAC gives each its own accessor, so these
+// macros do the bus/position match once, here, inside the façade. The `_`
+// arms are unreachable: `I3cRegisters::new` validates `bus`, and DAT
+// positions are bounded by `dat_depth()` — kept panic-free regardless.
+
+macro_rules! i3cg_reg0 {
+    ($self:expr, $($ops:tt)*) => {{
+        match $self.bus {
+            0 => $self.i3cg().i3c010().$($ops)*,
+            1 => $self.i3cg().i3c020().$($ops)*,
+            2 => $self.i3cg().i3c030().$($ops)*,
+            _ => $self.i3cg().i3c040().$($ops)*,
+        }
+    }};
+}
+
+macro_rules! i3cg_reg1 {
+    ($self:expr, $($ops:tt)*) => {{
+        match $self.bus {
+            0 => $self.i3cg().i3c014().$($ops)*,
+            1 => $self.i3cg().i3c024().$($ops)*,
+            2 => $self.i3cg().i3c034().$($ops)*,
+            _ => $self.i3cg().i3c044().$($ops)*,
+        }
+    }};
+}
+
+macro_rules! dat_reg {
+    ($self:expr, $pos:expr, $($ops:tt)*) => {{
+        match $pos {
+            0 => $self.i3c().i3cd280().$($ops)*,
+            1 => $self.i3c().i3cd284().$($ops)*,
+            2 => $self.i3c().i3cd288().$($ops)*,
+            3 => $self.i3c().i3cd28c().$($ops)*,
+            4 => $self.i3c().i3cd290().$($ops)*,
+            5 => $self.i3c().i3cd294().$($ops)*,
+            6 => $self.i3c().i3cd298().$($ops)*,
+            _ => $self.i3c().i3cd29c().$($ops)*,
+        }
+    }};
+}
+
+/// Safe wrapper around the I3C / I3C-global / SCU hardware registers of one bus.
+///
+/// This struct consolidates all unsafe I3C MMIO access. All register
+/// operations go through this single point, making it easy to audit safety
+/// invariants — the same shape as `SmcRegisters` in `smc/registers.rs`.
+///
+/// Not `Copy`/`Clone`: an `I3cRegisters` represents exclusive ownership of
+/// one bus's register blocks.
+pub struct I3cRegisters {
+    i3c: *const ast1060_pac::i3c::RegisterBlock,
+    i3cg: *const ast1060_pac::i3cglobal::RegisterBlock,
+    scu: *const ast1060_pac::scu::RegisterBlock,
+    bus: u8,
+    // `*const ()` marker keeps the handle `!Send` and `!Sync`. An
+    // `I3cRegisters` represents exclusive ownership of one bus's register
+    // blocks; it must not be shared between threads or moved into another
+    // execution context where it could alias the controller it owns.
+    _not_send_sync: PhantomData<*const ()>,
+}
+
+impl I3cRegisters {
+    /// Create the register façade for `bus` (0..[`MAX_BUSES`]).
+    ///
+    /// Returns `None` if `bus` is out of range — every accessor below is
+    /// therefore panic-free: a constructed façade always holds valid pointers
+    /// and an in-range bus index.
+    ///
+    /// `pub(crate)`: the single *public* unsafe gate is
+    /// [`Ast1060I3c::new`](super::hardware::Ast1060I3c::new), which forwards
+    /// this contract; external callers cannot construct a second façade for
+    /// a bus behind the driver's back.
+    ///
+    /// # Safety
+    ///
+    /// This is the entire `unsafe` perimeter for I3C MMIO (Delta D3):
+    /// - The AST1060 PAC singleton pointers (`I3c*::ptr()`,
+    ///   `I3cglobal::ptr()`, `Scu::ptr()`) must point to valid register
+    ///   blocks for the program's lifetime (they do on AST1060 hardware).
+    /// - Access through the returned façade must be serialized by the caller
+    ///   (the type is `!Sync`); only one owner per physical bus may be
+    ///   active at a time.
+    #[must_use]
+    pub(crate) const unsafe fn new(bus: u8) -> Option<Self> {
+        let i3c = match bus {
+            0 => ast1060_pac::I3c::ptr(),
+            1 => ast1060_pac::I3c1::ptr(),
+            2 => ast1060_pac::I3c2::ptr(),
+            3 => ast1060_pac::I3c3::ptr(),
+            _ => return None,
+        };
+        // Redundant with the match above, but keeps the invariant explicit if
+        // MAX_BUSES and the match ever diverge.
+        if bus as usize >= MAX_BUSES {
+            return None;
+        }
+        Some(Self {
+            i3c,
+            i3cg: ast1060_pac::I3cglobal::ptr(),
+            scu: ast1060_pac::Scu::ptr(),
+            bus,
+            _not_send_sync: PhantomData,
+        })
+    }
+
+    /// Bus index this façade was constructed for (always `< MAX_BUSES`).
+    #[inline]
+    #[must_use]
+    pub fn bus(&self) -> u8 {
+        self.bus
+    }
+
+    /// Second handle over the same bus for the **ISR side**.
+    ///
+    /// This is the one sanctioned exception to "one `I3cRegisters` per bus":
+    /// the interrupt service routine cannot borrow the thread-owned handle,
+    /// so it gets its own. No Rust memory is aliased (the pointers target
+    /// MMIO, not Rust objects).
+    ///
+    /// # Safety
+    ///
+    /// Device access through the alias must remain serialized with the
+    /// owning handle — on this single-core target that holds because the ISR
+    /// runs atomically with respect to the thread.
+    pub(crate) unsafe fn isr_alias(&self) -> Self {
+        Self {
+            i3c: self.i3c,
+            i3cg: self.i3cg,
+            scu: self.scu,
+            bus: self.bus,
+            _not_send_sync: PhantomData,
+        }
+    }
+
+    // -------------------------------------------------------------------------
+    // Interior deref helpers — the only repeated `unsafe`
+    // -------------------------------------------------------------------------
+
+    /// The only repeated interior `unsafe` for the I3C block.
+    ///
+    /// Returns a `'static` reference: the constructor's contract guarantees
+    /// the pointer is valid for the program lifetime.
+    #[inline]
+    fn i3c(&self) -> &'static ast1060_pac::i3c::RegisterBlock {
+        // SAFETY: `new` guarantees a valid pointer for the program lifetime;
+        // access is serialized by the caller (the type is `!Sync`).
+        unsafe { &*self.i3c }
+    }
+
+    /// The only repeated interior `unsafe` for the I3C-global block. See
+    /// [`i3c`](Self::i3c).
+    #[inline]
+    fn i3cg(&self) -> &'static ast1060_pac::i3cglobal::RegisterBlock {
+        // SAFETY: see `i3c`.
+        unsafe { &*self.i3cg }
+    }
+
+    /// The only repeated interior `unsafe` for the SCU block. See
+    /// [`i3c`](Self::i3c).
+    #[inline]
+    fn scu(&self) -> &'static ast1060_pac::scu::RegisterBlock {
+        // SAFETY: see `i3c`.
+        unsafe { &*self.scu }
+    }
+
+    // -------------------------------------------------------------------------
+    // SCU: per-bus reset and clock
+    // -------------------------------------------------------------------------
+
+    /// SCU050: assert this bus's controller reset.
+    pub(crate) fn core_reset_assert(&self) {
+        match self.bus {
+            0 => self
+                .scu()
+                .scu050()
+                .modify(|_, w| w.rst_i3c0ctrl().set_bit()),
+            1 => self
+                .scu()
+                .scu050()
+                .modify(|_, w| w.rst_i3c1ctrl().set_bit()),
+            2 => self
+                .scu()
+                .scu050()
+                .modify(|_, w| w.rst_i3c2ctrl().set_bit()),
+            _ => self
+                .scu()
+                .scu050()
+                .modify(|_, w| w.rst_i3c3ctrl().set_bit()),
+        };
+    }
+
+    /// SCU054: deassert this bus's controller reset (write-1-to-clear).
+    pub(crate) fn core_reset_deassert(&self) {
+        let mask = 1u32 << (8 + u32::from(self.bus));
+        self.scu()
+            .scu054()
+            .modify(|_, w| unsafe { w.scu050sys_rst_ctrl_clear_reg2().bits(mask) });
+    }
+
+    /// SCU050: assert the shared I3C register/DMA reset.
+    #[allow(dead_code)]
+    pub(crate) fn global_reset_assert(&self) {
+        self.scu()
+            .scu050()
+            .modify(|_, w| w.rst_i3cregdmactrl().set_bit());
+    }
+
+    /// SCU054: deassert the shared I3C register/DMA reset (write-1-to-clear).
+    pub(crate) fn global_reset_deassert(&self, mask: u32) {
+        self.scu()
+            .scu054()
+            .modify(|_, w| unsafe { w.scu050sys_rst_ctrl_clear_reg2().bits(mask) });
+    }
+
+    /// SCU094: ungate this bus's clock (write-1-to-clear stop bit).
+    pub(crate) fn clock_on(&self) {
+        let mask = 1u32 << (8 + u32::from(self.bus));
+        self.scu()
+            .scu094()
+            .modify(|_, w| unsafe { w.scu090clk_stop_ctrl_clear_reg_set2().bits(mask) });
+    }
+
+    /// SCU004: hardware revision ID.
+    pub(crate) fn hw_rev_id(&self) -> u32 {
+        self.scu().scu004().read().hw_rev_id().bits().into()
+    }
+
+    // -------------------------------------------------------------------------
+    // I3C-global: this bus's reg0/reg1 pair
+    // -------------------------------------------------------------------------
+
+    /// I3CG reg0: raw read.
+    pub(crate) fn i3cg_read_reg0(&self) -> u32 {
+        i3cg_reg0!(self, read().bits())
+    }
+
+    /// I3CG reg0: raw write.
+    pub(crate) fn i3cg_write_reg0(&self, val: u32) {
+        i3cg_reg0!(self, write(|w| unsafe { w.bits(val) }));
+    }
+
+    /// I3CG reg1: raw read.
+    pub(crate) fn i3cg_read_reg1(&self) -> u32 {
+        i3cg_reg1!(self, read().bits())
+    }
+
+    /// I3CG reg1: program act-mode 1, instance id = bus, and the bring-up
+    /// static address.
+    pub(crate) fn i3cg_program_reg1(&self, static_addr: u8) {
+        let bus = self.bus;
+        i3cg_reg1!(
+            self,
+            write(|w| unsafe {
+                w.actmode()
+                    .bits(1)
+                    .instid()
+                    .bits(bus)
+                    .staticaddr()
+                    .bits(static_addr)
+            })
+        );
+    }
+
+    /// I3CG reg1: read-modify-write setting `mask` bits.
+    pub(crate) fn i3cg_reg1_set_bits(&self, mask: u32) {
+        i3cg_reg1!(self, modify(|r, w| unsafe { w.bits(r.bits() | mask) }));
+    }
+
+    /// I3CG reg1: read-modify-write clearing `mask` bits.
+    pub(crate) fn i3cg_reg1_clear_bits(&self, mask: u32) {
+        i3cg_reg1!(self, modify(|r, w| unsafe { w.bits(r.bits() & !mask) }));
+    }
+
+    /// I3CG reg1: absolute write via read-modify-write (preserves the
+    /// reference's RMW bus access pattern).
+    pub(crate) fn i3cg_reg1_overwrite(&self, val: u32) {
+        i3cg_reg1!(self, modify(|_r, w| unsafe { w.bits(val) }));
+    }
+
+    // -------------------------------------------------------------------------
+    // I3CD000: device control
+    // -------------------------------------------------------------------------
+
+    /// I3CD000: set/clear automatic hot-join NACK.
+    pub(crate) fn set_hot_join_nack(&self, on: bool) {
+        self.i3c().i3cd000().modify(|_, w| {
+            if on {
+                w.hot_join_ack_nack_ctrl().set_bit()
+            } else {
+                w.hot_join_ack_nack_ctrl().clear_bit()
+            }
+        });
+    }
+
+    /// I3CD000: is the controller enable bit set?
+    pub(crate) fn controller_enabled(&self) -> bool {
+        self.i3c().i3cd000().read().enbl_i3cctrl().bit_is_set()
+    }
+
+    /// I3CD000: clear the controller enable bit.
+    pub(crate) fn disable_controller(&self) {
+        self.i3c()
+            .i3cd000()
+            .modify(|_, w| w.enbl_i3cctrl().clear_bit());
+    }
+
+    /// I3CD000: enable in primary (master) role — include broadcast address.
+    pub(crate) fn enable_controller_primary(&self) {
+        self.i3c().i3cd000().modify(|_, w| {
+            w.i3cbroadcast_addr_include()
+                .set_bit()
+                .enbl_i3cctrl()
+                .set_bit()
+        });
+    }
+
+    /// I3CD000: enable in secondary (target) role — IBI payload on, I2C/I3C
+    /// mode adaption off.
+    pub(crate) fn enable_controller_secondary(&self) {
+        self.i3c().i3cd000().modify(|_, w| {
+            w.enbl_adaption_of_i2ci3cmode()
+                .clear_bit()
+                .ibipayloaden()
+                .set_bit()
+                .enbl_i3cctrl()
+                .set_bit()
+        });
+    }
+
+    /// I3CD000: resume from a halted transfer state.
+    pub(crate) fn resume(&self) {
+        self.i3c().i3cd000().modify(|_, w| w.i3cresume().set_bit());
+    }
+
+    /// I3CD000: abort the current transfer (software halt request).
+    pub(crate) fn abort(&self) {
+        self.i3c().i3cd000().modify(|_, w| w.i3cabort().set_bit());
+    }
+
+    /// I3CD000: program the IBI mandatory data byte.
+    pub(crate) fn set_ibi_mdb(&self, mdb: u8) {
+        self.i3c()
+            .i3cd000()
+            .modify(|_, w| unsafe { w.mdb().bits(mdb) });
+    }
+
+    // -------------------------------------------------------------------------
+    // I3CD004 / I3CD008: device address & capability
+    // -------------------------------------------------------------------------
+
+    /// I3CD004: program the secondary-role static address (and mark valid).
+    pub(crate) fn program_secondary_static_addr(&self, addr: u8) {
+        self.i3c()
+            .i3cd004()
+            .write(|w| unsafe { w.dev_static_addr().bits(addr).static_addr_valid().set_bit() });
+    }
+
+    /// I3CD004: program the primary-role dynamic address (and mark valid).
+    pub(crate) fn program_primary_dynamic_addr(&self, addr: u8) {
+        self.i3c().i3cd004().write(|w| unsafe {
+            w.dev_dynamic_addr()
+                .bits(addr)
+                .dynamic_addr_valid()
+                .set_bit()
+        });
+    }
+
+    /// I3CD004: currently assigned dynamic address.
+    pub(crate) fn dynamic_addr(&self) -> u8 {
+        self.i3c().i3cd004().read().dev_dynamic_addr().bits()
+    }
+
+    /// I3CD004: is the dynamic address valid?
+    pub(crate) fn dynamic_addr_valid(&self) -> bool {
+        self.i3c().i3cd004().read().dynamic_addr_valid().bit()
+    }
+
+    /// I3CD008: does the device advertise hot-join capability?
+    pub(crate) fn hj_capable(&self) -> bool {
+        self.i3c().i3cd008().read().slvhjcap().bit()
+    }
+
+    // -------------------------------------------------------------------------
+    // Command / response / data ports
+    // -------------------------------------------------------------------------
+
+    /// I3CD00C: push one word into the command queue.
+    pub(crate) fn push_cmd(&self, val: u32) {
+        self.i3c().i3cd00c().write(|w| unsafe { w.bits(val) });
+    }
+
+    /// I3CD010: pop one word from the response queue.
+    pub(crate) fn pop_response(&self) -> u32 {
+        self.i3c().i3cd010().read().bits()
+    }
+
+    /// I3CD014: write `bytes` into the TX FIFO (LE words; tail zero-padded).
+    pub(crate) fn tx_fifo_write(&self, bytes: &[u8]) {
+        let mut chunks = bytes.chunks_exact(4);
+        for chunk in &mut chunks {
+            let word = u32::from_le_bytes([chunk[0], chunk[1], chunk[2], chunk[3]]);
+            self.i3c()
+                .i3cd014()
+                .write(|w| unsafe { w.tx_data_port().bits(word) });
+        }
+
+        let rem = chunks.remainder();
+        if !rem.is_empty() {
+            let mut tmp = [0u8; 4];
+            tmp[..rem.len()].copy_from_slice(rem);
+            let word = u32::from_le_bytes(tmp);
+            self.i3c()
+                .i3cd014()
+                .write(|w| unsafe { w.tx_data_port().bits(word) });
+        }
+    }
+
+    /// I3CD014: read `out.len()` bytes from the RX FIFO (LE words).
+    pub(crate) fn rx_fifo_read(&self, out: &mut [u8]) {
+        Self::fifo_read(|| self.i3c().i3cd014().read().rx_data_port().bits(), out);
+    }
+
+    /// I3CD014: discard `len` bytes from the RX FIFO.
+    pub(crate) fn rx_fifo_drain(&self, len: usize) {
+        Self::fifo_drain(|| self.i3c().i3cd014().read().rx_data_port().bits(), len);
+    }
+
+    /// I3CD018: pop one word from the IBI queue.
+    pub(crate) fn ibi_fifo_pop(&self) -> u32 {
+        self.i3c().i3cd018().read().bits()
+    }
+
+    /// I3CD018: read `out.len()` bytes from the IBI queue (LE words).
+    pub(crate) fn ibi_fifo_read(&self, out: &mut [u8]) {
+        Self::fifo_read(|| self.i3c().i3cd018().read().bits(), out);
+    }
+
+    /// I3CD018: discard `len` bytes from the IBI queue.
+    pub(crate) fn ibi_fifo_drain(&self, len: usize) {
+        Self::fifo_drain(|| self.i3c().i3cd018().read().bits(), len);
+    }
+
+    /// Word-at-a-time FIFO scatter helper (shared by RX/IBI reads).
+    fn fifo_read<F: FnMut() -> u32>(mut read_word: F, out: &mut [u8]) {
+        let mut chunks = out.chunks_exact_mut(4);
+        for chunk in &mut chunks {
+            let val = read_word();
+            chunk.copy_from_slice(&val.to_le_bytes());
+        }
+
+        let rem = chunks.into_remainder();
+        if !rem.is_empty() {
+            let val = read_word();
+            let bytes = val.to_le_bytes();
+            rem.copy_from_slice(&bytes[..rem.len()]);
+        }
+    }
+
+    /// Word-at-a-time FIFO discard helper (shared by RX/IBI drains).
+    fn fifo_drain<F: FnMut() -> u32>(mut read_word: F, len: usize) {
+        let nwords = (len + 3) >> 2;
+        for _ in 0..nwords {
+            let _ = read_word();
+        }
+    }
+
+    // -------------------------------------------------------------------------
+    // Queue thresholds
+    // -------------------------------------------------------------------------
+
+    /// I3CD01C: program the IBI data threshold.
+    pub(crate) fn set_ibi_data_threshold(&self, val: u8) {
+        self.i3c()
+            .i3cd01c()
+            .write(|w| unsafe { w.ibidata_threshold_value().bits(val) });
+    }
+
+    /// I3CD01C: program the response-buffer threshold.
+    pub(crate) fn set_resp_buf_threshold(&self, val: u8) {
+        self.i3c()
+            .i3cd01c()
+            .modify(|_, w| unsafe { w.response_buffer_threshold_value().bits(val) });
+    }
+
+    /// I3CD020: program the RX-buffer threshold.
+    pub(crate) fn set_rx_buf_threshold(&self, val: u8) {
+        self.i3c()
+            .i3cd020()
+            .modify(|_, w| unsafe { w.rx_buffer_threshold_value().bits(val) });
+    }
+
+    // -------------------------------------------------------------------------
+    // IBI MR/SIR reject masks
+    // -------------------------------------------------------------------------
+
+    /// I3CD02C: write the master-request reject mask.
+    pub(crate) fn write_mr_reject(&self, val: u32) {
+        self.i3c().i3cd02c().write(|w| unsafe { w.bits(val) });
+    }
+
+    /// I3CD030: read the SIR reject mask.
+    pub(crate) fn read_sir_reject(&self) -> u32 {
+        self.i3c().i3cd030().read().bits()
+    }
+
+    /// I3CD030: write the SIR reject mask.
+    pub(crate) fn write_sir_reject(&self, val: u32) {
+        self.i3c().i3cd030().write(|w| unsafe { w.bits(val) });
+    }
+
+    // -------------------------------------------------------------------------
+    // I3CD034: reset control
+    // -------------------------------------------------------------------------
+
+    /// I3CD034: assert every queue/buffer/core software reset at once.
+    pub(crate) fn assert_all_queue_resets(&self) {
+        self.i3c().i3cd034().write(|w| {
+            w.ibiqueue_sw_rst()
+                .set_bit()
+                .rx_buffer_sw_rst()
+                .set_bit()
+                .tx_buffer_sw_rst()
+                .set_bit()
+                .response_queue_sw_rst()
+                .set_bit()
+                .cmd_queue_sw_rst()
+                .set_bit()
+                .core_sw_rst()
+                .set_bit()
+        });
+    }
+
+    /// I3CD034: raw write (selected reset bits).
+    pub(crate) fn write_reset_ctrl(&self, val: u32) {
+        self.i3c().i3cd034().write(|w| unsafe { w.bits(val) });
+    }
+
+    /// I3CD034: raw read (0 once all resets have self-cleared).
+    pub(crate) fn read_reset_ctrl(&self) -> u32 {
+        self.i3c().i3cd034().read().bits()
+    }
+
+    // -------------------------------------------------------------------------
+    // I3CD038: slave event control
+    // -------------------------------------------------------------------------
+
+    /// I3CD038: raw read.
+    pub(crate) fn read_slv_event_ctrl(&self) -> u32 {
+        self.i3c().i3cd038().read().bits()
+    }
+
+    /// I3CD038: raw write.
+    pub(crate) fn write_slv_event_ctrl(&self, val: u32) {
+        self.i3c().i3cd038().write(|w| unsafe { w.bits(val) });
+    }
+
+    /// I3CD038: request a hot-join (secondary role, no dynamic address yet).
+    pub(crate) fn raise_hot_join_request(&self) {
+        self.write_slv_event_ctrl(super::constants::SLV_EVENT_CTRL_HJ_REQ);
+    }
+
+    // -------------------------------------------------------------------------
+    // Interrupt status / enables
+    // -------------------------------------------------------------------------
+
+    /// I3CD03C: read the interrupt status.
+    pub(crate) fn read_intr_status(&self) -> u32 {
+        self.i3c().i3cd03c().read().bits()
+    }
+
+    /// I3CD03C: clear the given interrupt-status bits (write-1-to-clear).
+    pub(crate) fn clear_intr_status(&self, mask: u32) {
+        self.i3c().i3cd03c().write(|w| unsafe { w.bits(mask) });
+    }
+
+    /// I3CD040/I3CD044: enable the primary-role interrupt set
+    /// (transfer error + response ready), status and signal.
+    pub(crate) fn enable_master_irqs(&self) {
+        self.i3c().i3cd040().write(|w| {
+            w.transfererrstaten()
+                .set_bit()
+                .respreadystatintren()
+                .set_bit()
+        });
+
+        self.i3c().i3cd044().write(|w| {
+            w.transfererrsignalen()
+                .set_bit()
+                .respreadysignalintren()
+                .set_bit()
+        });
+    }
+
+    /// I3CD040/I3CD044: enable the secondary-role interrupt set
+    /// (transfer error, response ready, CCC update, DA assignment, IBI
+    /// update, read request), status and signal.
+    pub(crate) fn enable_target_irqs(&self) {
+        self.i3c().i3cd040().write(|w| {
+            w.transfererrstaten()
+                .set_bit()
+                .respreadystatintren()
+                .set_bit()
+                .cccupdatedstaten()
+                .set_bit()
+                .dynaddrassgnstaten()
+                .set_bit()
+                .ibiupdatedstaten()
+                .set_bit()
+                .readreqrecvstaten()
+                .set_bit()
+        });
+
+        self.i3c().i3cd044().write(|w| {
+            w.transfererrsignalen()
+                .set_bit()
+                .respreadysignalintren()
+                .set_bit()
+                .cccupdatedsignalen()
+                .set_bit()
+                .dynaddrassgnsignalen()
+                .set_bit()
+                .ibiupdatedsignalen()
+                .set_bit()
+                .readreqrecvsignalen()
+                .set_bit()
+        });
+    }
+
+    /// I3CD040/I3CD044: additionally enable the IBI threshold interrupt,
+    /// status and signal.
+    pub(crate) fn enable_ibi_thld_irq(&self) {
+        self.i3c()
+            .i3cd040()
+            .modify(|_, w| w.ibithldstaten().set_bit());
+        self.i3c()
+            .i3cd044()
+            .modify(|_, w| w.ibithldsignalen().set_bit());
+    }
+
+    /// I3CD040/I3CD044: mask the master transfer-completion interrupt sources
+    /// (response ready + transfer error), status and signal.
+    ///
+    /// Called by the ISR (flag-and-defer): the response queue stays non-empty
+    /// until the polling thread drains it, so the level-style status would
+    /// refire the line forever if left enabled. The thread re-enables via
+    /// [`unmask_master_xfer_irqs`](Self::unmask_master_xfer_irqs) after
+    /// draining. `modify` (not `write`) so the IBI-threshold enables are
+    /// untouched.
+    pub(crate) fn mask_master_xfer_irqs(&self) {
+        self.i3c().i3cd040().modify(|_, w| {
+            w.transfererrstaten()
+                .clear_bit()
+                .respreadystatintren()
+                .clear_bit()
+        });
+        self.i3c().i3cd044().modify(|_, w| {
+            w.transfererrsignalen()
+                .clear_bit()
+                .respreadysignalintren()
+                .clear_bit()
+        });
+    }
+
+    /// I3CD040/I3CD044: re-enable the master transfer-completion interrupt
+    /// sources after the thread has drained the response queue. Counterpart
+    /// of [`mask_master_xfer_irqs`](Self::mask_master_xfer_irqs).
+    pub(crate) fn unmask_master_xfer_irqs(&self) {
+        self.i3c().i3cd040().modify(|_, w| {
+            w.transfererrstaten()
+                .set_bit()
+                .respreadystatintren()
+                .set_bit()
+        });
+        self.i3c().i3cd044().modify(|_, w| {
+            w.transfererrsignalen()
+                .set_bit()
+                .respreadysignalintren()
+                .set_bit()
+        });
+    }
+
+    /// I3CD040: read the interrupt status-enable mask (debug).
+    #[allow(dead_code)]
+    pub(crate) fn read_intr_status_en(&self) -> u32 {
+        self.i3c().i3cd040().read().bits()
+    }
+
+    /// I3CD044: read the interrupt signal-enable mask (debug).
+    #[allow(dead_code)]
+    pub(crate) fn read_intr_signal_en(&self) -> u32 {
+        self.i3c().i3cd044().read().bits()
+    }
+
+    // -------------------------------------------------------------------------
+    // Queue / transfer status
+    // -------------------------------------------------------------------------
+
+    /// I3CD04C: number of entries in the response buffer.
+    pub(crate) fn resp_buf_level(&self) -> usize {
+        self.i3c().i3cd04c().read().respbufblr().bits() as usize
+    }
+
+    /// I3CD04C: number of pending IBI status entries.
+    pub(crate) fn ibi_status_count(&self) -> u8 {
+        self.i3c().i3cd04c().read().ibistatuscnt().bits()
+    }
+
+    /// I3CD054: current transfer state machine status.
+    pub(crate) fn xfer_status(&self) -> u8 {
+        self.i3c().i3cd054().read().cmtfrstatus().bits()
+    }
+
+    /// I3CD05C: device address table depth.
+    pub(crate) fn dat_depth(&self) -> u16 {
+        self.i3c().i3cd05c().read().devaddrtabledepth().bits()
+    }
+
+    // -------------------------------------------------------------------------
+    // PID / characteristics
+    // -------------------------------------------------------------------------
+
+    /// I3CD070: program the MIPI manufacturer ID (and select PID[31:0] as
+    /// the instance value, not DCR).
+    pub(crate) fn set_pid_mfg_id(&self, id: u16) {
+        self.i3c()
+            .i3cd070()
+            .write(|w| unsafe { w.slvmipimfgid().bits(id).slvpiddcr().clear_bit() });
+    }
+
+    /// I3CD074: program the PID instance value word.
+    pub(crate) fn write_slv_pid_value(&self, val: u32) {
+        self.i3c().i3cd074().write(|w| unsafe { w.bits(val) });
+    }
+
+    /// I3CD078: read the slave characteristics register.
+    pub(crate) fn read_slv_char_ctrl(&self) -> u32 {
+        self.i3c().i3cd078().read().bits()
+    }
+
+    /// I3CD07C: read the max write/read length register (MRL in bits 31:16,
+    /// MWL in bits 15:0; updated by the bus master via SETMRL/SETMWL).
+    pub(crate) fn read_slv_max_len(&self) -> u32 {
+        self.i3c().i3cd07c().read().bits()
+    }
+
+    /// I3CD078: write the slave characteristics register.
+    pub(crate) fn write_slv_char_ctrl(&self, val: u32) {
+        self.i3c().i3cd078().write(|w| unsafe { w.bits(val) });
+    }
+
+    // -------------------------------------------------------------------------
+    // Misc control
+    // -------------------------------------------------------------------------
+
+    /// I3CD08C: raise a slave interrupt request (SIR).
+    pub(crate) fn raise_sir(&self) {
+        self.i3c().i3cd08c().write(|w| w.sir().set_bit());
+    }
+
+    /// I3CD0B0: program the device operation mode (0 = master, 1 = slave).
+    pub(crate) fn set_dev_op_mode(&self, mode: u8) {
+        self.i3c()
+            .i3cd0b0()
+            .modify(|_, w| unsafe { w.dev_op_mode().bits(mode) });
+    }
+
+    // -------------------------------------------------------------------------
+    // Clock / timing
+    // -------------------------------------------------------------------------
+
+    /// I3CD0BC: program the I2C Fast-mode SCL high/low counts.
+    pub(crate) fn set_i2c_fm_timing(&self, hi: u16, lo: u16) {
+        self.i3c()
+            .i3cd0bc()
+            .write(|w| unsafe { w.i2cfmhcnt().bits(hi).i2cfmlcnt().bits(lo) });
+    }
+
+    /// I3CD0C0: program the I2C Fast-mode-Plus SCL high/low counts.
+    pub(crate) fn set_i2c_fmp_timing(&self, hi: u8, lo: u16) {
+        self.i3c()
+            .i3cd0c0()
+            .write(|w| unsafe { w.i2cfmphcnt().bits(hi).i2cfmplcnt().bits(lo) });
+    }
+
+    /// I3CD0B4: program the I3C open-drain SCL high/low counts.
+    pub(crate) fn set_od_timing(&self, hi: u8, lo: u8) {
+        self.i3c()
+            .i3cd0b4()
+            .write(|w| unsafe { w.i3codhcnt().bits(hi).i3codlcnt().bits(lo) });
+    }
+
+    /// I3CD0B8: program the I3C push-pull SCL high/low counts.
+    pub(crate) fn set_pp_timing(&self, hi: u8, lo: u8) {
+        self.i3c()
+            .i3cd0b8()
+            .write(|w| unsafe { w.i3cpphcnt().bits(hi).i3cpplcnt().bits(lo) });
+    }
+
+    /// I3CD0D0: read the SDA hold/debounce register.
+    pub(crate) fn read_sda_hold(&self) -> u32 {
+        self.i3c().i3cd0d0().read().bits()
+    }
+
+    /// I3CD0D0: write the SDA hold/debounce register.
+    pub(crate) fn write_sda_hold(&self, val: u32) {
+        self.i3c().i3cd0d0().write(|w| unsafe { w.bits(val) });
+    }
+
+    /// I3CD0D4: program the bus-free timing register.
+    pub(crate) fn write_bus_free_timing(&self, val: u32) {
+        self.i3c().i3cd0d4().write(|w| unsafe { w.bits(val) });
+    }
+
+    /// I3CD0D4: IBI-free wait window in core-clock cycles.
+    pub(crate) fn ibi_free_cycles(&self) -> u32 {
+        self.i3c().i3cd0d4().read().i3cibifree().bits().into()
+    }
+
+    // -------------------------------------------------------------------------
+    // Device address table (I3CD280..I3CD29C)
+    // -------------------------------------------------------------------------
+
+    /// DAT[pos]: raw read.
+    pub(crate) fn dat_read(&self, pos: usize) -> u32 {
+        dat_reg!(self, pos, read().bits())
+    }
+
+    /// DAT[pos]: raw write.
+    pub(crate) fn dat_write_raw(&self, pos: usize, val: u32) {
+        dat_reg!(self, pos, write(|w| unsafe { w.bits(val) }));
+    }
+
+    /// DAT[pos]: reject SIR and master requests (detached/idle slot).
+    pub(crate) fn dat_set_reject(&self, pos: usize) {
+        dat_reg!(
+            self,
+            pos,
+            write(|w| w.sirreject().set_bit().mrreject().set_bit())
+        );
+    }
+
+    /// DAT[pos]: program a device's dynamic address (with parity bit) while
+    /// keeping SIR/MR rejected until IBIs are explicitly enabled.
+    pub(crate) fn dat_program_addr(&self, pos: usize, addr_with_parity: u8) {
+        dat_reg!(
+            self,
+            pos,
+            write(|w| unsafe {
+                w.sirreject()
+                    .set_bit()
+                    .mrreject()
+                    .set_bit()
+                    .devdynamicaddr()
+                    .bits(addr_with_parity)
+            })
+        );
+    }
+}
diff --git a/target/ast10x0/peripherals/i3c/types.rs b/target/ast10x0/peripherals/i3c/types.rs
new file mode 100644
index 00000000..201fa976
--- /dev/null
+++ b/target/ast10x0/peripherals/i3c/types.rs
@@ -0,0 +1,413 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C core types
+//!
+//! This module contains the core data types used throughout the I3C subsystem.
+
+use core::sync::atomic::{AtomicBool, Ordering};
+
+// =============================================================================
+// Speed Enumerations
+// =============================================================================
+
+/// I3C transfer speed modes
+#[repr(u32)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum SpeedI3c {
+    /// SDR0 - Standard Data Rate 0 (12.5 `MHz` max)
+    Sdr0 = 0x0,
+    /// SDR1 - Standard Data Rate 1 (8 `MHz` max)
+    Sdr1 = 0x1,
+    /// SDR2 - Standard Data Rate 2 (6 `MHz` max)
+    Sdr2 = 0x2,
+    /// SDR3 - Standard Data Rate 3 (4 `MHz` max)
+    Sdr3 = 0x3,
+    /// SDR4 - Standard Data Rate 4 (2 `MHz` max)
+    Sdr4 = 0x4,
+    /// HDR-TS - High Data Rate Ternary Symbol
+    HdrTs = 0x5,
+    /// HDR-DDR - High Data Rate Double Data Rate
+    HdrDdr = 0x6,
+    /// I2C FM as I3C fallback
+    I2cFmAsI3c = 0x7,
+}
+
+/// I2C transfer speed modes
+#[repr(u32)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum SpeedI2c {
+    /// Fast Mode (400 kHz)
+    Fm = 0x0,
+    /// Fast Mode Plus (1 `MHz`)
+    Fmp = 0x1,
+}
+
+// =============================================================================
+// Transaction ID
+// =============================================================================
+
+/// Transaction ID for tracking transfers
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum Tid {
+    /// Target IBI transaction
+    TargetIbi = 0x1,
+    /// Target read data transaction
+    TargetRdData = 0x2,
+    /// Target master write transaction
+    TargetMasterWr = 0x8,
+    /// Target master default transaction
+    TargetMasterDef = 0xF,
+}
+
+// =============================================================================
+// Transfer Status
+// =============================================================================
+
+/// I3C operation status
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum I3cStatus {
+    /// Operation completed successfully
+    Ok,
+    /// Operation timed out
+    Timeout,
+    /// Bus is busy
+    Busy,
+    /// Operation is pending
+    /// Invalid operation or parameter
+    Invalid,
+    /// Pending status
+    Pending,
+}
+
+// =============================================================================
+// Transfer Structures
+// =============================================================================
+
+/// I3C command descriptor
+#[derive(Debug)]
+pub struct I3cCmd<'a> {
+    /// Lower 32 bits of command
+    pub cmd_lo: u32,
+    /// Upper 32 bits of command
+    pub cmd_hi: u32,
+    /// Transmit data buffer (optional)
+    pub tx: Option<&'a [u8]>,
+    /// Receive data buffer (optional)
+    pub rx: Option<&'a mut [u8]>,
+    /// Transmit length in bytes
+    pub tx_len: u32,
+    /// Receive length in bytes
+    pub rx_len: u32,
+    /// Return code from hardware
+    pub ret: i32,
+}
+
+impl I3cCmd<'_> {
+    /// Create a new command with default values
+    #[must_use]
+    pub const fn new() -> Self {
+        Self {
+            cmd_lo: 0,
+            cmd_hi: 0,
+            tx: None,
+            rx: None,
+            tx_len: 0,
+            rx_len: 0,
+            ret: 0,
+        }
+    }
+}
+
+impl Default for I3cCmd<'_> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+/// I3C message descriptor
+pub struct I3cMsg<'a> {
+    /// Data buffer.
+    ///
+    /// **Consumed by the transfer**: `priv_xfer_build_cmds` moves the reborrow
+    /// into the command descriptor (`Option::take`), so this is `None` after a
+    /// transfer. Read the result through `actual_len`/`num_xfer`; the caller
+    /// still owns the underlying buffer.
+    pub buf: Option<&'a mut [u8]>,
+    /// Actual bytes transferred
+    pub actual_len: u32,
+    /// Number of transfers completed
+    pub num_xfer: u32,
+    /// Message flags (read/write/stop)
+    pub flags: u8,
+    /// HDR mode
+    pub hdr_mode: u8,
+    /// HDR command mode
+    pub hdr_cmd_mode: u8,
+}
+
+impl I3cMsg<'_> {
+    /// Create a new message with default values
+    #[must_use]
+    pub const fn new() -> Self {
+        Self {
+            buf: None,
+            actual_len: 0,
+            num_xfer: 0,
+            flags: 0,
+            hdr_mode: 0,
+            hdr_cmd_mode: 0,
+        }
+    }
+
+    /// Check if this is a read message
+    #[inline]
+    #[must_use]
+    pub const fn is_read(&self) -> bool {
+        (self.flags & super::constants::I3C_MSG_READ) != 0
+    }
+
+    /// Check if this message should terminate with STOP
+    #[inline]
+    #[must_use]
+    pub const fn has_stop(&self) -> bool {
+        (self.flags & super::constants::I3C_MSG_STOP) != 0
+    }
+}
+
+impl Default for I3cMsg<'_> {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+/// I3C transfer descriptor with multiple commands
+pub struct I3cXfer<'cmds, 'buf> {
+    /// Array of commands for this transfer
+    pub cmds: &'cmds mut [I3cCmd<'buf>],
+    /// Return code from transfer
+    pub ret: i32,
+}
+
+impl<'cmds, 'buf> I3cXfer<'cmds, 'buf> {
+    /// Create a new transfer with the given commands
+    #[must_use]
+    pub fn new(cmds: &'cmds mut [I3cCmd<'buf>]) -> Self {
+        Self { cmds, ret: 0 }
+    }
+
+    /// Get the number of commands in this transfer
+    #[inline]
+    #[must_use]
+    pub fn ncmds(&self) -> usize {
+        self.cmds.len()
+    }
+}
+
+// =============================================================================
+// Legacy I2C Operations
+// =============================================================================
+
+/// One leg of a legacy-I2C transaction on the I3C bus.
+///
+/// Mirrors `embedded_hal::i2c::Operation` without pulling that type into the
+/// hardware trait. Consecutive operations are joined by repeated START; the
+/// last one ends with STOP.
+pub enum I2cOp<'a> {
+    /// Write the bytes to the device.
+    Write(&'a [u8]),
+    /// Read into the buffer (filled completely on success).
+    Read(&'a mut [u8]),
+}
+
+// =============================================================================
+// Device Identification
+// =============================================================================
+
+/// I3C Provisional ID (48-bit)
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub struct I3cPid(pub u64);
+
+impl I3cPid {
+    /// Create a new PID from raw value
+    #[must_use]
+    pub const fn new(pid: u64) -> Self {
+        Self(pid)
+    }
+
+    /// Get the manufacturer ID (bits 47:33)
+    #[must_use]
+    pub const fn manuf_id(self) -> u16 {
+        ((self.0 >> 33) & 0x1FFF) as u16
+    }
+
+    /// Check if lower 32 bits are random (bit 32)
+    #[must_use]
+    pub const fn has_random_lower32(self) -> bool {
+        (self.0 & (1u64 << 32)) != 0
+    }
+
+    /// Get raw PID value
+    #[inline]
+    #[must_use]
+    pub const fn raw(self) -> u64 {
+        self.0
+    }
+}
+
+/// I3C device identifier
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub struct I3cDeviceId {
+    /// Provisional ID
+    pub pid: I3cPid,
+}
+
+impl I3cDeviceId {
+    /// Create a new device ID from raw PID
+    #[must_use]
+    pub const fn new(pid: u64) -> Self {
+        Self { pid: I3cPid(pid) }
+    }
+}
+
+// =============================================================================
+// IBI (In-Band Interrupt) Types
+// =============================================================================
+
+/// Type of In-Band Interrupt
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum I3cIbiType {
+    /// Target-initiated interrupt
+    TargetIntr,
+    /// Controller role request
+    ControllerRoleRequest,
+    /// Hot-join request
+    HotJoin,
+    /// Workqueue callback
+    WorkqueueCb,
+}
+
+/// In-Band Interrupt descriptor
+#[derive(Clone, Copy, Debug)]
+pub struct I3cIbi<'a> {
+    /// Type of IBI
+    pub ibi_type: I3cIbiType,
+    /// Optional payload data
+    pub payload: Option<&'a [u8]>,
+}
+
+impl<'a> I3cIbi<'a> {
+    /// Create a new IBI descriptor
+    #[must_use]
+    pub const fn new(ibi_type: I3cIbiType) -> Self {
+        Self {
+            ibi_type,
+            payload: None,
+        }
+    }
+
+    /// Create an IBI with payload
+    #[must_use]
+    pub const fn with_payload(ibi_type: I3cIbiType, payload: &'a [u8]) -> Self {
+        Self {
+            ibi_type,
+            payload: Some(payload),
+        }
+    }
+
+    /// Get payload length
+    #[inline]
+    #[must_use]
+    pub fn payload_len(&self) -> u8 {
+        self.payload.map_or(0, |p| {
+            u8::try_from(p.len().min(u8::MAX as usize)).unwrap_or(u8::MAX)
+        })
+    }
+
+    /// Get first byte of payload
+    #[must_use]
+    pub fn first_byte(&self) -> Option<u8> {
+        self.payload.and_then(|p| p.first().copied())
+    }
+}
+
+// =============================================================================
+// Completion Primitive
+// =============================================================================
+
+/// Synchronization primitive for signaling completion
+pub struct Completion {
+    done: AtomicBool,
+}
+
+impl Default for Completion {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+impl Completion {
+    /// Create a new completion in non-signaled state
+    #[must_use]
+    pub const fn new() -> Self {
+        Self {
+            done: AtomicBool::new(false),
+        }
+    }
+
+    /// Reset to non-signaled state
+    #[inline]
+    pub fn reset(&self) {
+        self.done.store(false, Ordering::Release);
+    }
+
+    /// Signal completion
+    #[inline]
+    pub fn complete(&self) {
+        self.done.store(true, Ordering::Release);
+        // Wake any waiting cores
+        cortex_m::asm::sev();
+    }
+
+    /// Check if completed
+    #[inline]
+    #[must_use]
+    pub fn is_completed(&self) -> bool {
+        self.done.load(Ordering::Acquire)
+    }
+
+    /// Wait for completion with timeout.
+    ///
+    /// Returns `true` if completed, `false` if timed out.
+    ///
+    /// Delta D2 (Cooperative-Yield Bounded-Poll Device): the reference took a
+    /// `&mut D: DelayNs`; here the wait policy is the caller-injected,
+    /// type-erased `yield_fn`, invoked once per non-completing poll with an
+    /// advisory wait window in nanoseconds (1 µs, mirroring the reference's
+    /// `delay.delay_us(1)`). A bare-metal caller passes
+    /// `|_| core::hint::spin_loop()`.
+    pub fn wait_for_us(&self, timeout_us: u32, yield_fn: &mut dyn FnMut(u32)) -> bool {
+        let mut left = timeout_us;
+        while !self.is_completed() {
+            if left == 0 {
+                return false;
+            }
+            yield_fn(1_000);
+            left -= 1;
+        }
+        true
+    }
+}
+
+// =============================================================================
+// Device Kind
+// =============================================================================
+
+/// Device type on the I3C bus
+#[derive(Clone, Copy, Debug, PartialEq, Eq)]
+pub enum DevKind {
+    /// Native I3C device
+    I3c,
+    /// Legacy I2C device
+    I2c,
+}
diff --git a/target/ast10x0/peripherals/lib.rs b/target/ast10x0/peripherals/lib.rs
index be02f133..82661cb4 100644
--- a/target/ast10x0/peripherals/lib.rs
+++ b/target/ast10x0/peripherals/lib.rs
@@ -4,6 +4,7 @@
 #![no_std]
 
 pub mod i2c;
+pub mod i3c;
 pub mod scu;
 pub mod smc;
 pub mod spimonitor;
diff --git a/target/ast10x0/peripherals/scu/pinctrl.rs b/target/ast10x0/peripherals/scu/pinctrl.rs
index 7655161a..9e7de475 100644
--- a/target/ast10x0/peripherals/scu/pinctrl.rs
+++ b/target/ast10x0/peripherals/scu/pinctrl.rs
@@ -733,6 +733,74 @@ pub const PINCTRL_SPIM4_DEFAULT: &[PinctrlPin] = &[
 /// I2C communication between the two AST1060 daughter cards.
 pub const PINCTRL_I2C2: &[PinctrlPin] = &[PIN_SCU418_0, PIN_SCU418_1];
 
+// =============================================================================
+// I3C pin groups
+// =============================================================================
+//
+// The AST1060 routes each I3C bus to either a Low-Voltage (LV) pad set,
+// enabled in SCU418, or a High-Voltage (HV) pad set, enabled in SCU4B8
+// (SVD fields `EnblI3CSCLn/SDAn{LV,HV}FnPin`). Setting the bit selects the
+// I3C function on that pad.
+//
+// Naming follows the PAC instance / `BUS_NUM`, 0-based: `PINCTRL_I3C0` is PAC
+// `I3c` (bus 0), `_I3C1` is PAC `I3c1` (bus 1), etc. — matching the aspeed-rust
+// reference's `PINCTRL_HVI3Cn` groups (e.g. `PINCTRL_HVI3C2` == bus 2 == PAC
+// `I3c2`). NOTE the SVD names the pads 1-based (SDA1..SDA4); bus `n` uses the
+// SVD's `SDA(n+1)`/`SCL(n+1)` pads.
+//
+// The HV groups additionally **clear** the conflicting LV function bits on the
+// same pads (`CLR_PIN_SCU418_*`), exactly as the reference does — enabling the
+// HV pad alone without first releasing the LV pad would leave both functions
+// muxed onto it. LV groups need no such clear (HV defaults off).
+
+/// I3C bus 0 (PAC `I3c`) — LV pads: SCL/SDA on SCU418[16:17].
+pub const PINCTRL_I3C0: &[PinctrlPin] = &[PIN_SCU418_16, PIN_SCU418_17];
+/// I3C bus 1 (PAC `I3c1`) — LV pads: SCL/SDA on SCU418[18:19].
+pub const PINCTRL_I3C1: &[PinctrlPin] = &[PIN_SCU418_18, PIN_SCU418_19];
+/// I3C bus 2 (PAC `I3c2`) — LV pads: SCL/SDA on SCU418[20:21].
+pub const PINCTRL_I3C2: &[PinctrlPin] = &[PIN_SCU418_20, PIN_SCU418_21];
+/// I3C bus 3 (PAC `I3c3`) — LV pads: SCL/SDA on SCU418[22:23].
+pub const PINCTRL_I3C3: &[PinctrlPin] = &[PIN_SCU418_22, PIN_SCU418_23];
+
+/// I3C bus 0 (PAC `I3c`) — HV pads: SCU4B8[8:9], clearing LV SCU418[8:9],[16:17].
+pub const PINCTRL_HVI3C0: &[PinctrlPin] = &[
+    CLR_PIN_SCU418_8,
+    CLR_PIN_SCU418_9,
+    CLR_PIN_SCU418_16,
+    CLR_PIN_SCU418_17,
+    PIN_SCU4B8_8,
+    PIN_SCU4B8_9,
+];
+/// I3C bus 1 (PAC `I3c1`) — HV pads: SCU4B8[10:11], clearing LV SCU418[10:11],[18:19].
+pub const PINCTRL_HVI3C1: &[PinctrlPin] = &[
+    CLR_PIN_SCU418_10,
+    CLR_PIN_SCU418_11,
+    CLR_PIN_SCU418_18,
+    CLR_PIN_SCU418_19,
+    PIN_SCU4B8_10,
+    PIN_SCU4B8_11,
+];
+/// I3C bus 2 (PAC `I3c2`) — HV pads: SCU4B8[12:13], clearing LV SCU418[12:13],[20:21].
+/// This is the bus/pad set the AST1060 Test Harness wires for I3C, and the one
+/// the aspeed-rust EVB tests (`PINCTRL_HVI3C2`) use.
+pub const PINCTRL_HVI3C2: &[PinctrlPin] = &[
+    CLR_PIN_SCU418_12,
+    CLR_PIN_SCU418_13,
+    CLR_PIN_SCU418_20,
+    CLR_PIN_SCU418_21,
+    PIN_SCU4B8_12,
+    PIN_SCU4B8_13,
+];
+/// I3C bus 3 (PAC `I3c3`) — HV pads: SCU4B8[14:15], clearing LV SCU418[14:15],[22:23].
+pub const PINCTRL_HVI3C3: &[PinctrlPin] = &[
+    CLR_PIN_SCU418_14,
+    CLR_PIN_SCU418_15,
+    CLR_PIN_SCU418_22,
+    CLR_PIN_SCU418_23,
+    PIN_SCU4B8_14,
+    PIN_SCU4B8_15,
+];
+
 /// Macro to safely modify a register bit (set or clear).
 macro_rules! modify_reg {
     ($reg:expr, $bit:expr, $clear:expr) => {{
diff --git a/target/ast10x0/tests/peripherals/i3c/i3c_init/BUILD.bazel b/target/ast10x0/tests/peripherals/i3c/i3c_init/BUILD.bazel
new file mode 100644
index 00000000..8be8d5d3
--- /dev/null
+++ b/target/ast10x0/tests/peripherals/i3c/i3c_init/BUILD.bazel
@@ -0,0 +1,79 @@
+# Licensed under the Apache-2.0 license
+# SPDX-License-Identifier: Apache-2.0
+
+load("@pigweed//pw_kernel/tooling:system_image.bzl", "system_image", "system_image_test")
+load("@pigweed//pw_kernel/tooling:target_codegen.bzl", "target_codegen")
+load("@pigweed//pw_kernel/tooling:target_linker_script.bzl", "target_linker_script")
+load("@pigweed//pw_kernel/tooling/panic_detector:rust_binary_no_panics_test.bzl", "rust_binary_no_panics_test")
+load("@rules_rust//rust:defs.bzl", "rust_binary")
+load("//target/ast10x0:defs.bzl", "TARGET_COMPATIBLE_WITH")
+
+system_image(
+    name = "i3c",
+    kernel = ":target",
+    platform = "//target/ast10x0",
+    system_config = ":system_config",
+    tags = ["kernel"],
+    userspace = False,
+)
+
+system_image_test(
+    name = "i3c_init_test",
+    image = ":i3c",
+    tags = ["hardware"],
+    target_compatible_with = select({
+        "//target/ast10x0:qemu_enabled": ["@platforms//:incompatible"],
+        "//conditions:default": [],
+    }),
+)
+
+rust_binary_no_panics_test(
+    name = "no_panics_test",
+    binary = ":i3c",
+    tags = ["kernel"],
+)
+
+filegroup(
+    name = "system_config",
+    srcs = ["system.json5"],
+)
+
+target_codegen(
+    name = "codegen",
+    arch = "@pigweed//pw_kernel/arch/arm_cortex_m:arch_arm_cortex_m",
+    system_config = ":system_config",
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+)
+
+target_linker_script(
+    name = "linker_script",
+    system_config = ":system_config",
+    tags = ["kernel"],
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+    template = "//target/ast10x0:linker_script_template",
+)
+
+rust_binary(
+    name = "target",
+    srcs = ["target.rs"],
+    edition = "2024",
+    tags = ["kernel"],
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+    deps = [
+        ":codegen",
+        ":linker_script",
+        "//target/ast10x0:config",
+        "//target/ast10x0:entry",
+        "//target/ast10x0/board:ast10x0_board",
+        "//target/ast10x0/peripherals",
+        "@ast1060_pac",
+        "@pigweed//pw_kernel/arch/arm_cortex_m:arch_arm_cortex_m",
+        "@pigweed//pw_kernel/kernel",
+        "@pigweed//pw_kernel/subsys/console:console_backend",
+        "@pigweed//pw_kernel/target:target_common",
+        "@pigweed//pw_log/rust:pw_log",
+        "@pigweed//pw_status/rust:pw_status",
+        "@rust_crates//:cortex-m",
+        "@rust_crates//:cortex-m-semihosting",
+    ],
+)
diff --git a/target/ast10x0/tests/peripherals/i3c/i3c_init/README.md b/target/ast10x0/tests/peripherals/i3c/i3c_init/README.md
new file mode 100644
index 00000000..cc31d8d5
--- /dev/null
+++ b/target/ast10x0/tests/peripherals/i3c/i3c_init/README.md
@@ -0,0 +1,17 @@
+# AST10x0 I3C init smoke test
+
+Mirrors `tests/peripherals/i2c/i2c_init`. Brings up the I3C controller via the
+`ast10x0_peripherals::i3c` driver (ported from `aspeed-rust/src/i3c/`; see
+`target/ast10x0/peripherals/i3c/plans/goal.md`) and verifies the init-time
+hardware state.
+
+What runs where:
+
+- **Build + `no_panics_test`** (`--config=virt_ast10x0`, kernel tag): the binary
+  must compile and be panic-free. This is the CI gate under QEMU.
+- **`i3c_init_test`** (`hardware` tag): executes the init/register-verify on real
+  hardware only — `target_compatible_with` marks it incompatible when
+  `qemu_enabled`, because QEMU `ast1030-evb` does not model the I3C pads/PHY.
+
+Pass/fail is signalled by writing `TEST_RESULT:PASS` / `TEST_RESULT:FAIL` to the
+console, the same sentinel protocol the I2C tests use.
diff --git a/target/ast10x0/tests/peripherals/i3c/i3c_init/system.json5 b/target/ast10x0/tests/peripherals/i3c/i3c_init/system.json5
new file mode 100644
index 00000000..40e635a4
--- /dev/null
+++ b/target/ast10x0/tests/peripherals/i3c/i3c_init/system.json5
@@ -0,0 +1,18 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+// AST10x0 Kernel I3C Test Configuration
+// Uses the same memory layout as the kernel-only / I2C tests.
+{
+    arch: {
+        type: "armv7m",
+        vector_table_start_address: 0x00000000,
+        vector_table_size_bytes: 1280,  // 0x500 (320 vectors)
+    },
+    kernel: {
+        flash_start_address: 0x00000500,  // After vector table
+        flash_size_bytes: 262144,         // 256KB for kernel code (in RAM)
+        ram_start_address: 0x00040500,    // RAM starts after code
+        ram_size_bytes: 393216,           // 384KB for data
+    },
+}
diff --git a/target/ast10x0/tests/peripherals/i3c/i3c_init/target.rs b/target/ast10x0/tests/peripherals/i3c/i3c_init/target.rs
new file mode 100644
index 00000000..ab0fd736
--- /dev/null
+++ b/target/ast10x0/tests/peripherals/i3c/i3c_init/target.rs
@@ -0,0 +1,113 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+#![no_std]
+#![no_main]
+
+//! I3C controller init smoke test.
+//!
+//! Brings up I3C bus 0 (`PAC I3c`) through the `ast10x0_peripherals::i3c`
+//! driver — the behavioral-parity port of `aspeed-rust/src/i3c/`
+//! (see `target/ast10x0/peripherals/i3c/plans/goal.md`). Validates the clock
+//! configuration, constructs the controller behind the confined-`unsafe`
+//! façade with a busy-spin yield hook, runs the `Uninitialized -> Ready`
+//! bring-up (`start()`), and (on real hardware) verifies the
+//! controller-enable bit. Reports PASS/FAIL via the console sentinel,
+//! matching the I2C tests.
+
+use ast10x0_board::{Ast10x0Board, Ast10x0BoardDescriptor};
+use ast10x0_peripherals::i3c::{Ast1060I3c, I3cConfig, I3cController};
+use ast10x0_peripherals::scu::pinctrl;
+use codegen as _;
+use console_backend::console_backend_write_all;
+use entry as _;
+use target_common::{declare_target, TargetInterface};
+
+pub struct Target {}
+
+/// One driver type serves every bus; the instance is selected at runtime.
+type I3cHw = Ast1060I3c<fn(u32)>;
+/// Bus index under test (PAC `I3c`, the first instance).
+const I3C_BUS: u8 = 0;
+
+/// Busy-spin yield hook (bare-metal wait policy). A named `fn` (not a closure)
+/// keeps the `I3cCore` type nameable for the `singleton!` storage.
+fn yield_spin(_ns: u32) {
+    core::hint::spin_loop();
+}
+
+/// Example platform core clock (Hz) for timing computation. The AST1060 I3C
+/// core is fed from the HCLK domain; 200 MHz is a representative value and is
+/// only used to derive the timing-register fields during `init`.
+const CORE_CLK_HZ: u32 = 200_000_000;
+/// Target I3C push-pull SCL (12.5 MHz, SDR0).
+const I3C_SCL_HZ: u32 = 12_500_000;
+/// Target legacy-I2C SCL (Fast-mode, 400 kHz).
+const I2C_SCL_HZ: u32 = 400_000;
+
+fn run_i3c_init_smoke_test() -> Result<(), &'static str> {
+    pw_log::info!("=== AST10x0 I3C init smoke test ===");
+
+    let board = Ast10x0Board::new(Ast10x0BoardDescriptor {
+        pinctrl_groups: &[pinctrl::PINCTRL_I3C0],
+        i2c_buses: &[],
+    });
+    // SAFETY: Test target runs once at boot with exclusive access to the board.
+    unsafe { board.init() }.expect("board init failed");
+    pw_log::info!("Board-level pinctrl applied for I3C1");
+
+    let mut config = I3cConfig::new()
+        .core_clk_hz(CORE_CLK_HZ)
+        .i3c_scl_hz(I3C_SCL_HZ)
+        .i2c_scl_hz(I2C_SCL_HZ);
+    config.core_period = 1_000_000_000 / CORE_CLK_HZ;
+
+    config
+        .validate_clock()
+        .map_err(|_| "i3c clock validation failed")?;
+    pw_log::info!("Clock configuration validated");
+
+    // SAFETY: the test owns I3C bus 0 for its lifetime and uses the matching
+    // PAC register blocks; the busy-spin hook is the bare-metal wait policy.
+    let hw = unsafe { I3cHw::new(I3C_BUS, yield_spin) }.ok_or("invalid I3C bus index")?;
+    let ctrl = I3cController::new(hw, &mut config);
+    pw_log::info!("Controller constructed");
+
+    // `start()` claims the IRQ slot (single-shot) and programs the hardware.
+    // This smoke test leaves the NVIC line masked (its system.json5 has no
+    // I3C vector entry), so no interrupt can be delivered.
+    let _ctrl = ctrl.start().map_err(|_| "controller start failed")?;
+    pw_log::info!("controller start complete");
+
+    // On real hardware the controller-enable bit must be set after a primary
+    // (non-secondary) init. QEMU `ast1030-evb` does not model the I3C block, so
+    // the on-hardware register check is exercised only by the hardware-tagged
+    // `i3c_init_test`; here we confirm the bring-up sequence ran to completion.
+    // SAFETY: exclusive ownership of I3C bus 0 during the test.
+    let regs = unsafe { &*ast1060_pac::I3c::ptr() };
+    let enabled = regs.i3cd000().read().enbl_i3cctrl().bit_is_set();
+    pw_log::info!("i3cd000.enbl_i3cctrl = {}", enabled as u8);
+
+    pw_log::info!("=== AST10x0 I3C init smoke test complete ===");
+    Ok(())
+}
+
+impl TargetInterface for Target {
+    const NAME: &'static str = "AST10x0 Kernel I3C";
+
+    fn main() -> ! {
+        let sentinel: &[u8] = match run_i3c_init_smoke_test() {
+            Ok(()) => b"TEST_RESULT:PASS\n",
+            Err(error) => {
+                pw_log::error!("I3C init smoke test failed: {}", error as &str);
+                b"TEST_RESULT:FAIL\n"
+            }
+        };
+
+        let _ = console_backend_write_all(sentinel);
+        #[expect(clippy::empty_loop)]
+        loop {}
+    }
+}
+
+declare_target!(Target);
diff --git a/target/ast10x0/tests/peripherals/i3c/i3c_irq/BUILD.bazel b/target/ast10x0/tests/peripherals/i3c/i3c_irq/BUILD.bazel
new file mode 100644
index 00000000..f1193cac
--- /dev/null
+++ b/target/ast10x0/tests/peripherals/i3c/i3c_irq/BUILD.bazel
@@ -0,0 +1,139 @@
+# Licensed under the Apache-2.0 license
+# SPDX-License-Identifier: Apache-2.0
+
+load("@pigweed//pw_kernel/tooling:system_image.bzl", "system_image")
+load("@pigweed//pw_kernel/tooling:target_codegen.bzl", "target_codegen")
+load("@pigweed//pw_kernel/tooling:target_linker_script.bzl", "target_linker_script")
+load("@pigweed//pw_kernel/tooling/panic_detector:rust_binary_no_panics_test.bzl", "rust_binary_no_panics_test")
+load("@rules_rust//rust:defs.bzl", "rust_binary")
+load("//target/ast10x0:defs.bzl", "TARGET_COMPATIBLE_WITH", "system_image_test")
+
+COMMON_DEPS = [
+    "//target/ast10x0:config",
+    "//target/ast10x0:entry",
+    "//target/ast10x0/board:ast10x0_board",
+    "//target/ast10x0/peripherals",
+    "@ast1060_pac",
+    "@pigweed//pw_kernel/arch/arm_cortex_m:arch_arm_cortex_m",
+    "@pigweed//pw_kernel/kernel",
+    "@pigweed//pw_kernel/subsys/console:console_backend",
+    "@pigweed//pw_kernel/target:target_common",
+    "@pigweed//pw_log/rust:pw_log",
+    "@pigweed//pw_status/rust:pw_status",
+    "@rust_crates//:cortex-m",
+    "@rust_crates//:cortex-m-semihosting",
+]
+
+# ---------------------------------------------------------------------------
+# Controller image (device A)
+# ---------------------------------------------------------------------------
+
+filegroup(
+    name = "system_config",
+    srcs = ["system.json5"],
+)
+
+target_codegen(
+    name = "codegen",
+    arch = "@pigweed//pw_kernel/arch/arm_cortex_m:arch_arm_cortex_m",
+    system_config = ":system_config",
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+)
+
+target_linker_script(
+    name = "linker_script",
+    system_config = ":system_config",
+    tags = ["kernel"],
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+    template = "//target/ast10x0:linker_script_template",
+)
+
+rust_binary(
+    name = "target",
+    srcs = ["target.rs"],
+    edition = "2024",
+    tags = ["kernel"],
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+    deps = [
+        ":codegen",
+        ":linker_script",
+    ] + COMMON_DEPS,
+)
+
+system_image(
+    name = "controller",
+    kernel = ":target",
+    platform = "//target/ast10x0",
+    system_config = ":system_config",
+    tags = ["kernel"],
+    userspace = False,
+)
+
+system_image_test(
+    name = "irq_test",
+    image = ":controller",
+    slave_image = ":slave",
+    tags = ["hardware"],
+    target_compatible_with = select({
+        "//target/ast10x0:qemu_enabled": ["@platforms//:incompatible"],
+        "//conditions:default": [],
+    }),
+)
+
+rust_binary_no_panics_test(
+    name = "no_panics_test",
+    binary = ":controller",
+    tags = ["kernel"],
+)
+
+# ---------------------------------------------------------------------------
+# Target image (device B)
+# ---------------------------------------------------------------------------
+
+filegroup(
+    name = "slave_system_config",
+    srcs = ["slave_system.json5"],
+)
+
+target_codegen(
+    name = "slave_codegen",
+    arch = "@pigweed//pw_kernel/arch/arm_cortex_m:arch_arm_cortex_m",
+    crate_name = "codegen",
+    system_config = ":slave_system_config",
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+)
+
+target_linker_script(
+    name = "slave_linker_script",
+    system_config = ":slave_system_config",
+    tags = ["kernel"],
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+    template = "//target/ast10x0:linker_script_template",
+)
+
+rust_binary(
+    name = "slave_target",
+    srcs = ["slave_target.rs"],
+    edition = "2024",
+    tags = ["kernel"],
+    target_compatible_with = TARGET_COMPATIBLE_WITH,
+    deps = [
+        ":slave_codegen",
+        ":slave_linker_script",
+    ] + COMMON_DEPS,
+)
+
+system_image(
+    name = "slave",
+    kernel = ":slave_target",
+    platform = "//target/ast10x0",
+    system_config = ":slave_system_config",
+    tags = ["kernel"],
+    userspace = False,
+)
+
+rust_binary_no_panics_test(
+    name = "slave_no_panics_test",
+    binary = ":slave",
+    tags = ["kernel"],
+)
diff --git a/target/ast10x0/tests/peripherals/i3c/i3c_irq/slave_system.json5 b/target/ast10x0/tests/peripherals/i3c/i3c_irq/slave_system.json5
new file mode 100644
index 00000000..dd904d47
--- /dev/null
+++ b/target/ast10x0/tests/peripherals/i3c/i3c_irq/slave_system.json5
@@ -0,0 +1,23 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+// AST10x0 I3C IBI Test — target image (device B). Same layout as the controller.
+{
+    arch: {
+        type: "armv7m",
+        vector_table_start_address: 0x00000000,
+        vector_table_size_bytes: 1536,  // 0x600: exception vectors + PW_KERNEL_INTERRUPT_TABLE_ARRAY up to IRQ 104
+    },
+    kernel: {
+        flash_start_address: 0x00000600,
+        flash_size_bytes: 262144,
+        ram_start_address: 0x00040600,
+        ram_size_bytes: 393216,
+        interrupt_table: {
+            table: {
+                // I3C2 IRQ (bus 2, used by the HV IBI test).
+                "104": "crate::i3c2_irq",
+            },
+        },
+    },
+}
diff --git a/target/ast10x0/tests/peripherals/i3c/i3c_irq/slave_target.rs b/target/ast10x0/tests/peripherals/i3c/i3c_irq/slave_target.rs
new file mode 100644
index 00000000..fbd6e90f
--- /dev/null
+++ b/target/ast10x0/tests/peripherals/i3c/i3c_irq/slave_target.rs
@@ -0,0 +1,322 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C In-Band-Interrupt test — target side (device B).
+//!
+//! Faithful openprot port of aspeed-rust `tests-hw/src/i3c_test.rs::test_i3c_target`
+//! (@ ce3b567). Companion to `target.rs`; runs on the AST1060 Test Harness on
+//! I3C **bus 2** (PAC `I3c2`) HV pads (`PINCTRL_HVI3C2`).
+//!
+//! Boot order (mirrors the reference): power **the controller first**, then this
+//! target — the controller must already be draining the IBI work queue when this
+//! target raises its Hot-Join.
+//!
+//! Flow (mirrors the reference): come up in secondary mode, attach a device,
+//! raise a Hot-Join, wait for the controller to assign a dynamic address, then
+//! send 10 IBIs (each making a 16-byte payload available for the controller to
+//! read). Panic-hygiene-only differences from the reference (Delta D9).
+//!
+//! Under QEMU this image is build- + `no_panics`-checked; the real exchange runs
+//! under the `hardware`-tagged `irq_test` (`--config=k_ast1060_evb`).
+
+#![no_std]
+#![no_main]
+
+use ast10x0_board::{Ast10x0Board, Ast10x0BoardDescriptor};
+use ast10x0_peripherals::i3c::{
+    i3c_ibi_workq_consumer, Ast1060I3c, I3cConfig, I3cController, I3cTargetConfig, IbiConsumer,
+    IbiWork,
+};
+use ast10x0_peripherals::scu::pinctrl;
+use codegen as _;
+use console_backend::console_backend_write_all;
+use cortex_m::peripheral::NVIC;
+use entry as _;
+use kernel::Kernel;
+use target_common::{declare_target, TargetInterface};
+
+pub struct Target {}
+
+/// One driver type serves every bus; the instance is selected at runtime.
+type I3cHw = Ast1060I3c<fn(u32)>;
+
+/// Bus index under test (PAC `I3c2`, HV pads).
+const I3C_BUS: u8 = 2;
+
+/// Number of IBIs the target raises once it has a dynamic address.
+const MAX_IBIS: u32 = 10;
+/// Give the controller time to finish init and open the hot-join ACK window.
+const HOT_JOIN_STARTUP_DELAY_SPINS: u32 = 0x1000_0000;
+/// Re-raise hot-join while waiting in case the first request hit the NACK window.
+const HOT_JOIN_RETRY_SPINS: u32 = 0x0400_0000;
+const WAIT_MASTER_WRITE_SPINS: u32 = 0x0400_0000;
+const XFER_DATA_LEN: usize = 16;
+
+fn spin_wait(mut cycles: u32) {
+    while cycles != 0 {
+        core::hint::spin_loop();
+        cycles = cycles.wrapping_sub(1);
+    }
+}
+
+/// Read-only register snapshot for debugging (never pops a queue).
+fn dump_slave_i3c2(label: u32) {
+    let regs = unsafe { &*ast1060_pac::I3c2::ptr() };
+    let status = regs.i3cd03c().read().bits();
+    let queue = regs.i3cd04c().read().bits();
+    let present = regs.i3cd054().read().bits();
+    let event_ctrl = regs.i3cd038().read().bits();
+    let dev_addr = regs.i3cd004().read().bits();
+    pw_log::info!(
+        "[SDUMP{}] status={:08x} queue={:08x}",
+        label as u32,
+        status as u32,
+        queue as u32
+    );
+    pw_log::info!(
+        "[SDUMP{}] present={:08x} event_ctrl={:08x}",
+        label as u32,
+        present as u32,
+        event_ctrl as u32
+    );
+    pw_log::info!("[SDUMP{}] dev_addr={:08x}", label as u32, dev_addr as u32);
+}
+
+fn log_target_hj_state(label: u32) {
+    let regs = unsafe { &*ast1060_pac::I3c2::ptr() };
+    let dev_addr = regs.i3cd004().read().bits();
+    let event_ctrl = regs.i3cd038().read().bits();
+    let device_char = regs.i3cd008().read().bits();
+    pw_log::info!(
+        "[DBG] target hj label={} dev_addr={}",
+        label as u32,
+        dev_addr as u32
+    );
+    pw_log::info!(
+        "[DBG] target hj event_ctrl={} device_char={}",
+        event_ctrl as u32,
+        device_char as u32
+    );
+}
+
+/// Logs the first [`XFER_DATA_LEN`] bytes of a received master write. The
+/// work item's inline buffer is larger (`IBI_MWR_DATA_MAX`); this test only
+/// exchanges 16-byte payloads.
+fn log_target_master_write(exchange: u32, len: u8, data: &[u8]) {
+    let mut d = [0u8; XFER_DATA_LEN];
+    let take = data.len().min(d.len());
+    d[..take].copy_from_slice(&data[..take]);
+    let w0 = u32::from_be_bytes([d[0], d[1], d[2], d[3]]);
+    let w1 = u32::from_be_bytes([d[4], d[5], d[6], d[7]]);
+    let w2 = u32::from_be_bytes([d[8], d[9], d[10], d[11]]);
+    let w3 = u32::from_be_bytes([d[12], d[13], d[14], d[15]]);
+    pw_log::info!(
+        "TARGET_RX_FROM_MASTER #{} {}B {:08x} {:08x} {:08x} {:08x}",
+        exchange as u32,
+        len as u32,
+        w0 as u32,
+        w1 as u32,
+        w2 as u32,
+        w3 as u32
+    );
+}
+
+fn log_target_read_payload(ibi_count: u32, data: &[u8; XFER_DATA_LEN]) {
+    let w0 = u32::from_be_bytes([data[0], data[1], data[2], data[3]]);
+    let w1 = u32::from_be_bytes([data[4], data[5], data[6], data[7]]);
+    let w2 = u32::from_be_bytes([data[8], data[9], data[10], data[11]]);
+    let w3 = u32::from_be_bytes([data[12], data[13], data[14], data[15]]);
+    pw_log::info!(
+        "TARGET_TX_TO_MASTER #{} 16B {:08x} {:08x} {:08x} {:08x}",
+        ibi_count as u32,
+        w0 as u32,
+        w1 as u32,
+        w2 as u32,
+        w3 as u32
+    );
+}
+
+fn wait_for_master_write(ibi_cons: &mut IbiConsumer, exchange: u32) -> Result<(), &'static str> {
+    let mut spin_count = 0u32;
+    loop {
+        let Some(work) = ibi_cons.dequeue() else {
+            core::hint::spin_loop();
+            spin_count = spin_count.wrapping_add(1);
+            if spin_count >= WAIT_MASTER_WRITE_SPINS {
+                return Err("master write not received");
+            }
+            continue;
+        };
+
+        match work {
+            IbiWork::TargetMasterWrite { len, data } => {
+                log_target_master_write(exchange, len, &data);
+                return Ok(());
+            }
+            IbiWork::TargetDaAssignment => pw_log::info!("[IBI] TargetDaAssignment"),
+            IbiWork::HotJoin => pw_log::info!("[IBI] hotjoin"),
+            IbiWork::Sirq { addr, len, .. } => {
+                pw_log::info!("[IBI] SIRQ from 0x{:02x} len {}", addr as u32, len as u32);
+            }
+        }
+    }
+}
+
+/// Calibrated busy-wait used as the driver's yield/delay hook. Mirrors the
+/// reference `DummyDelay::delay_ns` (busy-loop of ~`ns / 100` nops). A named
+/// `fn` (not a closure) keeps the driver type nameable.
+fn yield_delay(ns: u32) {
+    for _ in 0..(ns / 100) {
+        core::hint::spin_loop();
+    }
+}
+
+/// Build + validate the configuration in its own `#[inline(never)]` frame so
+/// builder temporaries are freed on return — the kernel bootstrap stack is
+/// only 2 KiB and the config embeds the ~0.5 KiB device tables. The caller
+/// keeps the single live config and lends it to the controller (`&mut`).
+#[inline(never)]
+fn build_config() -> Result<I3cConfig, &'static str> {
+    // Secondary (target) timing — identical to the reference target.
+    let mut config = I3cConfig::new()
+        .core_clk_hz(200_000_000)
+        .secondary(true)
+        .i2c_scl_hz(1_000_000)
+        .i3c_scl_hz(12_500_000)
+        .i3c_pp_scl_hi_period_ns(36)
+        .i3c_pp_scl_lo_period_ns(36)
+        .i3c_od_scl_hi_period_ns(0)
+        .i3c_od_scl_lo_period_ns(0)
+        .sda_tx_hold_ns(0)
+        .dcr(0xcc)
+        .target_config(I3cTargetConfig::new(0, Some(0), 0xae));
+    config.init_runtime_fields();
+    config
+        .validate_clock()
+        .map_err(|_| "invalid clock configuration")?;
+    Ok(config)
+}
+
+fn run_target() -> Result<(), &'static str> {
+    pw_log::info!("####### I3C target test #######");
+
+    let board = Ast10x0Board::new(Ast10x0BoardDescriptor {
+        pinctrl_groups: &[pinctrl::PINCTRL_HVI3C2],
+        i2c_buses: &[],
+    });
+    // SAFETY: single call at boot with exclusive access to the board.
+    unsafe { board.init() }.expect("board init failed");
+
+    // Build the config in a separate (never-inlined) frame, keep the single
+    // live copy here, and lend it to the controller — see `build_config`.
+    let mut config = build_config()?;
+    // SAFETY: the test owns I3C bus 2 and uses the matching PAC blocks.
+    let hw = unsafe { I3cHw::new(I3C_BUS, yield_delay) }.ok_or("invalid I3C bus index")?;
+    let mut ctrl = I3cController::new(hw, &mut config)
+        .start()
+        .map_err(|_| "controller start failed")?;
+    let bus = ctrl.bus_num() as usize;
+    let mut ibi_cons = i3c_ibi_workq_consumer(bus).ok_or("IBI consumer unavailable")?;
+    pw_log::info!("IBI work queue ready on bus {}", bus as u32);
+
+    // Kernel vector is in place and the handler is registered; this
+    // integration layer owns the NVIC line for the bus it selected
+    // (`I3C_BUS` = 2 -> `Interrupt::i3c2`), so unmask it now.
+    // SAFETY: handler registered and hardware initialized (Ready state);
+    // unmasking cannot deliver an IRQ into partially-initialized state.
+    unsafe { NVIC::unmask(ast1060_pac::Interrupt::i3c2) };
+
+    let dyn_addr = 8u8;
+    let dev_idx = 0usize;
+    let _ = ctrl.attach_i3c_dev(0, dyn_addr, dev_idx as u8);
+    pw_log::info!(
+        "target dev at slot {}, dyn addr {}",
+        dev_idx as u32,
+        dyn_addr as u32
+    );
+
+    pw_log::info!("waiting before hot-join...");
+    spin_wait(HOT_JOIN_STARTUP_DELAY_SPINS);
+    pw_log::info!("raising hot-join; waiting for dynamic address assignment...");
+    let hj_ok = ctrl.target_raise_hot_join().is_ok();
+    pw_log::info!("[DBG] hot-join raise ok={}", hj_ok as u32);
+    log_target_hj_state(0);
+
+    // Wait for the controller to assign our dynamic address.
+    let mut spin_count = 0u32;
+    loop {
+        let Some(work) = ibi_cons.dequeue() else {
+            core::hint::spin_loop();
+            spin_count = spin_count.wrapping_add(1);
+            if spin_count & (HOT_JOIN_RETRY_SPINS - 1) == 0 {
+                pw_log::info!("[DBG] retry hot-join");
+                let hj_ok = ctrl.target_raise_hot_join().is_ok();
+                pw_log::info!("[DBG] hot-join retry ok={}", hj_ok as u32);
+                log_target_hj_state(1);
+            }
+            continue;
+        };
+        match work {
+            IbiWork::TargetDaAssignment => {
+                let da = ctrl.target_dynamic_address();
+                if let Some(da) = da {
+                    pw_log::info!("[IBI] dyn addr 0x{:02x} assigned by master", da as u32);
+                }
+                ctrl.target_on_dynamic_address_assigned();
+                break;
+            }
+            IbiWork::HotJoin => pw_log::info!("[IBI] hotjoin"),
+            IbiWork::Sirq { addr, len, .. } => {
+                pw_log::info!("[IBI] SIRQ from 0x{:02x} len {}", addr as u32, len as u32);
+            }
+            IbiWork::TargetMasterWrite { len, data } => {
+                log_target_master_write(0, len, &data);
+            }
+        }
+    }
+
+    // Raise IBIs, each presenting a 16-byte incrementing payload for the master.
+    let mut ibi_count = 0u32;
+    while ibi_count < MAX_IBIS {
+        let mut data = [0u8; XFER_DATA_LEN];
+        for (i, b) in data.iter_mut().enumerate() {
+            *b = u8::try_from(i).unwrap_or(0);
+        }
+        dump_slave_i3c2(ibi_count);
+        if ctrl.target_get_ibi_payload(&mut data).is_err() {
+            dump_slave_i3c2(0xdead);
+            return Err("target_get_ibi_payload failed");
+        }
+        log_target_read_payload(ibi_count, &data);
+        wait_for_master_write(&mut ibi_cons, ibi_count)?;
+        ibi_count += 1;
+    }
+
+    pw_log::info!("I3C target test done");
+    Ok(())
+}
+
+pub fn i3c2_irq<K: Kernel>(_k: K) {
+    ast10x0_peripherals::i3c::dispatch_i3c_irq(2);
+}
+
+codegen::declare_kernel_interrupt_handlers!();
+
+impl TargetInterface for Target {
+    const NAME: &'static str = "AST10x0 Kernel I3C IBI (target)";
+
+    fn main() -> ! {
+        let sentinel: &[u8] = match run_target() {
+            Ok(()) => b"TEST_RESULT:PASS\n",
+            Err(error) => {
+                pw_log::error!("I3C IBI target test failed: {}", error as &str);
+                b"TEST_RESULT:FAIL\n"
+            }
+        };
+        let _ = console_backend_write_all(sentinel);
+        #[expect(clippy::empty_loop)]
+        loop {}
+    }
+}
+
+declare_target!(Target);
diff --git a/target/ast10x0/tests/peripherals/i3c/i3c_irq/system.json5 b/target/ast10x0/tests/peripherals/i3c/i3c_irq/system.json5
new file mode 100644
index 00000000..e9d3c1c1
--- /dev/null
+++ b/target/ast10x0/tests/peripherals/i3c/i3c_irq/system.json5
@@ -0,0 +1,24 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+// AST10x0 I3C IBI Test — controller image (device A). Single kernel binary;
+// memory layout mirrors i3c_init / i2c_irq to keep the linker happy.
+{
+    arch: {
+        type: "armv7m",
+        vector_table_start_address: 0x00000000,
+        vector_table_size_bytes: 1536,  // 0x600: exception vectors + PW_KERNEL_INTERRUPT_TABLE_ARRAY up to IRQ 104
+    },
+    kernel: {
+        flash_start_address: 0x00000600,  // After vector table
+        flash_size_bytes: 262144,         // 256KB for kernel code (in RAM)
+        ram_start_address: 0x00040600,    // RAM starts after code
+        ram_size_bytes: 393216,           // 384KB for data
+        interrupt_table: {
+            table: {
+                // I3C2 IRQ (bus 2, used by the HV IBI test).
+                "104": "crate::i3c2_irq",
+            },
+        },
+    },
+}
diff --git a/target/ast10x0/tests/peripherals/i3c/i3c_irq/target.rs b/target/ast10x0/tests/peripherals/i3c/i3c_irq/target.rs
new file mode 100644
index 00000000..19ea3b6c
--- /dev/null
+++ b/target/ast10x0/tests/peripherals/i3c/i3c_irq/target.rs
@@ -0,0 +1,369 @@
+// Licensed under the Apache-2.0 license
+// SPDX-License-Identifier: Apache-2.0
+
+//! I3C In-Band-Interrupt test — controller side (device A).
+//!
+//! Faithful openprot port of aspeed-rust `tests-hw/src/i3c_test.rs::test_i3c_master`
+//! (@ ce3b567). Runs on the AST1060 Test Harness with I3C **bus 2** (PAC `I3c2`)
+//! wired between device A and device B on the **HV** pads (`PINCTRL_HVI3C2`), the
+//! same bus/pad set the reference uses. Load the `:slave` image on device B.
+//!
+//! Boot order (mirrors the reference): bring up **this controller first** so it
+//! is already draining the IBI work queue, then power the target — the target
+//! raises a Hot-Join which this controller answers by assigning a dynamic
+//! address.
+//!
+//! Flow (mirrors the reference): bring up the controller, pre-attach a device by
+//! PID, enable its IBI, then drain the IBI work queue — on Hot-Join assign a
+//! dynamic address; on a target SIR do a private read followed by a private
+//! write; stop after 10 exchanges.
+//!
+//! Differences from the reference are panic-hygiene only (Delta D9): `unwrap`s
+//! become `?`/`pw_log`, and `DummyDelay` (a no-op in the reference) is dropped.
+//! Under QEMU this image is build- + `no_panics`-checked; the two-device run is
+//! the `hardware`-tagged `irq_test` (`--config=k_ast1060_evb`).
+
+#![no_std]
+#![no_main]
+
+use ast10x0_board::{Ast10x0Board, Ast10x0BoardDescriptor};
+use ast10x0_peripherals::i3c::{
+    i3c_ibi_workq_consumer, Ast1060I3c, I3cConfig, I3cController, IbiWork, Ready,
+};
+use ast10x0_peripherals::scu::pinctrl;
+use codegen as _;
+use console_backend::console_backend_write_all;
+use cortex_m::peripheral::NVIC;
+use entry as _;
+use kernel::Kernel;
+use target_common::{declare_target, TargetInterface};
+
+pub struct Target {}
+
+/// One driver type serves every bus; the instance is selected at runtime.
+type I3cHw = Ast1060I3c<fn(u32)>;
+type I3c2Controller<'c> = I3cController<'c, I3cHw, Ready>;
+
+/// Bus index under test (PAC `I3c2`, HV pads).
+const I3C_BUS: u8 = 2;
+
+/// PID of the peer target (matches the `:slave` image / the reference).
+const KNOWN_PID: u64 = 0x07ec_a003_2000;
+/// Stop after this many master<->target exchanges.
+const MAX_EXCHANGES: u32 = 10;
+const XFER_DATA_LEN: usize = 16;
+const WAIT_LOG_SPINS: u32 = 0x0400_0000;
+
+/// Calibrated busy-wait used as the driver's yield/delay hook. Mirrors the
+/// reference `DummyDelay::delay_ns` (busy-loop of ~`ns / 100` nops). A named
+/// `fn` (not a closure) keeps the driver type nameable.
+fn yield_delay(ns: u32) {
+    for _ in 0..(ns / 100) {
+        core::hint::spin_loop();
+    }
+}
+
+fn log_master_read_payload(exchange: u32, len: u32, data: &[u8; XFER_DATA_LEN]) {
+    let w0 = u32::from_be_bytes([data[0], data[1], data[2], data[3]]);
+    let w1 = u32::from_be_bytes([data[4], data[5], data[6], data[7]]);
+    let w2 = u32::from_be_bytes([data[8], data[9], data[10], data[11]]);
+    let w3 = u32::from_be_bytes([data[12], data[13], data[14], data[15]]);
+    pw_log::info!(
+        "MASTER_RX_FROM_TARGET #{} {}B {:08x} {:08x} {:08x} {:08x}",
+        exchange as u32,
+        len as u32,
+        w0 as u32,
+        w1 as u32,
+        w2 as u32,
+        w3 as u32
+    );
+}
+
+fn log_master_write_payload(exchange: u32, data: &[u8; XFER_DATA_LEN]) {
+    let w0 = u32::from_be_bytes([data[0], data[1], data[2], data[3]]);
+    let w1 = u32::from_be_bytes([data[4], data[5], data[6], data[7]]);
+    let w2 = u32::from_be_bytes([data[8], data[9], data[10], data[11]]);
+    let w3 = u32::from_be_bytes([data[12], data[13], data[14], data[15]]);
+    pw_log::info!(
+        "MASTER_TX_TO_TARGET #{} 16B {:08x} {:08x} {:08x} {:08x}",
+        exchange as u32,
+        w0 as u32,
+        w1 as u32,
+        w2 as u32,
+        w3 as u32
+    );
+}
+
+/// Build + validate the configuration in its own `#[inline(never)]` frame so
+/// builder temporaries are freed on return — the kernel bootstrap stack is
+/// only 2 KiB and the config embeds the ~0.5 KiB device tables. The caller
+/// keeps the single live config and lends it to the controller (`&mut`).
+#[inline(never)]
+fn build_config() -> Result<I3cConfig, &'static str> {
+    // Controller (primary) timing — identical to the reference master.
+    let mut config = I3cConfig::new()
+        .core_clk_hz(200_000_000)
+        .secondary(false)
+        .i2c_scl_hz(1_000_000)
+        .i3c_scl_hz(12_500_000)
+        .i3c_pp_scl_hi_period_ns(250)
+        .i3c_pp_scl_lo_period_ns(250)
+        .i3c_od_scl_hi_period_ns(0)
+        .i3c_od_scl_lo_period_ns(0)
+        .sda_tx_hold_ns(20);
+    config.init_runtime_fields();
+    config
+        .validate_clock()
+        .map_err(|_| "invalid clock configuration")?;
+    Ok(config)
+}
+
+/// Read-only register snapshot for debugging (never pops a queue).
+fn dump_i3c2(label: u32) {
+    let regs = unsafe { &*ast1060_pac::I3c2::ptr() };
+    let status = regs.i3cd03c().read().bits();
+    let queue = regs.i3cd04c().read().bits();
+    let present = regs.i3cd054().read().bits();
+    let dat0 = regs.i3cd280().read().bits();
+    pw_log::info!(
+        "[DUMP{}] status={:08x} queue={:08x}",
+        label as u32,
+        status as u32,
+        queue as u32
+    );
+    pw_log::info!(
+        "[DUMP{}] present={:08x} dat0={:08x}",
+        label as u32,
+        present as u32,
+        dat0 as u32
+    );
+    let dev_addr = regs.i3cd004().read().bits();
+    let sir_rej = regs.i3cd030().read().bits();
+    let sten = regs.i3cd040().read().bits();
+    let sgen = regs.i3cd044().read().bits();
+    pw_log::info!(
+        "[DUMP{}] dev_addr={:08x} sir_reject={:08x}",
+        label as u32,
+        dev_addr as u32,
+        sir_rej as u32
+    );
+    pw_log::info!(
+        "[DUMP{}] status_en={:08x} signal_en={:08x}",
+        label as u32,
+        sten as u32,
+        sgen as u32
+    );
+}
+
+#[inline(never)]
+fn master_read_from_target(
+    ctrl: &mut I3c2Controller<'_>,
+) -> Result<(u32, [u8; XFER_DATA_LEN]), &'static str> {
+    let mut rx_buf = [0u8; 128];
+    let actual_len = ctrl
+        .priv_read(KNOWN_PID, &mut rx_buf)
+        .map_err(|_| "private read failed")?;
+    let mut data = [0u8; XFER_DATA_LEN];
+    let take = (actual_len as usize).min(data.len()).min(rx_buf.len());
+    data[..take].copy_from_slice(&rx_buf[..take]);
+    Ok((actual_len, data))
+}
+
+#[inline(never)]
+fn master_write_to_target(
+    ctrl: &mut I3c2Controller<'_>,
+    exchange: u32,
+) -> Result<(), &'static str> {
+    let mut tx_buf: [u8; XFER_DATA_LEN] = [
+        0xde, 0xad, 0xbe, 0xef, 0xca, 0xfe, 0xba, 0xbe, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+        0x88,
+    ];
+    ctrl.priv_write(KNOWN_PID, &mut tx_buf)
+        .map_err(|_| "private write failed")?;
+    log_master_write_payload(exchange, &tx_buf);
+    Ok(())
+}
+
+fn run_controller() -> Result<(), &'static str> {
+    pw_log::info!("####### I3C master test #######");
+
+    let board = Ast10x0Board::new(Ast10x0BoardDescriptor {
+        pinctrl_groups: &[pinctrl::PINCTRL_HVI3C2],
+        i2c_buses: &[],
+    });
+    // SAFETY: single call at boot with exclusive access to the board.
+    unsafe { board.init() }.expect("board init failed");
+
+    // Build the config in a separate (never-inlined) frame, keep the single
+    // live copy here, and lend it to the controller — see `build_config`.
+    let mut config = build_config()?;
+    // SAFETY: the test owns I3C bus 2 and uses the matching PAC blocks.
+    let hw = unsafe { I3cHw::new(I3C_BUS, yield_delay) }.ok_or("invalid I3C bus index")?;
+    let mut ctrl = I3cController::new(hw, &mut config)
+        .start()
+        .map_err(|_| "controller start failed")?;
+    let bus = ctrl.bus_num() as usize;
+    let mut ibi_cons = i3c_ibi_workq_consumer(bus).ok_or("IBI consumer unavailable")?;
+    pw_log::info!("IBI work queue ready on bus {}", bus as u32);
+
+    // The kernel vector (system.json5 IRQ 104 -> `i3c2_irq`) is in place and
+    // the handler is registered; this integration layer owns the NVIC line
+    // for the bus it selected (`I3C_BUS` = 2 -> `Interrupt::i3c2`), so unmask
+    // it now.
+    // SAFETY: handler registered and hardware initialized (Ready state);
+    // unmasking cannot deliver an IRQ into partially-initialized state.
+    unsafe { NVIC::unmask(ast1060_pac::Interrupt::i3c2) };
+    pw_log::info!("I3C2 controller ready");
+
+    let dyn_addr = ctrl
+        .alloc_dynamic_address_from(8)
+        .ok_or("no dynamic address available")?;
+    ctrl.attach_i3c_dev(KNOWN_PID, dyn_addr, 0)
+        .map_err(|_| "attach_i3c_dev failed")?;
+    ctrl.enable_ibi(dyn_addr, 0)
+        .map_err(|_| "ibi_enable failed")?;
+    pw_log::info!("pre-attached dev at slot 0, dyn addr {}", dyn_addr as u32);
+
+    let mut received = 0u32;
+    let mut spin_count = 0u32;
+    loop {
+        let Some(work) = ibi_cons.dequeue() else {
+            core::hint::spin_loop();
+            spin_count = spin_count.wrapping_add(1);
+            if spin_count & (WAIT_LOG_SPINS - 1) == 0 {
+                let irq_count = I3C2_IRQ_COUNT.load(core::sync::atomic::Ordering::Relaxed);
+                let status = I3C2_LAST_STATUS.load(core::sync::atomic::Ordering::Relaxed);
+                let queue_status =
+                    I3C2_LAST_QUEUE_STATUS.load(core::sync::atomic::Ordering::Relaxed);
+                let status_en = I3C2_LAST_STATUS_EN.load(core::sync::atomic::Ordering::Relaxed);
+                let signal_en = I3C2_LAST_SIGNAL_EN.load(core::sync::atomic::Ordering::Relaxed);
+                let ibi_count = (queue_status >> 24) & 0x1f;
+                let ibi_buf_blr = (queue_status >> 16) & 0xff;
+                let resp_blr = (queue_status >> 8) & 0xff;
+                pw_log::info!(
+                    "[DBG] waiting irq_count={} spin={}",
+                    irq_count as u32,
+                    spin_count as u32
+                );
+                pw_log::info!(
+                    "[DBG] i3c2 status={} queue={}",
+                    status as u32,
+                    queue_status as u32
+                );
+                pw_log::info!(
+                    "[DBG] i3c2 ibi_count={} ibi_buf_blr={}",
+                    ibi_count as u32,
+                    ibi_buf_blr as u32
+                );
+                pw_log::info!(
+                    "[DBG] i3c2 resp_blr={} status_en={}",
+                    resp_blr as u32,
+                    status_en as u32
+                );
+                pw_log::info!(
+                    "[DBG] i3c2 signal_en={} reserved={}",
+                    signal_en as u32,
+                    0 as u32
+                );
+            }
+            continue;
+        };
+        match work {
+            IbiWork::HotJoin => {
+                pw_log::info!("[IBI] hotjoin");
+                dump_i3c2(0);
+                let _ = ctrl.handle_hot_join();
+                match ctrl.assign_dynamic_address(dyn_addr) {
+                    Ok(da) => pw_log::info!("DA assigned: 0x{:02x}", da as u32),
+                    Err(e) => {
+                        use ast10x0_peripherals::i3c::I3cError;
+                        // 1=ENTDAA failed (AddrInUse), 2=GETPID/GETBCR failed
+                        // (Invalid), 3=bookkeeping/IBI-enable failed (Other),
+                        // 0xff=anything else
+                        let code: u32 = match e {
+                            I3cError::AddrInUse => 1,
+                            I3cError::Invalid => 2,
+                            I3cError::Other => 3,
+                            _ => 0xff,
+                        };
+                        pw_log::error!("assign_dynamic_address failed: code={}", code as u32);
+                    }
+                }
+                dump_i3c2(1);
+            }
+            IbiWork::Sirq { addr, len, .. } => {
+                pw_log::info!("[IBI] SIRQ from 0x{:02x} len {}", addr as u32, len as u32);
+                if ctrl.acknowledge_ibi(addr).is_err() {
+                    pw_log::error!("acknowledge_ibi failed");
+                }
+
+                let exchange = received;
+                let (read_len, read_data) = master_read_from_target(&mut ctrl)?;
+                log_master_read_payload(exchange, read_len, &read_data);
+
+                master_write_to_target(&mut ctrl, exchange)?;
+                received += 1;
+
+                if received >= MAX_EXCHANGES {
+                    pw_log::info!("I3C master test done");
+                    return Ok(());
+                }
+            }
+            IbiWork::TargetDaAssignment => pw_log::info!("[IBI] TargetDaAssignment"),
+            IbiWork::TargetMasterWrite { len, .. } => {
+                pw_log::info!("[IBI] TargetMasterWrite len {}", len as u32);
+            }
+        }
+    }
+}
+
+static I3C2_IRQ_COUNT: core::sync::atomic::AtomicU32 = core::sync::atomic::AtomicU32::new(0);
+static I3C2_LAST_STATUS: core::sync::atomic::AtomicU32 = core::sync::atomic::AtomicU32::new(0);
+static I3C2_LAST_QUEUE_STATUS: core::sync::atomic::AtomicU32 =
+    core::sync::atomic::AtomicU32::new(0);
+static I3C2_LAST_STATUS_EN: core::sync::atomic::AtomicU32 = core::sync::atomic::AtomicU32::new(0);
+static I3C2_LAST_SIGNAL_EN: core::sync::atomic::AtomicU32 = core::sync::atomic::AtomicU32::new(0);
+
+pub fn i3c2_irq<K: Kernel>(_k: K) {
+    // Do not read i3cd018 here: that register pops the IBI queue entry.
+    let regs = unsafe { &*ast1060_pac::I3c2::ptr() };
+    I3C2_LAST_STATUS.store(
+        regs.i3cd03c().read().bits(),
+        core::sync::atomic::Ordering::Relaxed,
+    );
+    I3C2_LAST_QUEUE_STATUS.store(
+        regs.i3cd04c().read().bits(),
+        core::sync::atomic::Ordering::Relaxed,
+    );
+    I3C2_LAST_STATUS_EN.store(
+        regs.i3cd040().read().bits(),
+        core::sync::atomic::Ordering::Relaxed,
+    );
+    I3C2_LAST_SIGNAL_EN.store(
+        regs.i3cd044().read().bits(),
+        core::sync::atomic::Ordering::Relaxed,
+    );
+    I3C2_IRQ_COUNT.fetch_add(1, core::sync::atomic::Ordering::Relaxed);
+    ast10x0_peripherals::i3c::dispatch_i3c_irq(2);
+}
+
+codegen::declare_kernel_interrupt_handlers!();
+
+impl TargetInterface for Target {
+    const NAME: &'static str = "AST10x0 Kernel I3C IBI (controller)";
+
+    fn main() -> ! {
+        let sentinel: &[u8] = match run_controller() {
+            Ok(()) => b"TEST_RESULT:PASS\n",
+            Err(error) => {
+                pw_log::error!("I3C IBI controller test failed: {}", error as &str);
+                b"TEST_RESULT:FAIL\n"
+            }
+        };
+        let _ = console_backend_write_all(sentinel);
+        #[expect(clippy::empty_loop)]
+        loop {}
+    }
+}
+
+declare_target!(Target);
diff --git a/third_party/crates_io/Cargo.lock b/third_party/crates_io/Cargo.lock
index 0ab0217d..dce76ca3 100644
--- a/third_party/crates_io/Cargo.lock
+++ b/third_party/crates_io/Cargo.lock
@@ -271,6 +271,7 @@ checksum = "8ec610d8f49840a5b376c69663b6369e71f4b34484b9b2eb29fb918d92516cb9"
 dependencies = [
  "bare-metal",
  "bitfield 0.13.2",
+ "critical-section",
  "embedded-hal 0.2.7",
  "volatile-register",
 ]
@@ -1295,6 +1296,7 @@ dependencies = [
  "cortex-m",
  "cortex-m-rt",
  "cortex-m-semihosting",
+ "critical-section",
  "ctr",
  "ecdsa",
  "embedded-hal 1.0.0",
diff --git a/third_party/crates_io/Cargo.toml b/third_party/crates_io/Cargo.toml
index a83b7b6c..0fbd3ef7 100644
--- a/third_party/crates_io/Cargo.toml
+++ b/third_party/crates_io/Cargo.toml
@@ -39,9 +39,10 @@ vcell = "0.1.2"
 zerocopy = { version = "0.8.48", default-features = false, features = ["derive"] }
 zeroize = { version = "1.8", default-features = false, features = ["derive"] }
 
-cortex-m = "0.7.7"
+cortex-m = { version = "0.7.7", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7.5"
 cortex-m-semihosting = "0.5.0"
+critical-section = "1.2"
 embedded-hal = "1.0"
 embedded-hal-async = "1.0"
 embedded-hal-nb = "1.0"
diff --git a/third_party/pigweed/syscall_defs_always_compatible.patch b/third_party/pigweed/syscall_defs_always_compatible.patch
new file mode 100644
index 00000000..4e8a1c88
--- /dev/null
+++ b/third_party/pigweed/syscall_defs_always_compatible.patch
@@ -0,0 +1,13 @@
+--- a/pw_kernel/syscall/BUILD.bazel
++++ b/pw_kernel/syscall/BUILD.bazel
+@@ -27,10 +27,6 @@
+     edition = "2024",
+     rustc_flags = KERNEL_TEST_RUSTC_FLAGS,
+     tags = ["kernel"],
+-    target_compatible_with = select({
+-        "//pw_kernel/userspace:userspace_build_enabled": [],
+-        "//conditions:default": ["@platforms//:incompatible"],
+-    }),
+     deps = [
+         "//pw_status/rust:pw_status",
+         "@rust_crates//:bitflags",