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franciscofrancoDhineshCool
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drm: msm: kcal: export rgb to userspace and clean it up
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
1 parent 20e2867 commit 978c7d9

1 file changed

Lines changed: 24 additions & 35 deletions

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drivers/gpu/drm/msm/sde/sde_hw_color_proc_v4.c

Lines changed: 24 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,19 @@
1010
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1111
* GNU General Public License for more details.
1212
*/
13+
#include <linux/moduleparam.h>
1314
#include <drm/msm_drm_pp.h>
1415
#include "sde_hw_color_proc_common_v4.h"
1516
#include "sde_hw_color_proc_v4.h"
1617

18+
unsigned int kcal_red = 256;
19+
unsigned int kcal_green = 256;
20+
unsigned int kcal_blue = 256;
21+
22+
module_param(kcal_red, uint, 0644);
23+
module_param(kcal_green, uint, 0644);
24+
module_param(kcal_blue, uint, 0644);
25+
1726
static int sde_write_3d_gamut(struct sde_hw_blk_reg_map *hw,
1827
struct drm_msm_3d_gamut *payload, u32 base,
1928
u32 *opcode)
@@ -173,21 +182,21 @@ void sde_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)
173182
struct drm_msm_pcc *pcc_cfg;
174183
struct drm_msm_pcc_coeff *coeffs = NULL;
175184
int i = 0;
185+
int kcal_min = 20;
176186
u32 base = 0;
177-
#if 1
178-
int enable = 0, r=255,g=255,b=255, min = 20;
179-
#endif
180187

181188
if (!ctx || !cfg) {
182189
DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg);
183190
return;
184191
}
185-
#if 1
186-
pr_info("%s [CLEANSLATE] kcal setup... \n",__func__);
187-
if (r<min) r= min;
188-
if (g<min) g= min;
189-
if (b<min) b= min;
190-
#endif
192+
193+
if (kcal_red < kcal_min)
194+
kcal_red = kcal_min;
195+
if (kcal_green < kcal_min)
196+
kcal_green = kcal_min;
197+
if (kcal_blue < kcal_min)
198+
kcal_blue = kcal_min;
199+
191200
if (!hw_cfg->payload) {
192201
DRM_DEBUG_DRIVER("disable pcc feature\n");
193202
SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, 0);
@@ -239,39 +248,19 @@ void sde_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg)
239248
SDE_REG_WRITE(&ctx->hw, base + PCC_C_OFF, coeffs->c);
240249
// ====
241250
// RED
242-
#if 1
243-
if (enable && i==0) {
244-
SDE_REG_WRITE(&ctx->hw, base + PCC_R_OFF, (coeffs->r * r)/256);
245-
pr_info("%s [CLEANSLATE] kcal r = %d\n",__func__,(coeffs->r * r)/256);
246-
} else
247-
#endif
248-
SDE_REG_WRITE(&ctx->hw, base + PCC_R_OFF, coeffs->r);
251+
SDE_REG_WRITE(&ctx->hw, base + PCC_R_OFF,
252+
i == 0 ? (coeffs->r * kcal_red) / 256 : coeffs->r);
249253
// GREEN
250-
#if 1
251-
if (enable && i==1) {
252-
SDE_REG_WRITE(&ctx->hw, base + PCC_G_OFF, (coeffs->g * g)/256);
253-
pr_info("%s [CLEANSLATE] kcal g = %d\n",__func__,(coeffs->g * g)/256);
254-
} else
255-
#endif
256-
SDE_REG_WRITE(&ctx->hw, base + PCC_G_OFF, coeffs->g);
254+
SDE_REG_WRITE(&ctx->hw, base + PCC_G_OFF,
255+
i == 1 ? (coeffs->g * kcal_green) / 256 : coeffs->g);
257256
// BLUE
258-
#if 1
259-
if (enable && i==2) {
260-
SDE_REG_WRITE(&ctx->hw, base + PCC_B_OFF, (coeffs->b * b)/256);
261-
pr_info("%s [CLEANSLATE] kcal b = %d\n",__func__,(coeffs->b * b)/256);
262-
} else
263-
#endif
264-
SDE_REG_WRITE(&ctx->hw, base + PCC_B_OFF, coeffs->b);
257+
SDE_REG_WRITE(&ctx->hw, base + PCC_B_OFF,
258+
i == 2 ? (coeffs->b * kcal_blue) / 256 : coeffs->b);
265259
// =====
266260
SDE_REG_WRITE(&ctx->hw, base + PCC_RG_OFF, coeffs->rg);
267261
SDE_REG_WRITE(&ctx->hw, base + PCC_RB_OFF, coeffs->rb);
268262
SDE_REG_WRITE(&ctx->hw, base + PCC_GB_OFF, coeffs->gb);
269263
SDE_REG_WRITE(&ctx->hw, base + PCC_RGB_OFF, coeffs->rgb);
270-
#if 0
271-
pr_info("%s [CLEANSLATE] kcal setup... drm_msm_pcc i %d r %d (rg %d) r_rr %d r_gg %d r_bb %d \n",__func__, i, coeffs->r, coeffs->rg, pcc_cfg->r_rr, pcc_cfg->r_gg, pcc_cfg->r_bb);
272-
pr_info("%s [CLEANSLATE] kcal setup... drm_msm_pcc i %d g %d (rb %d) g_rr %d g_gg %d g_bb %d \n",__func__, i, coeffs->g, coeffs->rb, pcc_cfg->g_rr, pcc_cfg->g_gg, pcc_cfg->g_bb);
273-
pr_info("%s [CLEANSLATE] kcal setup... drm_msm_pcc i %d b %d (gb %d rgb %d) b_rr %d b_gg %d b_bb %d \n",__func__, i, coeffs->b, coeffs->gb, coeffs->rgb, pcc_cfg->b_rr, pcc_cfg->b_gg, pcc_cfg->b_bb);
274-
#endif
275264
}
276265

277266
SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, PCC_EN);

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