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10 | 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
11 | 11 | * GNU General Public License for more details. |
12 | 12 | */ |
| 13 | +#include <linux/moduleparam.h> |
13 | 14 | #include <drm/msm_drm_pp.h> |
14 | 15 | #include "sde_hw_color_proc_common_v4.h" |
15 | 16 | #include "sde_hw_color_proc_v4.h" |
16 | 17 |
|
| 18 | +unsigned int kcal_red = 256; |
| 19 | +unsigned int kcal_green = 256; |
| 20 | +unsigned int kcal_blue = 256; |
| 21 | + |
| 22 | +module_param(kcal_red, uint, 0644); |
| 23 | +module_param(kcal_green, uint, 0644); |
| 24 | +module_param(kcal_blue, uint, 0644); |
| 25 | + |
17 | 26 | static int sde_write_3d_gamut(struct sde_hw_blk_reg_map *hw, |
18 | 27 | struct drm_msm_3d_gamut *payload, u32 base, |
19 | 28 | u32 *opcode) |
@@ -173,21 +182,21 @@ void sde_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg) |
173 | 182 | struct drm_msm_pcc *pcc_cfg; |
174 | 183 | struct drm_msm_pcc_coeff *coeffs = NULL; |
175 | 184 | int i = 0; |
| 185 | + int kcal_min = 20; |
176 | 186 | u32 base = 0; |
177 | | -#if 1 |
178 | | - int enable = 0, r=255,g=255,b=255, min = 20; |
179 | | -#endif |
180 | 187 |
|
181 | 188 | if (!ctx || !cfg) { |
182 | 189 | DRM_ERROR("invalid param ctx %pK cfg %pK\n", ctx, cfg); |
183 | 190 | return; |
184 | 191 | } |
185 | | -#if 1 |
186 | | - pr_info("%s [CLEANSLATE] kcal setup... \n",__func__); |
187 | | - if (r<min) r= min; |
188 | | - if (g<min) g= min; |
189 | | - if (b<min) b= min; |
190 | | -#endif |
| 192 | + |
| 193 | + if (kcal_red < kcal_min) |
| 194 | + kcal_red = kcal_min; |
| 195 | + if (kcal_green < kcal_min) |
| 196 | + kcal_green = kcal_min; |
| 197 | + if (kcal_blue < kcal_min) |
| 198 | + kcal_blue = kcal_min; |
| 199 | + |
191 | 200 | if (!hw_cfg->payload) { |
192 | 201 | DRM_DEBUG_DRIVER("disable pcc feature\n"); |
193 | 202 | SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, 0); |
@@ -239,39 +248,19 @@ void sde_setup_dspp_pccv4(struct sde_hw_dspp *ctx, void *cfg) |
239 | 248 | SDE_REG_WRITE(&ctx->hw, base + PCC_C_OFF, coeffs->c); |
240 | 249 | // ==== |
241 | 250 | // RED |
242 | | -#if 1 |
243 | | - if (enable && i==0) { |
244 | | - SDE_REG_WRITE(&ctx->hw, base + PCC_R_OFF, (coeffs->r * r)/256); |
245 | | - pr_info("%s [CLEANSLATE] kcal r = %d\n",__func__,(coeffs->r * r)/256); |
246 | | - } else |
247 | | -#endif |
248 | | - SDE_REG_WRITE(&ctx->hw, base + PCC_R_OFF, coeffs->r); |
| 251 | + SDE_REG_WRITE(&ctx->hw, base + PCC_R_OFF, |
| 252 | + i == 0 ? (coeffs->r * kcal_red) / 256 : coeffs->r); |
249 | 253 | // GREEN |
250 | | -#if 1 |
251 | | - if (enable && i==1) { |
252 | | - SDE_REG_WRITE(&ctx->hw, base + PCC_G_OFF, (coeffs->g * g)/256); |
253 | | - pr_info("%s [CLEANSLATE] kcal g = %d\n",__func__,(coeffs->g * g)/256); |
254 | | - } else |
255 | | -#endif |
256 | | - SDE_REG_WRITE(&ctx->hw, base + PCC_G_OFF, coeffs->g); |
| 254 | + SDE_REG_WRITE(&ctx->hw, base + PCC_G_OFF, |
| 255 | + i == 1 ? (coeffs->g * kcal_green) / 256 : coeffs->g); |
257 | 256 | // BLUE |
258 | | -#if 1 |
259 | | - if (enable && i==2) { |
260 | | - SDE_REG_WRITE(&ctx->hw, base + PCC_B_OFF, (coeffs->b * b)/256); |
261 | | - pr_info("%s [CLEANSLATE] kcal b = %d\n",__func__,(coeffs->b * b)/256); |
262 | | - } else |
263 | | -#endif |
264 | | - SDE_REG_WRITE(&ctx->hw, base + PCC_B_OFF, coeffs->b); |
| 257 | + SDE_REG_WRITE(&ctx->hw, base + PCC_B_OFF, |
| 258 | + i == 2 ? (coeffs->b * kcal_blue) / 256 : coeffs->b); |
265 | 259 | // ===== |
266 | 260 | SDE_REG_WRITE(&ctx->hw, base + PCC_RG_OFF, coeffs->rg); |
267 | 261 | SDE_REG_WRITE(&ctx->hw, base + PCC_RB_OFF, coeffs->rb); |
268 | 262 | SDE_REG_WRITE(&ctx->hw, base + PCC_GB_OFF, coeffs->gb); |
269 | 263 | SDE_REG_WRITE(&ctx->hw, base + PCC_RGB_OFF, coeffs->rgb); |
270 | | -#if 0 |
271 | | - pr_info("%s [CLEANSLATE] kcal setup... drm_msm_pcc i %d r %d (rg %d) r_rr %d r_gg %d r_bb %d \n",__func__, i, coeffs->r, coeffs->rg, pcc_cfg->r_rr, pcc_cfg->r_gg, pcc_cfg->r_bb); |
272 | | - pr_info("%s [CLEANSLATE] kcal setup... drm_msm_pcc i %d g %d (rb %d) g_rr %d g_gg %d g_bb %d \n",__func__, i, coeffs->g, coeffs->rb, pcc_cfg->g_rr, pcc_cfg->g_gg, pcc_cfg->g_bb); |
273 | | - pr_info("%s [CLEANSLATE] kcal setup... drm_msm_pcc i %d b %d (gb %d rgb %d) b_rr %d b_gg %d b_bb %d \n",__func__, i, coeffs->b, coeffs->gb, coeffs->rgb, pcc_cfg->b_rr, pcc_cfg->b_gg, pcc_cfg->b_bb); |
274 | | -#endif |
275 | 264 | } |
276 | 265 |
|
277 | 266 | SDE_REG_WRITE(&ctx->hw, ctx->cap->sblk->pcc.base, PCC_EN); |
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