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kdrag0nExactExampl
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clk: qcom: clk-cpu-osm: Remove sdm845v1 support
Supporting sdm845v1 just adds extra complexity with no benefit as no production devices are shipping with sdm845v1. Remove support for this obscure platform altogether to simplify the driver. Signed-off-by: Danny Lin <danny@kdrag0n.dev>
1 parent 6abd593 commit 3b6dd46

1 file changed

Lines changed: 14 additions & 30 deletions

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drivers/clk/qcom/clk-cpu-osm.c

Lines changed: 14 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -58,17 +58,13 @@
5858
#define CORE_DCVS_CTRL 0xbc
5959
#define PSTATE_STATUS 0x700
6060

61-
#define DCVS_PERF_STATE_DESIRED_REG_0_V1 0x780
62-
#define DCVS_PERF_STATE_DESIRED_REG_0_V2 0x920
63-
#define DCVS_PERF_STATE_DESIRED_REG(n, v1) \
64-
(((v1) ? DCVS_PERF_STATE_DESIRED_REG_0_V1 \
65-
: DCVS_PERF_STATE_DESIRED_REG_0_V2) + 4 * (n))
66-
67-
#define OSM_CYCLE_COUNTER_STATUS_REG_0_V1 0x7d0
68-
#define OSM_CYCLE_COUNTER_STATUS_REG_0_V2 0x9c0
69-
#define OSM_CYCLE_COUNTER_STATUS_REG(n, v1) \
70-
(((v1) ? OSM_CYCLE_COUNTER_STATUS_REG_0_V1 \
71-
: OSM_CYCLE_COUNTER_STATUS_REG_0_V2) + 4 * (n))
61+
#define DCVS_PERF_STATE_DESIRED_REG_0 0x920
62+
#define DCVS_PERF_STATE_DESIRED_REG(n) \
63+
(DCVS_PERF_STATE_DESIRED_REG_0 + 4 * (n))
64+
65+
#define OSM_CYCLE_COUNTER_STATUS_REG_0 0x9c0
66+
#define OSM_CYCLE_COUNTER_STATUS_REG(n) \
67+
(OSM_CYCLE_COUNTER_STATUS_REG_0 + 4 * (n))
7268

7369
static DEFINE_VDD_REGS_INIT(vdd_l3_mx_ao, 1);
7470
static DEFINE_VDD_REGS_INIT(vdd_pwrcl_mx_ao, 1);
@@ -101,8 +97,6 @@ struct clk_osm {
10197
struct mutex update_lock;
10298
};
10399

104-
static bool is_sdm845v1;
105-
106100
static inline struct clk_osm *to_clk_osm(struct clk_hw *_hw)
107101
{
108102
return container_of(_hw, struct clk_osm, hw);
@@ -224,9 +218,7 @@ static int clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
224218
}
225219

226220
core_num = parent->per_core_dcvs ? c->core_num : 0;
227-
clk_osm_write_reg(parent, index,
228-
DCVS_PERF_STATE_DESIRED_REG(core_num,
229-
is_sdm845v1));
221+
clk_osm_write_reg(parent, index, DCVS_PERF_STATE_DESIRED_REG(core_num));
230222

231223
/* Make sure the write goes through before proceeding */
232224
clk_osm_mb(parent);
@@ -246,9 +238,7 @@ static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
246238
return -EINVAL;
247239

248240
core_num = parent->per_core_dcvs ? c->core_num : 0;
249-
index = clk_osm_read_reg(parent,
250-
DCVS_PERF_STATE_DESIRED_REG(core_num,
251-
is_sdm845v1));
241+
index = clk_osm_read_reg(parent, DCVS_PERF_STATE_DESIRED_REG(core_num));
252242
return parent->osm_table[index].frequency;
253243
}
254244

@@ -292,8 +282,7 @@ static int l3_clk_set_rate(struct clk_hw *hw, unsigned long rate,
292282
}
293283
pr_debug("rate: %lu --> index %d\n", rate, index);
294284

295-
clk_osm_write_reg(cpuclk, index,
296-
DCVS_PERF_STATE_DESIRED_REG(0, is_sdm845v1));
285+
clk_osm_write_reg(cpuclk, index, DCVS_PERF_STATE_DESIRED_REG(0));
297286

298287
/* Make sure the write goes through before proceeding */
299288
clk_osm_mb(cpuclk);
@@ -329,8 +318,7 @@ static unsigned long l3_clk_recalc_rate(struct clk_hw *hw,
329318
if (!cpuclk)
330319
return -EINVAL;
331320

332-
index = clk_osm_read_reg(cpuclk,
333-
DCVS_PERF_STATE_DESIRED_REG(0, is_sdm845v1));
321+
index = clk_osm_read_reg(cpuclk, DCVS_PERF_STATE_DESIRED_REG(0));
334322

335323
pr_debug("%s: Index %d, freq %ld\n", __func__, index,
336324
cpuclk->osm_table[index].frequency);
@@ -681,8 +669,7 @@ osm_set_index(struct clk_osm *c, unsigned int index)
681669
/* Skip the update if the current rate is the same as the new one */
682670
mutex_lock(&parent->update_lock);
683671
current_index = clk_osm_read_reg(parent,
684-
DCVS_PERF_STATE_DESIRED_REG(core_num,
685-
is_sdm845v1));
672+
DCVS_PERF_STATE_DESIRED_REG(core_num));
686673
if (current_index == index)
687674
goto unlock;
688675

@@ -718,7 +705,7 @@ static unsigned int osm_cpufreq_get(unsigned int cpu)
718705

719706
c = policy->driver_data;
720707
index = clk_osm_read_reg(c,
721-
DCVS_PERF_STATE_DESIRED_REG(c->core_num, is_sdm845v1));
708+
DCVS_PERF_STATE_DESIRED_REG(c->core_num));
722709
curr_lval = CURRENT_LVAL(clk_osm_read_reg(c, PSTATE_STATUS));
723710

724711
if (policy->freq_table[index].frequency == OSM_INIT_RATE / 1000)
@@ -1009,7 +996,7 @@ static u64 clk_osm_get_cpu_cycle_counter(int cpu)
1009996
*/
1010997
core_num = parent->per_core_dcvs ? c->core_num : 0;
1011998
val = clk_osm_read_reg_no_log(parent,
1012-
OSM_CYCLE_COUNTER_STATUS_REG(core_num, is_sdm845v1));
999+
OSM_CYCLE_COUNTER_STATUS_REG(core_num));
10131000

10141001
if (val < c->prev_cycle_counter) {
10151002
/* Handle counter overflow */
@@ -1246,9 +1233,6 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev)
12461233
return PTR_ERR(ext_xo_clk);
12471234
}
12481235

1249-
is_sdm845v1 = of_device_is_compatible(pdev->dev.of_node,
1250-
"qcom,clk-cpu-osm");
1251-
12521236
if (of_device_is_compatible(pdev->dev.of_node,
12531237
"qcom,clk-cpu-osm-sdm670"))
12541238
clk_cpu_osm_driver_sdm670_fixup();

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