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HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig and the plugins ghdl-yosys-plugin and yosys-slang. It relies on Docker and PyFPGA containers.

vhdl2vhdl: converts from a newer VHDL to VHDL'93 (using ghdl).
vhdl2vlog: converts from VHDL to Verilog (backends: ghdl or yosys).
slog2vlog: converts from SystemVerilog to Verilog (frontends: slang, synlig or yosys).