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Maintanance: Sync Read Write Velocity
1 parent 14ca4d4 commit dc02edd

1 file changed

Lines changed: 4 additions & 4 deletions

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examples/advanced/sync_read_write_raw/sync_read_write_raw.ino renamed to examples/advanced/sync_read_write_velocity/sync_read_write_velocity.ino

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -94,9 +94,9 @@ const uint8_t DXL_ID_LIST[DXL_ID_CNT] = {1, 2};
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const uint16_t user_pkt_buf_cap = 128;
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uint8_t user_pkt_buf[user_pkt_buf_cap];
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97-
const uint16_t SR_START_ADDR = 126;
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const uint16_t SR_ADDR_LEN = 10; //2+4+4
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const uint16_t SW_START_ADDR = 104; //Goal velocity
97+
const uint16_t SR_START_ADDR = 126; // Starting Data Addr, Can differ Depending on what address to access
98+
const uint16_t SR_ADDR_LEN = 10; // Data Length (2+4+4), Can differ depending on how many address to access.
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const uint16_t SW_START_ADDR = 104;
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const uint16_t SW_ADDR_LEN = 4;
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typedef struct sr_data{
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int16_t present_current;
@@ -151,7 +151,6 @@ void setup() {
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}
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sr_infos.is_info_changed = true;
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154-
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// Fill the members of structure to syncWrite using internal packet buffer
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sw_infos.packet.p_buf = nullptr;
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sw_infos.packet.is_completed = false;
@@ -162,6 +161,7 @@ void setup() {
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sw_data[0].goal_velocity = 0;
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sw_data[1].goal_velocity = 100;
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for(i=0; i<DXL_ID_CNT; i++){
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info_xels_sw[i].id = DXL_ID_LIST[i];
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info_xels_sw[i].p_data = (uint8_t*)&sw_data[i].goal_velocity;

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