Update RESMGR_ID according to device ID

Author: ANOSTM

Utilities/ResourcesManager/res_mgr.c

@@ -149,7 +149,9 @@ device_config_t mp1_device_config[] = {
   { RESMGR_ID_I2C4,         I2C4_BASE,      0x05 },
   { RESMGR_ID_RNG1,         RNG1_BASE,      0x07 },
   { RESMGR_ID_HASH1,        HASH1_BASE,     0x08 },
+#if defined (STM32MP157Cxx) || defined (STM32MP153Cxx) || defined (STM32MP151Cxx)
   { RESMGR_ID_CRYP1,        CRYP1_BASE,     0x09 },
+#endif
   { RESMGR_ID_I2C6,         I2C6_BASE,      0x0C },
   { RESMGR_ID_TIM2,         TIM2_BASE,      0x10 },
   { RESMGR_ID_TIM3,         TIM3_BASE,      0x11 },
@@ -189,9 +191,11 @@ device_config_t mp1_device_config[] = {
   { RESMGR_ID_SAI2,         SAI2_BASE,      0x3B },
   { RESMGR_ID_SAI3,         SAI3_BASE,      0x3C },
   { RESMGR_ID_DFSDM1,       DFSDM1_BASE,    0x3D },
+#if defined (STM32MP157Cxx) || defined (STM32MP157Axx) || defined (STM32MP153Cxx) || defined (STM32MP153Axx)
   { RESMGR_ID_FDCAN1,       FDCAN1_BASE,    0x3E }, /* same decprot for all FDCAN */
   { RESMGR_ID_FDCAN2,       FDCAN2_BASE,    0x3E }, /* same decprot for all FDCAN */
   { RESMGR_ID_FDCAN_CCU,    FDCAN_CCU_BASE, 0x3E }, /* same decprot for all FDCAN */
+#endif
   { RESMGR_ID_LPTIM2,       LPTIM2_BASE,    0x40 },
   { RESMGR_ID_LPTIM3,       LPTIM3_BASE,    0x41 },
   { RESMGR_ID_LPTIM4,       LPTIM4_BASE,    0x42 },
@@ -204,7 +208,9 @@ device_config_t mp1_device_config[] = {
   { RESMGR_ID_ADC2,         ADC2_BASE,      0x48 }, /* same decprot for both ADC */
   { RESMGR_ID_HASH2,        HASH2_BASE,     0x49 },
   { RESMGR_ID_RNG2,         RNG2_BASE,      0x4A },
+#if defined (STM32MP157Cxx) || defined (STM32MP153Cxx) || defined (STM32MP151Cxx)
   { RESMGR_ID_CRYP2,        CRYP2_BASE,     0x4B },
+#endif
   { RESMGR_ID_USB1_OTG_HS,  USBOTG_BASE,    0x55 },
   { RESMGR_ID_SDMMC3,       SDMMC3_BASE,    0x56 },
   { RESMGR_ID_DLYB_SDMMC3,  DLYB_SDMMC3_BASE,   0x57 },
@@ -219,8 +225,10 @@ device_config_t mp1_device_config[] = {
   { RESMGR_ID_CRC1,         CRC1_BASE,      ETZPC_NO_INDEX },
   { RESMGR_ID_DLYB_SDMMC1,  DLYB_SDMMC1_BASE,   ETZPC_NO_INDEX },
   { RESMGR_ID_DLYB_SDMMC2,  DLYB_SDMMC2_BASE,   ETZPC_NO_INDEX },
+#if defined (STM32MP157Cxx) || defined (STM32MP157Axx)
   { RESMGR_ID_DSI,          DSI_BASE,       ETZPC_NO_INDEX },
   { RESMGR_ID_GPU,          GPU_BASE,       ETZPC_NO_INDEX },
+#endif
   { RESMGR_ID_IPCC,         IPCC_BASE,      ETZPC_NO_INDEX },
   { RESMGR_ID_IWDG1,        IWDG1_BASE,     ETZPC_NO_INDEX },
   { RESMGR_ID_IWDG2,        IWDG2_BASE,     ETZPC_NO_INDEX },