-
Notifications
You must be signed in to change notification settings - Fork 1
Expand file tree
/
Copy pathRelease_Notes.html
More file actions
176 lines (176 loc) · 6.69 KB
/
Release_Notes.html
File metadata and controls
176 lines (176 loc) · 6.69 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
<!DOCTYPE html>
<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
<head>
<meta charset="utf-8" />
<meta name="generator" content="pandoc" />
<meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
<title>Release Notes for STM32C0xx CMSIS</title>
<style>
code{white-space: pre-wrap;}
span.smallcaps{font-variant: small-caps;}
div.columns{display: flex; gap: min(4vw, 1.5em);}
div.column{flex: auto; overflow-x: auto;}
div.hanging-indent{margin-left: 1.5em; text-indent: -1.5em;}
/* The extra [class] is a hack that increases specificity enough to
override a similar rule in reveal.js */
ul.task-list[class]{list-style: none;}
ul.task-list li input[type="checkbox"] {
font-size: inherit;
width: 0.8em;
margin: 0 0.8em 0.2em -1.6em;
vertical-align: middle;
}
.display.math{display: block; text-align: center; margin: 0.5rem auto;}
</style>
<link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
<link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
<!--[if lt IE 9]>
<script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
<![endif]-->
</head>
<body>
<div class="row">
<div class="col-sm-12 col-lg-4">
<center>
<h1 id="release-notes-for-stm32c0xx-cmsis">Release Notes for
<mark> STM32C0xx CMSIS </mark></h1>
<p>Copyright © 2022 STMicroelectronics<br />
</p>
<a href="https://www.st.com" class="logo"><img
src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
</center>
</div>
<section id="update-history" class="col-sm-12 col-lg-8">
<h1><strong>Update History</strong></h1>
<div class="collapse">
<input type="checkbox" id="collapse-section4" checked aria-hidden="true">
<label for="collapse-section4" checked aria-hidden="true"><strong>V1.3.0
/ 30-October-2024</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>Official release of STM32C0xx CMSIS drivers to support
<strong>STM32C051xx</strong> and <strong>STM32C091/92xx</strong>
devices</li>
<li>General updates to fix known defects and enhance implementation</li>
<li>Align version of bit and registers definition with the STM32C0
reference manual</li>
</ul>
<h2 id="contents">Contents</h2>
<ul>
<li><strong>Support of STM32C051xx and STM32C091/92xx devices</strong>:
<ul>
<li>Add “stm32c051xx.h” , “stm32c091xx.h”, and “stm32c092xx.h”
files</li>
<li>Add startup files “startup_stm32c051xx.s”, “startup_stm32c091xx.s”
and “startup_stm32c092xx.s” for EWARM, STM32CubeIDE and MDK-ARM
toolchains</li>
<li>Add STM32C051xx and STM32C091/92xx devices linker files for EWARM
and STM32CubeIDE toolchains</li>
</ul></li>
<li><strong>Registers and bit field definitions updates</strong> :
<ul>
<li>Add BL_EXIT_SEC_MEM_BASE Bootloader Exit Secure Memory Firmware
addresses</li>
<li>Remove RCC_CR_SYSDIV bit definition from C031xx and C011xx CMSIS
files as undefined</li>
</ul></li>
</ul>
<h2 id="supported-devices">Supported Devices</h2>
<ul>
<li>STM32C011xx, STM32C031xx, <strong>STM32C051xx</strong>, STM32C071xx
and <strong>STM32C091/92xx</strong> devices</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true">
<label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 /
05-June-2024</strong></label>
<div>
<h2 id="main-changes-1">Main Changes</h2>
<ul>
<li>First official release of STM32C0xx CMSIS drivers to support
<strong>STM32C071xx</strong> devices</li>
<li>General updates to fix known defects and enhance implementation</li>
<li>Align version of bit and registers definition with the STM32C0
reference manual</li>
</ul>
<h2 id="contents-1">Contents</h2>
<ul>
<li><strong>Support of STM32C071xx devices</strong>:
<ul>
<li>Add “stm32c071xx.h” file</li>
<li>Add startup files “startup_stm32c071xx.s” for EWARM, STM32CubeIDE
and MDK-ARM toolchains</li>
<li>Add STM32C071xx devices linker files for EWARM and STM32CubeIDE
toolchains</li>
</ul></li>
<li><strong>Registers and bit field definitions updates</strong> :
<ul>
<li>Add DMAMUX1_RequestGenerator3_BASE and DMAMUX1_RequestGenerator3
definitions</li>
<li>Remove DMA_IFCR_CGIF4, DMA_IFCR_CTCIF4, DMA_IFCR_CHTIF4 and
DMA_IFCR_CTEIF4 definitions</li>
<li>Add ADC_AWD2CR_AWD2CH_19, ADC_AWD2CR_AWD2CH_20, ADC_AWD2CR_AWD2CH_21
and ADC_AWD2CR_AWD2CH_22 bits definitions</li>
<li>Add ADC_AWD3CR_AWD3CH_19, ADC_AWD3CR_AWD3CH_20,
ADC_AWD3CR_AWD3CH_21, ADC_AWD3CR_AWD3CH_22 bits definitions</li>
<li>Add FLASH_OPTR_SECURE_MUXING_EN bit definition</li>
<li>Correct Flash page number section mask (FLASH_CR_PNB_Msk)</li>
<li>Remove extra FLASH_ECCR register bits definitions</li>
<li>Correct masks values of FLASH_PCROP1ASR, FLASH_WRP1AR, FLASH_WRP1BR,
FLASH_WRP1BR, FLASH_PCROP1BER registers</li>
<li>Add FLASH_SIZE macro to compute Flash size value</li>
<li>Fix correct FLASH_OPTR_BORF_LEV and FLASH_OPTR_BORR_LEV
positions</li>
<li>Remove SYSCFG_CFGR1_BOOSTEN bit definition</li>
<li>Correct SYSCFG_CFGR3 register bits masks values</li>
<li>Change SYSCFG_ITLINE0_SR_EWDG bit definition naming by
SYSCFG_ITLINE0_SR_WWDG to be aligned with the reference manual</li>
<li>Change SYSCFG_ITLINE4_SR_CLK_CTRL bit definition naming by
SYSCFG_ITLINE4_SR_RCC to be aligned with the reference manual</li>
<li>Update IS_TIM_REMAP_INSTANCE and IS_TIM_ETRSEL_INSTANCE macros</li>
<li>Update TIM Capture/Compare masks values</li>
<li>Remove extra EXTI interrupts and events Masks</li>
<li>Remove extra PWR_SR2_REGLPF bits definition</li>
<li>Update some RCC_CFGR bit definitions
<ul>
<li>Remove RCC_CFGR_MCO2PRE_3 and RCC_CFGR_MCOPRE_3 bits definitions as
reserved</li>
<li>Update RCC_CFGR_MCO2PRE_Msk and RCC_CFGR_MCOPRE_Msk masks
values</li>
</ul></li>
</ul></li>
</ul>
<h2 id="supported-devices-1">Supported Devices</h2>
<ul>
<li>STM32C011xx, STM32C031xx and STM32C071xx devices</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true">
<label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 /
07-June-2023</strong></label>
<h2 id="main-changes-2">Main Changes</h2>
<p>Align flash register address with STM32C0 reference manual</p>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true">
<label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 /
09-February-2022</strong></label>
<h2 id="main-changes-3">Main Changes</h2>
<p>First official release version of bits and registers definition
aligned with STM32C0 reference manual</p>
</div>
</section>
</div>
<footer class="sticky">
This release note uses up to date web standards and, for this reason,
should not be opened with Internet Explorer but preferably with popular
browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft
Edge.
</footer>
</body>
</html>