l1_cache_dm_8kb_simple.v

// Simplified SINGLE-CLOCK L1 D-Cache (NO CDC issues!)
// This version uses only CPU clock - memory is modeled as taking multiple cycles

`include "alu_gates_64.v"
`include "addr_alu.v"
`include "regs_and_counters.v"

module l1_cache_dm_8kb_simple #(
  parameter ADDR_W=32, LINE_BYTES=64, LINE_BITS=512, L1_BYTES=8192,
  parameter LINES=L1_BYTES/LINE_BYTES, BUS_BYTES=8
)(
  // Single clock domain
  input  wire                 clk, rst,
  input  wire                 cpu_req_valid, cpu_req_write,
  input  wire [ADDR_W-1:0]    cpu_req_addr,
  input  wire [31:0]          cpu_req_wdata,
  output reg                  cpu_req_ready,
  output reg                  cpu_resp_valid,
  output reg  [31:0]          cpu_resp_rdata,

  // Per-phase controls
  input  wire                 stat_clear,
  input  wire                 invalidate,

  // Stats out
  output wire [31:0]          stat_accesses,
  output wire [31:0]          stat_misses,
  output wire [31:0]          stat_mem_txns,
  output wire [31:0]          stat_beats,
  output wire [63:0]          stat_bytes
);
  localparam OFFSET_BITS=6, INDEX_BITS=7, TAG_BITS=ADDR_W-OFFSET_BITS-INDEX_BITS;

  reg                    valid [0:LINES-1];
  reg                    dirty [0:LINES-1];
  reg [TAG_BITS-1:0]     tags  [0:LINES-1];
  reg [LINE_BITS-1:0]    data  [0:LINES-1];
  integer ii;

  // Latched request
  reg                  rq_write;
  reg [ADDR_W-1:0]     rq_addr;
  reg [31:0]           rq_wdata;
  reg [INDEX_BITS-1:0] rq_index;
  reg [TAG_BITS-1:0]   rq_tag;
  reg [OFFSET_BITS-1:0]rq_off;

  wire [3:0] word_sel = rq_off[5:2];

  // Tag compare
  wire [TAG_BITS-1:0] tag_xor = tags[rq_index] ^ rq_tag;
  wire tag_diff_any = |tag_xor;
  wire hit = valid[rq_index] && !tag_diff_any;

  typedef enum logic [2:0] {S_IDLE,S_LOOKUP,S_EVICT,S_FILL,S_RESP} state_t;
  state_t cstate;

  // Beat counter for memory transfers
  reg  [2:0] beat;
  reg  [ADDR_W-1:0] cur_addr;
  wire [ADDR_W-1:0] line_base  = {rq_addr[ADDR_W-1:OFFSET_BITS], {OFFSET_BITS{1'b0}} };
  wire [ADDR_W-1:0] cur_addr_plus8;
  add8 #(ADDR_W) ADD8(.a(cur_addr), .y(cur_addr_plus8));

  // Memory model: simple array (instant access, but we model latency)
  reg [7:0] memory [0:4*1024*1024-1];
  reg [2:0] mem_delay;  // Cycles to wait per beat
  
  // Stats
  reg stat_clear_q;
  always @(posedge clk) stat_clear_q <= stat_clear;
  
  wire acc_inc  = (cstate==S_IDLE)   && cpu_req_valid && cpu_req_ready;
  wire miss_inc = (cstate==S_LOOKUP) && !hit;
  wire beat_inc = ((cstate==S_EVICT || cstate==S_FILL) && mem_delay==0);
  
  counter_inc1 #(32) CACC (.clk(clk), .rst(rst), .clr(stat_clear_q), .inc(acc_inc),  .q(stat_accesses));
  counter_inc1 #(32) CMIS (.clk(clk), .rst(rst), .clr(stat_clear_q), .inc(miss_inc), .q(stat_misses));
  counter_inc1 #(32) CBEAT(.clk(clk), .rst(rst), .clr(stat_clear_q), .inc(beat_inc), .q(stat_beats));
  counter_inc8 #(64) CBYTE(.clk(clk), .rst(rst), .clr(stat_clear_q), .inc8(beat_inc), .q(stat_bytes));
  
  reg txn_inc;
  counter_inc1 #(32) CTXN (.clk(clk), .rst(rst), .clr(stat_clear_q), .inc(txn_inc), .q(stat_mem_txns));

  // Main FSM
  always @(posedge clk) begin
    if (rst) begin
      cstate <= S_IDLE;
      cpu_req_ready <= 1'b1;
      cpu_resp_valid<= 1'b0;
      beat <= 0;
      mem_delay <= 0;
      txn_inc <= 0;
      for (ii=0; ii<LINES; ii=ii+1) begin
        valid[ii]<=1'b0; dirty[ii]<=1'b0; 
        tags[ii]<={TAG_BITS{1'b0}}; data[ii]<={LINE_BITS{1'b0}};
      end
    end else begin
      cpu_resp_valid <= 1'b0;
      txn_inc <= 0;
      
      if (invalidate) begin
        for (ii = 0; ii < LINES; ii = ii + 1) begin
          valid[ii] <= 1'b0;
          dirty[ii] <= 1'b0;
        end
      end

      case (cstate)
        S_IDLE: begin
          cpu_req_ready <= 1'b1;
          if (cpu_req_valid && cpu_req_ready) begin
            rq_write<=cpu_req_write; rq_addr<=cpu_req_addr; rq_wdata<=cpu_req_wdata;
            rq_off  <=cpu_req_addr[OFFSET_BITS-1:0];
            rq_index<=cpu_req_addr[OFFSET_BITS +: INDEX_BITS];
            rq_tag  <=cpu_req_addr[OFFSET_BITS+INDEX_BITS +: TAG_BITS];
            cpu_req_ready <= 1'b0;
            cstate <= S_LOOKUP;
          end
        end
        
        S_LOOKUP: begin
          if (hit) begin
            if (rq_write) begin
              data[rq_index][ (word_sel*32) +: 32 ] <= rq_wdata;
              dirty[rq_index] <= 1'b1;
            end else begin
              cpu_resp_rdata  <= data[rq_index][ (word_sel*32) +: 32 ];
            end
            cpu_resp_valid  <= 1'b1;
            cpu_req_ready <= 1'b1;
            cstate <= S_IDLE;
          end else begin
            // Miss - need to evict if dirty, then fill
            if (valid[rq_index] && dirty[rq_index]) begin
              beat <= 0;
              mem_delay <= 3'd4;  // 5 cycles per beat (200MHz mem / 1GHz cpu)
              cur_addr <= {tags[rq_index], rq_index, {OFFSET_BITS{1'b0}}};
              txn_inc <= 1;
              cstate <= S_EVICT;
            end else begin
              beat <= 0;
              mem_delay <= 3'd4;
              cur_addr <= line_base;
              txn_inc <= 1;
              cstate <= S_FILL;
            end
          end
        end
        
        S_EVICT: begin
          if (mem_delay > 0) begin
            mem_delay <= mem_delay - 1;
          end else begin
            // Write beat to memory
            memory[cur_addr + 0] <= data[rq_index][ (beat*64) +: 8 ];
            memory[cur_addr + 1] <= data[rq_index][ (beat*64+8) +: 8 ];
            memory[cur_addr + 2] <= data[rq_index][ (beat*64+16) +: 8 ];
            memory[cur_addr + 3] <= data[rq_index][ (beat*64+24) +: 8 ];
            memory[cur_addr + 4] <= data[rq_index][ (beat*64+32) +: 8 ];
            memory[cur_addr + 5] <= data[rq_index][ (beat*64+40) +: 8 ];
            memory[cur_addr + 6] <= data[rq_index][ (beat*64+48) +: 8 ];
            memory[cur_addr + 7] <= data[rq_index][ (beat*64+56) +: 8 ];
            
            if (beat == 7) begin
              // Eviction complete, start fill
              dirty[rq_index] <= 1'b0;
              beat <= 0;
              mem_delay <= 3'd4;
              cur_addr <= line_base;
              txn_inc <= 1;  // Count the fill transaction
              cstate <= S_FILL;
            end else begin
              beat <= beat + 1;
              cur_addr <= cur_addr_plus8;
              mem_delay <= 3'd4;
            end
          end
        end
        
        S_FILL: begin
          if (mem_delay > 0) begin
            mem_delay <= mem_delay - 1;
          end else begin
            // Read beat from memory
            data[rq_index][ (beat*64) +: 8 ]   <= memory[cur_addr + 0];
            data[rq_index][ (beat*64+8) +: 8 ] <= memory[cur_addr + 1];
            data[rq_index][ (beat*64+16) +: 8 ]<= memory[cur_addr + 2];
            data[rq_index][ (beat*64+24) +: 8 ]<= memory[cur_addr + 3];
            data[rq_index][ (beat*64+32) +: 8 ]<= memory[cur_addr + 4];
            data[rq_index][ (beat*64+40) +: 8 ]<= memory[cur_addr + 5];
            data[rq_index][ (beat*64+48) +: 8 ]<= memory[cur_addr + 6];
            data[rq_index][ (beat*64+56) +: 8 ]<= memory[cur_addr + 7];
            
            if (beat == 7) begin
              // Fill complete
              valid[rq_index] <= 1'b1;
              tags[rq_index] <= rq_tag;
              cstate <= S_RESP;
            end else begin
              beat <= beat + 1;
              cur_addr <= cur_addr_plus8;
              mem_delay <= 3'd4;
            end
          end
        end
        
        S_RESP: begin
          if (rq_write) begin
            data[rq_index][ (word_sel*32) +: 32 ] <= rq_wdata;
            dirty[rq_index] <= 1'b1;
          end else begin
            cpu_resp_rdata  <= data[rq_index][ (word_sel*32) +: 32 ];
          end
          cpu_resp_valid  <= 1'b1;
          cpu_req_ready <= 1'b1;
          cstate <= S_IDLE;
        end
      endcase
    end
  end
endmodule