Revisions to CVM exercise

kcaisley · kcaisley · commit 590ac87ac1e1 · 2025-05-12T17:33:00.000+02:00
diff --git a/code/CVM/cvm.py b/code/CVM/cvm.py
@@ -10,8 +10,8 @@
 GPIO_MODE_ALT0 = 4 # GPIO alternative mode 0 (GPCLK0 on GPIO 4)
 R_SERIES = 1000    # kOhm series resitor in current path (value needed to correct for its voltage drop)
 
-# access to C-library for enhanced GPIO access 
-GPIO = ctypes.CDLL("/home/pi/Embedded-System-Lab/code/lib/gpio_clib.so")  
+# access to C-library for enhanced GPIO access
+GPIO = ctypes.CDLL("/home/pi/Embedded-System-Lab/code/lib/gpio_clib.so")
 
 # voltage source with current measurement
 smu = SMU()
@@ -20,31 +20,31 @@
 
 # clock output
 GPIO.setup()
-GPIO.set_gpio_mode(CLK, GPIO_MODE_ALT0) 
+GPIO.set_gpio_mode(CLK, GPIO_MODE_ALT0)
 
 # scan parameters
 smu_voltage = 1500  # voltage amplitude for charge measurement
-frequency_values = np.arange(100, 1000, 100)   # switch frequency in kHz units
+frequency_values = np.arange(100, 500, 50)   # switching frequencies in kHz units
 current_values   = np.empty(frequency_values.size)
 
 fig, ax = plt.subplots()
 
 cvm.set_voltage(smu_voltage) # mV units
 for frequency_index, frequency in enumerate(frequency_values):
-  GPIO.set_gpclk_freq(int(frequency)) 
+  GPIO.set_gpclk_freq(int(frequency))
   time.sleep(0.05)
   current = cvm.get_current()  # mA units
   current_values[frequency_index] = current
 
 ax.plot(frequency_values, current_values)
 
-corrected_current_values = [current * smu_voltage/(smu_voltage - current * R_SERIES) for current in current_values]
-slope, offset = np.polyfit(frequency_values, corrected_current_values, 1)
-capacitance = slope/smu_voltage * 1e9 # pF units: (mA/kHz)/mV * 1e9 
+# slope, offset = ?
+# capacitance = ? # pF units: (mA/kHz)/mV * 1e9
 
-print('offset: %.4f nA' % (offset * 1e6))
-print('slope: %.4f nA/kHz' % (slope * 1e6))
-print('capacitance: %.2f pF' % capacitance)
+# Use these to plot the
+# print('offset: %.4f nA' % (offset * 1e6))
+# print('slope: %.4f nA/kHz' % (slope * 1e6))
+# print('capacitance: %.2f pF' % capacitance)
 
 ax.set(xlabel='Frequency [kHz]', ylabel='Current (mA)', title='I-F Curve')
 plt.show()
@@ -53,4 +53,3 @@
 GPIO.set_gpclk_freq(0) # switch off
 smu.close()
 GPIO.cleanup(1)
-
diff --git a/docs/source/cvm.rst b/docs/source/cvm.rst
@@ -8,7 +8,7 @@ Experiment: Capacitance Measurement
 
     CV-Meter Module
 
-This experiment uses the C-V meter module to characterise the capacitance of a sensor diode. The measurement is based on the charge-based capacitance measurement (CBCM) technique which is capable of measuring capacitance with a resolution of a few pF. The CBCM method measures an average current which is generated by periodically charging and discharging the capacitance with a constant voltage amplitude. A simplified block diagram of the measurement circuit is shown here: 
+This experiment uses the C-V meter module to characterise the capacitance of a sensor diode. The measurement is based on the charge-based capacitance measurement (CBCM) technique which is capable of measuring capacitance with a resolution of a few pF. The CBCM method measures an average current which is generated by periodically charging and discharging the capacitance with a constant voltage amplitude. A simplified block diagram of the measurement circuit is shown here:
 
 
 .. figure:: images/cbcm.png
@@ -21,8 +21,8 @@ This experiment uses the C-V meter module to characterise the capacitance of a s
 The switches which control the charging and discharging of the capacitance are steered in a way that only the current from the charging phase is measured (i.e. either S1 or S2 are closed at a time). This leads to an expression for the average current which is proportional to the capacitance, the clock frequency, and the voltage amplitude:
 
 .. math::
-  
-  I_\text{avg} = C \cdot V_{0} \cdot f_\text{CLK} +   I_\text{leak}. 
+
+  I_\text{avg} = C \cdot V_{0} \cdot f_\text{CLK} +   I_\text{leak}.
 
 The term :math:`I_\text{leak}` represents any leakage current of the capacitance, which in particular, for measuring the pn-junction of a sensor diode, cannot be neglected. To suppress this term, the capacitance can be extracted from the slope factor which is derived from the measured current as a function of the clock frequency. The slope factor is given by:
 
@@ -36,10 +36,10 @@ and therefore
 
   C = \frac{S}{V_{0}}.
 
-  
-Circuit Implementation 
+
+Circuit Implementation
 ----------------------
-The switches for charing and discharging the capacitance are implemented with a CMOS inverter. The power supply of the inverter is connected via an RC low-pass filter to the voltage source :math:`V_0` and the inverter input is connected to a GPIO signal with programmable frequency. The low-pass filter smooths the current transients during the charing phase and thus allows the measurement of the average current. The output of the inverter is connected to the capacitance under test. To characterise the (bias-) voltage dependence of a sensor diode capacitance, the output of the CBCM circuit is ac-coupled. That allows the connection of a bias voltage source to the detector diode. A large series resistor R_bias (1 Meg Ohm) isolates the bias voltage source from the CBCM circuit. 
+The switches for charing and discharging the capacitance are implemented with a CMOS inverter. The power supply of the inverter is connected via an RC low-pass filter to the voltage source :math:`V_0` and the inverter input is connected to a GPIO signal with programmable frequency. The low-pass filter smooths the current transients during the charing phase and thus allows the measurement of the average current. The output of the inverter is connected to the capacitance under test. To characterise the (bias-) voltage dependence of a sensor diode capacitance, the output of the CBCM circuit is ac-coupled. That allows the connection of a bias voltage source to the detector diode. A large series resistor R_bias (1 Meg Ohm) isolates the bias voltage source from the CBCM circuit.
 
 .. figure:: images/CVM_circuit.png
     :width: 600
@@ -48,14 +48,14 @@ The switches for charing and discharging the capacitance are implemented with a
     Simplified schematic of the CVM module. The switches are implemented with a CMOS inverter where the NMOS transistor is closed and the PMOS is open during the discharge phase (CLK = high) and the NMOS transistor is open and the PMOS is closed during the charging phase (CLK = low). The full circuit schematic is found here: :download:`CVM_1.1.pdf <documents/CVM_1.1.pdf>`
 
 
-To apply the voltage :math:`V_0` and to measure the current, an SMU-module can be used. The voltage :math:`V_0` should be chosen such that the PMOS and NMOS transistors in the CMOS inverter are not switched on at the same time. If :math:`V_0` is chosen too high (> 2 times the threshold voltage of a transistor), both transistors will be conducting during an input clock transition which will deteriorate the measurement. If the voltage is chosen too small, the measured current will be small and thus more affected by noise. 1.5 V has been found to be a good compromise for the CBCM measurement.	
+To apply the voltage :math:`V_0` and to measure the current, an SMU-module can be used. The voltage :math:`V_0` should be chosen such that the PMOS and NMOS transistors in the CMOS inverter are not switched on at the same time. If :math:`V_0` is chosen too high (> 2 times the threshold voltage of a transistor), both transistors will be conducting during an input clock transition which will deteriorate the measurement. If the voltage is chosen too small, the measured current will be small and thus more affected by noise. 1.5 V has been found to be a good compromise for the CBCM measurement.
 
-Exercises 
+Exercises
 ---------
 
-There is a script ``cvm.py`` in the folder ``code\CVM`` which contains the necessary includes, the basic configuration for implementing a programmable clock with one of the GPIO pins and code for taking capacitance measurements with the SMU module. Copy it into your ``work`` folder and use it as a template for your scripts. There is also another file called ``cvm_solution.py`` which contains working code for most of the exercises. Note that this should only be used for reference or as a last resort if you got stuck.
+Check the file ``code/CVM/cvm.py`` which contains the basic includes, the configuration for implementing a programmable clock with one of the GPIO pins, and code for taking capacitance measurements with the SMU module. Copy it into your ``work`` folder and use it as a template for your scripts.
 
-The clock configuration for the CVM module requires to call a C-library which needs ``root`` privileges. Therefore, once you navigated to your ``work`` directory, you need to start the script with the following command:
+The clock configuration for the CVM module requires calling a C-library which needs ``root`` privileges. Therefore, once you navigated to your ``work`` directory, you need to start the script with the following command:
 
 .. code-block:: text
 
@@ -65,18 +65,19 @@ The clock configuration for the CVM module requires to call a C-library which ne
 
 Exercise 0 should be solved before coming to the lab.
 
-.. admonition:: Exercise 0. Preparatory questions
+.. admonition:: Exercise 0. Pre-lab questions
+
+  #. To measure the average periodic diode charging current, an RC low-pass filter is used. As a secondary consequence, however, the :math:`R_\text{lpf}` resistor unforuntately reduces the effective voltage charging the diode capacitance. Modify the equation above to account for this effect. (Hint: If :math:`I_\text{avg}'` denotes the actual measured current, express the correction factor :math:`\frac{I_\text{avg}}{I_\text{avg}'}`.)
+  #. The ac-coupling capacitor can only be ignored if it is much larger than the capacitance of the diode. If this were not the case, how would you calculate the real capacitance from the measured value?
+  #. Give the formula of the depletion width of a pn-junction. How does the capacitance of a pn-junction depend on the bias voltage (assuming a plate capacitor configuration)? What expression normalizes a plot of this to a linear linear function?
 
-  #. To measure the average of the periodic charge current, an RC low-pass filter is used. The resulting voltage drop over the :math:`R_\text{lpf}` resistor will reduce the effective charge voltage. How would you need to modify the equation above to compensate for this effect? (Hint: If :math:`I_\text{avg}'` denotes the measured current, estimate the correction factor :math:`\frac{I_\text{avg}}{I_\text{avg}'}`.)
-  #. The ac-coupling capacitor should be much larger than the capacitance under test to not influence the measurement. If this is not the case, how would you calculate the real capacitance from the measured value?
-  #. Give the formula of the depletion width of a pn-junction. How does the capacitance of a pn-junction depend on the bias voltage (assume a plate capacitor configuration)? And how would one plot the voltage dependent capacitance as a linear function?
+.. admonition:: Exercise 1. Testing of the measurement setup
 
-.. admonition:: Exercise 1. Preparation and test of the measurement setup
-    
   #. Connect the CVM module to the base board and modify the ``cvm.py`` script such that GPIO pin 4 generates a 100 kHz clock signal. Connect an oscilloscope probe to GPIO4 test pin at the Embedded-System-Lab base board and measure the clock frequency.
   #. Connect the SMU module to the base board with an flat-ribbon cable and adjust the script such that the SMU module is set to source a voltage of 1.5 V. Measure the voltage with a DVM.
-  #. Connect the output of the SMU module to the LEMO socket on the CVM module labeled "VIN" (don't connect a test capacitor or diode yet). Modify the script that it scans the clock frequency from 100 kHz to 1 MHz in steps of 100 kHz and measures the current for each frequency step. Plot the measured current as a function of the clock frequency. Use the slope factor of this F-I plot to calculate the parasitic capacitance of CVM circuit. How large is the static leakage current (input bias current of the CVM circuit)?
-  #. Connect test capacitors or BNC cables of various lengths to the socket labeled "SENSOR" and measure their capacitance by extracting the slope factor of the F-I curve. (Hint: The capacitance of a BNC cable is around 100 pF/m.)
+  #. First we will characterize the test bench. Connect the output of the SMU module to the LEMO socket on the CVM module labeled "VIN". (Don't connect a test capacitor or diode yet). Modify the script so it scans the clock frequency from 100 kHz to 1 MHz in steps of 100 kHz and check that it measures the current at each frequency step.
+  #. Next, from the of plot the measured current as a function of the clock frequency, compute the offset and slope of this curve (``np.polyfit`` is useful here). Use these to calculate the static leakage current and parasitic capacitance of the testbench circuit.
+  #. Finally, also connect several test capacitors or BNC cables of various lengths to the socket labeled "SENSOR" and measure their capacitance by similarly extracting the slope factor of the I vs F curve. (Hint: The capacitance of a BNC cable is around 100 pF/m.) Remember to subtract the baseline leakage current first.
 
 .. admonition:: Exercise 2. Measure and plot the C-V curve of a sensor diode
 
@@ -91,7 +92,7 @@ Exercise 0 should be solved before coming to the lab.
      * - Active area
        - 2.65 mm x 2.65 mm (7.02 mm^2)
      * - Thickness
-       - 210 - 300 µm    
+       - 210 - 300 µm
      * - Reverse breakdown voltage
        - 70 V
      * - Capacitance at zero bias
@@ -108,15 +109,12 @@ Exercise 0 should be solved before coming to the lab.
   where  :math:`\epsilon_{0} = 8.854 \cdot 10^-12 \frac{F}{m}` is the vacuum permittivity, :math:`\epsilon_{Si} = 11.7` is the permittivity of silicon, :math:`A` is the active area and :math:`W` is the width of the depletion zone.
 
 
-  #. Connect the bias supply to the the connector labeled "BIAS" and plug a sensor diode (BPW 34) to the CVM module. Measure the diode capacitance at zero bias (i.e. the bias supply set to 0 Volt output). The measured capacitance should be in the range of 80 to 120 pF. Hint: Make sure that the polarity of the bias voltage is correct, i.e. the inner wire of the coax cable is connected to the positive power supply terminal (the banana plug to BNC adapter is correctly plugged into the power supply outputs ). 
-  #. Measure the capacitance of the diode as a function of the bias voltage (C-V curve) in a range from 0 to 30 Volts. Start with a step size of 1 Volt. 
-  #. Between each voltage step a certain settling time is required to reach a stable bias potential at the diode. Test the chosen settling (delay) time by scanning form 0 to 30 Volts and back to 0 Volts in one loop. The points from both scan directions should be on top of each other. If not, increase the delay time in your scan loop. Once you have optimized your scan loop timing decrease the voltage step to 100 mV and measure the capacitance again.
-  #. Use the C-V data from the previous measurement and calculate the depletion width as a function of the bias voltage. Assume a parallel plate capacitor configuration to calculate the depletion width from the measured capacitance. Plot the depletion width as a function of the bias voltage. 
-  #. What dependency of the depletion width from the bias voltage would you expect for an ideal pn-junction (i.e. abrupt junction and constant doping profile)? Implement the expression for the voltage dependent depletion width of ideal pn-junction in your code and compare the simulated data with your measurement. Adjust the simulation parameters manually to get a similar result range compared to the measurement data.
-  #. What could be the reason for the deviation of the measured data from the ideal case? 
+  #. Connect the bias supply to the the connector labeled "BIAS" and plug a sensor diode (BPW 34) to the CVM module. Measure the diode capacitance at zero bias (i.e. the bias supply set to 0 Volt output). The measured capacitance should be in the range of 80 to 120 pF. Hint: Make sure that the polarity of the bias voltage is correct, i.e. the inner wire of the coax cable is connected to the positive power supply terminal (the banana plug to BNC adapter is correctly plugged into the power supply outputs ).
+  #. Now, plot the capacitance of the diode as a function of the bias voltage (C-V curve) in a range from 0 to 30 Volts, with suffient step size to reveal the curve's shape. Note that each voltage step will require a certain settling time to reach a stable bias potential at the diode.
+  #. Use the C-V data from the previous measurement and create a plot of the depletion width as a function of the bias voltage. Assume a parallel plate capacitor configuration to calculate the depletion width from the measured capacitance.
+  #. Is this depletion width from the bias voltage what would you expect for an ideal pn-junction (i.e. abrupt junction and constant doping profile)? Implement the ideal expression for the voltage dependent depletion width of a pn-junction in your code and plot it alongside your measurement. Adjust the parameters of this simulated diode manually to get a similar result range compared to the measurement data. Explain any deviation.
 
-
-.. admonition:: Exercise 3 (advanced). Extract the doping profile from the C-V measurement
+.. admonition:: Exercise 3. Extract the doping profile from the C-V measurement
 
   As hinted in the results from the previous exercise, the doping profile of the BAS34 diode is not constant. Actually, this type of diode is a so-called PIN diode, which has a region of very low effective doping density (almost intrinsic) between the p- and n-doped regions (therefore the name "p-i-n"). The doping profile can be calculated from the C-V data using the differential capacitance method. The differential capacitance is defined as:
 
@@ -137,6 +135,5 @@ Exercise 0 should be solved before coming to the lab.
     N(W)_{\text{eff}} = \frac{2}{q \epsilon_{0} \epsilon_{Si} A^2 \frac{d}{dV}(\frac{1}{C^2})}.
 
 
-  #. Use this formula to calculate and plot the doping profile of the BPW34 diode. 
-  #. Where is the minimum of the doping profile located and how wide is the intrinsic layer approximately? What is the the minimum doping density and how does this value compare with the intrinsic doping density of silicon?
-
+  #. Use the formula to calculate doping profile effectively at each bias voltage of the BPW34 diode. Use this along with the depletion width at each bias voltage, to create a plot of doping concentration vs depletion depth.
+  #. Where is the minimum of the doping profile located and how wide is the 'I' intrinsic layerm approximately? What is the the minimum doping density and how does this value compare with the intrinsic doping density of silicon?
