@@ -116,92 +116,92 @@ impl Interpreter {
116116
117117 match inst. opcode {
118118 OpCode :: Add => {
119- let a = self . get_register ( inst. rs1 ) ;
120- let b = self . get_register ( inst. rs2 ( ) ) ;
121- self . set_register ( inst. rd , a . wrapping_add ( b ) ) ;
119+ let lhs = self . get_register ( inst. rs1 ) ;
120+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
121+ self . set_register ( inst. rd , lhs . wrapping_add ( rhs ) ) ;
122122 self . pc += 1 ;
123123 }
124124 OpCode :: Sub => {
125- let a = self . get_register ( inst. rs1 ) ;
126- let b = self . get_register ( inst. rs2 ( ) ) ;
127- self . set_register ( inst. rd , a . wrapping_sub ( b ) ) ;
125+ let lhs = self . get_register ( inst. rs1 ) ;
126+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
127+ self . set_register ( inst. rd , lhs . wrapping_sub ( rhs ) ) ;
128128 self . pc += 1 ;
129129 }
130130 OpCode :: Mul => {
131- let a = self . get_register ( inst. rs1 ) ;
132- let b = self . get_register ( inst. rs2 ( ) ) ;
133- self . set_register ( inst. rd , a . wrapping_mul ( b ) ) ;
131+ let lhs = self . get_register ( inst. rs1 ) ;
132+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
133+ self . set_register ( inst. rd , lhs . wrapping_mul ( rhs ) ) ;
134134 self . pc += 1 ;
135135 }
136136 OpCode :: Div => {
137- let a = self . get_register ( inst. rs1 ) ;
138- let b = self . get_register ( inst. rs2 ( ) ) ;
139- if b == 0 {
137+ let lhs = self . get_register ( inst. rs1 ) ;
138+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
139+ if rhs == 0 {
140140 return Err ( InterpreterError :: DivisionByZero ) ;
141141 }
142- self . set_register ( inst. rd , a / b ) ;
142+ self . set_register ( inst. rd , lhs / rhs ) ;
143143 self . pc += 1 ;
144144 }
145145 OpCode :: Mod => {
146- let a = self . get_register ( inst. rs1 ) ;
147- let b = self . get_register ( inst. rs2 ( ) ) ;
148- if b == 0 {
146+ let lhs = self . get_register ( inst. rs1 ) ;
147+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
148+ if rhs == 0 {
149149 return Err ( InterpreterError :: DivisionByZero ) ;
150150 }
151- self . set_register ( inst. rd , a % b ) ;
151+ self . set_register ( inst. rd , lhs % rhs ) ;
152152 self . pc += 1 ;
153153 }
154154 OpCode :: And => {
155- let a = self . get_register ( inst. rs1 ) ;
156- let b = self . get_register ( inst. rs2 ( ) ) ;
157- self . set_register ( inst. rd , a & b ) ;
155+ let lhs = self . get_register ( inst. rs1 ) ;
156+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
157+ self . set_register ( inst. rd , lhs & rhs ) ;
158158 self . pc += 1 ;
159159 }
160160 OpCode :: Or => {
161- let a = self . get_register ( inst. rs1 ) ;
162- let b = self . get_register ( inst. rs2 ( ) ) ;
163- self . set_register ( inst. rd , a | b ) ;
161+ let lhs = self . get_register ( inst. rs1 ) ;
162+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
163+ self . set_register ( inst. rd , lhs | rhs ) ;
164164 self . pc += 1 ;
165165 }
166166 OpCode :: Xor => {
167- let a = self . get_register ( inst. rs1 ) ;
168- let b = self . get_register ( inst. rs2 ( ) ) ;
169- self . set_register ( inst. rd , a ^ b ) ;
167+ let lhs = self . get_register ( inst. rs1 ) ;
168+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
169+ self . set_register ( inst. rd , lhs ^ rhs ) ;
170170 self . pc += 1 ;
171171 }
172172 OpCode :: Not => {
173- let a = self . get_register ( inst. rs1 ) ;
174- self . set_register ( inst. rd , !a ) ;
173+ let lhs = self . get_register ( inst. rs1 ) ;
174+ self . set_register ( inst. rd , !lhs ) ;
175175 self . pc += 1 ;
176176 }
177177 OpCode :: Eq => {
178- let a = self . get_register ( inst. rs1 ) ;
179- let b = self . get_register ( inst. rs2 ( ) ) ;
180- self . set_register ( inst. rd , if a == b { 1 } else { 0 } ) ;
178+ let lhs = self . get_register ( inst. rs1 ) ;
179+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
180+ self . set_register ( inst. rd , if lhs == rhs { 1 } else { 0 } ) ;
181181 self . pc += 1 ;
182182 }
183183 OpCode :: Lt => {
184- let a = self . get_register ( inst. rs1 ) ;
185- let b = self . get_register ( inst. rs2 ( ) ) ;
186- self . set_register ( inst. rd , if a < b { 1 } else { 0 } ) ;
184+ let lhs = self . get_register ( inst. rs1 ) ;
185+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
186+ self . set_register ( inst. rd , if lhs < rhs { 1 } else { 0 } ) ;
187187 self . pc += 1 ;
188188 }
189189 OpCode :: Gt => {
190- let a = self . get_register ( inst. rs1 ) ;
191- let b = self . get_register ( inst. rs2 ( ) ) ;
192- self . set_register ( inst. rd , if a > b { 1 } else { 0 } ) ;
190+ let lhs = self . get_register ( inst. rs1 ) ;
191+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
192+ self . set_register ( inst. rd , if lhs > rhs { 1 } else { 0 } ) ;
193193 self . pc += 1 ;
194194 }
195195 OpCode :: Le => {
196- let a = self . get_register ( inst. rs1 ) ;
197- let b = self . get_register ( inst. rs2 ( ) ) ;
198- self . set_register ( inst. rd , if a <= b { 1 } else { 0 } ) ;
196+ let lhs = self . get_register ( inst. rs1 ) ;
197+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
198+ self . set_register ( inst. rd , if lhs <= rhs { 1 } else { 0 } ) ;
199199 self . pc += 1 ;
200200 }
201201 OpCode :: Ge => {
202- let a = self . get_register ( inst. rs1 ) ;
203- let b = self . get_register ( inst. rs2 ( ) ) ;
204- self . set_register ( inst. rd , if a >= b { 1 } else { 0 } ) ;
202+ let lhs = self . get_register ( inst. rs1 ) ;
203+ let rhs = self . get_register ( inst. rs2 ( ) ) ;
204+ self . set_register ( inst. rd , if lhs >= rhs { 1 } else { 0 } ) ;
205205 self . pc += 1 ;
206206 }
207207 OpCode :: Load => {
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