Describe the bug
The CTS README documentation states that when -sink_clustering_size is not specified, the value is automatically chosen from the set {10, 20, 30}. The exact text from src/cts/README.md is:
"If this is not specified the size will be automatically chosen between 10, 20 or 30 based on the tree buffer max cap."
When running CTS on the Croc SoC design using the IHP SG13G2 130nm open-source PDK, we observed that the auto-selected cluster size was 8, outside the documented range. Upon inspecting TritonCTS.cpp, we found that when -sink_clustering_size is not set, the clustering size is determined by the sink buffer's maximum fanout via getBufferFanoutLimit(), which takes the minimum fanout limit across SDC, Liberty port, and library defaults, and passes it to limitSinkClusteringSizes(). The resulting cluster size is therefore PDK-dependent and is not limited to {10, 20, 30} as the documentation states. This was further confirmed by course staff at UC San Diego (ECE 260C).
Expected Behavior
The documentation should correctly state that:
The documentation should correctly state that when -sink_clustering_size is not set, the clustering size is determined by the sink buffer's maximum fanout via getBufferFanoutLimit() in TritonCTS.cpp. The resulting cluster size is PDK-dependent and is not limited to {10, 20, 30}.
Suggested replacement text:
"If this is not specified, sinks will be clustered based on the sink buffer's maximum fanout. "
Environment
Env.sh not available, using pre-built OpenROAD binary via Docker/Codespaces. Version confirmed from OpenROAD startup log: 26Q1-1636-g52ff2a5ea5
OpenROAD Version: 26Q1-1636-g52ff2a5ea5
Features: +GPU +GUI +Python
OS: Ubuntu 24 (Docker container / GitHub Codespaces)
PDK: IHP SG13G2 130nm (open-source)
Design: Croc SoC (https://github.com/pulp-platform/croc)
Flow: Custom Croc backend flow (openroad/run_backend.sh)
To Reproduce
Step 1: Clone the Croc SoC repository:
git clone https://github.com/pulp-platform/croc
cd croc
git submodule update --init --recursive
Step 2: Run synthesis and placement:
cd yosys && ./run_synthesis.sh --synth
cd ../openroad && ./run_backend.sh --floorplan
cd ../openroad && ./run_backend.sh --placement
Step 3: Run CTS with default parameters (no sink_clustering_size set):
cd openroad && ./run_backend.sh --cts
The relevant section of scripts/03_cts.tcl (attached):
Step 4: Observe the log, as seen below, auto-selected cluster size is 8, not from {10, 20, 30}:
Relevant log output
OpenROAD 26Q1-1636-g52ff2a5ea5
Features included (+) or not (-): +GPU +GUI +Python
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Setting up project croc
- Netlist: ../yosys/out/croc_yosys.v
- Netlist: croc
- Top design: croc_chip
- Report directory: reports
- Save directory: save
- Output directory: out
Init tech from Github PDK
Init standard cells
Init IO cells
Init SRAM macros
Init tech-lef
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_tech.lef, created 19 layers, 70 vias
Init cell-lef
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_stdcell/lef/sg13g2_stdcell.lef, created 84 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_io/lef/sg13g2_io.lef, created 22 library cells
[INFO ODB-0227] LEF file: ../ihp13/bondpad/lef/bondpad_70x70.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_256x32_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_512x16_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_1024x32_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_64x32_c2.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_64x22_c2.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_512x16_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_256x32_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_512x64_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_256x8_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_256x8_c3_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x8_c3_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x32_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_4096x16_c3_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_256x48_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_1024x16_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_64x64_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_512x32_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_256x16_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_256x16_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_512x32_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x64_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_2048x64_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_512x8_c3_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_2P_512x8_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_256x64_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_8192x32_c4.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x16_c2_bm_bist.lef, created 1 library cells
[INFO ODB-0227] LEF file: ../ihp13/pdk/ihp-sg13g2/libs.ref/sg13g2_sram/lef/RM_IHPSG13_1P_1024x8_c2_bm_bist.lef, created 1 library cells
Loading checkpoint 02_croc.placed
Loading from ZIP file: save/02_croc.placed.zip
###############################################################################
# Stage 03: CLOCK TREE SYNTHESIS
###############################################################################
Repair clock inverters
Clock Tree Synthesis
[INFO CTS-0050] Root buffer is sg13g2_buf_8.
[INFO CTS-0051] Sink buffer is sg13g2_buf_16.
[INFO CTS-0052] The following clock buffers will be used for CTS:
sg13g2_buf_2
sg13g2_buf_4
sg13g2_buf_8
sg13g2_buf_16
[INFO CTS-0049] Characterization buffer is sg13g2_buf_16.
[INFO CTS-0007] Net "clk_i" found for clock "clk_sys".
[INFO CTS-0116] Special net "clk_i" skipped.
[INFO CTS-0011] Clock net "soc_clk_i" for macros has 2 sinks.
[INFO CTS-0011] Clock net "soc_clk_i_regs" for registers has 3987 sinks.
[INFO CTS-0007] Net "jtag_tck_i" found for clock "clk_jtg".
[INFO CTS-0116] Special net "jtag_tck_i" skipped.
[INFO CTS-0011] Clock net "soc_jtag_tck_i" for macros has 1 sinks.
[INFO CTS-0011] Clock net "soc_jtag_tck_i_regs" for registers has 289 sinks.
[INFO CTS-0010] Clock net "i_croc_soc/i_croc/i_dmi_jtag/i_dmi_jtag_tap.tck_n" has 2 sinks.
[INFO CTS-0007] Net "ref_clk_i" found for clock "clk_rtc".
[INFO CTS-0116] Special net "ref_clk_i" skipped.
[WARNING CTS-0041] Net "soc_ref_clk_i" has 1 sinks. Skipping...
[INFO CTS-0008] TritonCTS found 5 clock nets.
[INFO CTS-0097] Characterization used 4 buffer(s) types.
[INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used.
[INFO CTS-0027] Generating H-Tree topology for net soc_clk_i.
[INFO CTS-0028] Total number of sinks: 2.
[INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 1569.0 um.
[INFO CTS-0030] Number of static layers: 0.
[INFO CTS-0020] Wire segment unit: 18900 dbu (18 um).
[INFO CTS-0023] Original sink region: [(952370, 463290), (952370, 1453170)].
[INFO CTS-0024] Normalized sink region: [(50.3899, 24.5127), (50.3899, 76.8873)].
[INFO CTS-0025] Width: 0.0000.
[INFO CTS-0026] Height: 52.3746.
Level 1
Direction: Vertical
Sinks per sub-region: 1
Sub-region size: 0.0000 X 26.1873
[INFO CTS-0034] Segment length (rounded): 13.
[INFO CTS-0032] Stop criterion found. Max number of sinks is 8.
[INFO CTS-0035] Number of sinks covered: 2.
[INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used.
[INFO CTS-0027] Generating H-Tree topology for net soc_clk_i_regs.
[INFO CTS-0028] Total number of sinks: 3987.
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
[INFO CTS-0030] Number of static layers: 0.
[INFO CTS-0020] Wire segment unit: 18900 dbu (18 um).
[INFO CTS-0206] Best clustering solution was found from clustering size of 8 and clustering diameter of 50.
[INFO CTS-0019] Total number of sinks after clustering: 180.
[INFO CTS-0024] Normalized sink region: [(20.4652, 26.0393), (82.992, 75.4074)].
[INFO CTS-0025] Width: 62.5268.
[INFO CTS-0026] Height: 49.3681.
Level 1
Direction: Horizontal
Sinks per sub-region: 90
Sub-region size: 31.2634 X 49.3681
[INFO CTS-0034] Segment length (rounded): 16.
Level 2
Direction: Vertical
Sinks per sub-region: 45
Sub-region size: 31.2634 X 24.6840
[INFO CTS-0034] Segment length (rounded): 12.
Level 3
Direction: Horizontal
Sinks per sub-region: 23
Sub-region size: 15.6317 X 24.6840
[INFO CTS-0034] Segment length (rounded): 8.
Level 4
Direction: Vertical
Sinks per sub-region: 12
Sub-region size: 15.6317 X 12.3420
[INFO CTS-0034] Segment length (rounded): 6.
Level 5
Direction: Horizontal
Sinks per sub-region: 6
Sub-region size: 7.8158 X 12.3420
[INFO CTS-0034] Segment length (rounded): 4.
[INFO CTS-0032] Stop criterion found. Max number of sinks is 8.
[INFO CTS-0035] Number of sinks covered: 180.
[INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used.
[INFO CTS-0027] Generating H-Tree topology for net soc_jtag_tck_i.
[INFO CTS-0028] Total number of sinks: 1.
[INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 1569.0 um.
[INFO CTS-0030] Number of static layers: 0.
[INFO CTS-0020] Wire segment unit: 18900 dbu (18 um).
[INFO CTS-0023] Original sink region: [(340596, 1079687), (340596, 1079687)].
[INFO CTS-0024] Normalized sink region: [(18.021, 57.1263), (18.021, 57.1263)].
[INFO CTS-0025] Width: 0.0000.
[INFO CTS-0026] Height: 0.0000.
Level 1
Direction: Vertical
Sinks per sub-region: 1
Sub-region size: 0.0000 X 0.0000
[INFO CTS-0034] Segment length (rounded): 1.
[INFO CTS-0032] Stop criterion found. Max number of sinks is 8.
[INFO CTS-0035] Number of sinks covered: 1.
[INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used.
[INFO CTS-0027] Generating H-Tree topology for net soc_jtag_tck_i_regs.
[INFO CTS-0028] Total number of sinks: 289.
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
[INFO CTS-0030] Number of static layers: 0.
[INFO CTS-0020] Wire segment unit: 18900 dbu (18 um).
[INFO CTS-0206] Best clustering solution was found from clustering size of 8 and clustering diameter of 50.
[INFO CTS-0019] Total number of sinks after clustering: 14.
[INFO CTS-0024] Normalized sink region: [(18.6695, 48.558), (29.5893, 59.8889)].
[INFO CTS-0025] Width: 10.9197.
[INFO CTS-0026] Height: 11.3309.
Level 1
Direction: Vertical
Sinks per sub-region: 7
Sub-region size: 10.9197 X 5.6654
[INFO CTS-0034] Segment length (rounded): 2.
[INFO CTS-0032] Stop criterion found. Max number of sinks is 8.
[INFO CTS-0035] Number of sinks covered: 14.
[INFO CTS-0201] 2 blockages from hard placement blockages and placed macros will be used.
[INFO CTS-0027] Generating H-Tree topology for net i_croc_soc\/i_croc\/i_dmi_jtag\/i_dmi_jtag_tap.tck_n.
[INFO CTS-0028] Total number of sinks: 2.
[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
[INFO CTS-0030] Number of static layers: 0.
[INFO CTS-0020] Wire segment unit: 18900 dbu (18 um).
[INFO CTS-0023] Original sink region: [(337440, 1071840), (339360, 1082760)].
[INFO CTS-0024] Normalized sink region: [(17.854, 56.7111), (17.9556, 57.2889)].
[INFO CTS-0025] Width: 0.1016.
[INFO CTS-0026] Height: 0.5778.
Level 1
Direction: Vertical
Sinks per sub-region: 1
Sub-region size: 0.1016 X 0.2889
[INFO CTS-0034] Segment length (rounded): 1.
[INFO CTS-0032] Stop criterion found. Max number of sinks is 8.
[INFO CTS-0035] Number of sinks covered: 2.
[INFO CTS-0018] Created 3 clock buffers.
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
[INFO CTS-0015] Created 3 clock nets.
[INFO CTS-0016] Fanout distribution for the current clock = 1:2..
[INFO CTS-0017] Max level of the clock tree: 1.
[INFO CTS-0018] Created 217 clock buffers.
[INFO CTS-0012] Minimum number of buffers in the clock path: 4.
[INFO CTS-0013] Maximum number of buffers in the clock path: 4.
[INFO CTS-0015] Created 217 clock nets.
[INFO CTS-0016] Fanout distribution for the current clock = 5:12, 6:20, 11:1, 14:1, 16:3, 17:4, 18:5, 19:14, 20:14, 21:21, 22:33, 23:31, 24:24, 25:13, 26:6, 27:8, 28:1, 29:1..
[INFO CTS-0017] Max level of the clock tree: 5.
[INFO CTS-0018] Created 2 clock buffers.
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
[INFO CTS-0015] Created 2 clock nets.
[INFO CTS-0016] Fanout distribution for the current clock = 1:1..
[INFO CTS-0017] Max level of the clock tree: 1.
[INFO CTS-0018] Created 17 clock buffers.
[INFO CTS-0012] Minimum number of buffers in the clock path: 3.
[INFO CTS-0013] Maximum number of buffers in the clock path: 3.
[INFO CTS-0015] Created 17 clock nets.
[INFO CTS-0016] Fanout distribution for the current clock = 7:3, 17:1, 18:3, 20:3, 22:1, 25:2, 26:2, 27:1..
[INFO CTS-0017] Max level of the clock tree: 1.
[INFO CTS-0018] Created 3 clock buffers.
[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
[INFO CTS-0015] Created 3 clock nets.
[INFO CTS-0016] Fanout distribution for the current clock = 1:2..
[INFO CTS-0017] Max level of the clock tree: 1.
[INFO CTS-0098] Clock net "soc_clk_i"
[INFO CTS-0099] Sinks 2
[INFO CTS-0100] Leaf buffers 0
[INFO CTS-0101] Average sink wire length 1342.76 um
[INFO CTS-0102] Path depth 2 - 2
[INFO CTS-0207] Dummy loads inserted 0
[INFO CTS-0098] Clock net "soc_clk_i_regs"
[INFO CTS-0099] Sinks 4138
[INFO CTS-0100] Leaf buffers 180
[INFO CTS-0101] Average sink wire length 819.05 um
[INFO CTS-0102] Path depth 3 - 4
[INFO CTS-0207] Dummy loads inserted 151
[INFO CTS-0124] Clock net "soc_jtag_tck_i"
[INFO CTS-0125] Sinks 1
[INFO CTS-0098] Clock net "soc_jtag_tck_i_regs"
[INFO CTS-0099] Sinks 301
[INFO CTS-0100] Leaf buffers 14
[INFO CTS-0101] Average sink wire length 185.05 um
[INFO CTS-0102] Path depth 3 - 3
[INFO CTS-0207] Dummy loads inserted 12
[INFO CTS-0098] Clock net "i_croc_soc\/i_croc\/i_dmi_jtag\/i_dmi_jtag_tap.tck_n"
[INFO CTS-0099] Sinks 2
[INFO CTS-0100] Leaf buffers 0
[INFO CTS-0101] Average sink wire length 37.10 um
[INFO CTS-0102] Path depth 2 - 2
[INFO CTS-0207] Dummy loads inserted 0
[INFO CTS-0033] Balancing latency for clock clk_jtg
[INFO CTS-0036] inserted 0 delay buffers
[INFO CTS-0033] Balancing latency for clock clk_sys
[INFO CTS-0036] inserted 0 delay buffers
Detailed placement
Placement Analysis
---------------------------------
total displacement 4294.2 u
average displacement 0.1 u
max displacement 12.0 u
original HPWL 1446770.6 u
legalized HPWL 1470546.3 u
delta HPWL 2 %
Estimate parasitics
Repair setup
[INFO RSZ-0100] Repair move sequence: UnbufferMove SizeUpMove SwapPinsMove BufferMove CloneMove SplitLoadMove
[INFO RSZ-0098] No setup violations found
Detailed placement
Placement Analysis
---------------------------------
total displacement 0.0 u
average displacement 0.0 u
max displacement 0.0 u
original HPWL 1470546.3 u
legalized HPWL 1470546.3 u
delta HPWL 0 %
Check placement
Estimate parasitics
Saving checkpoint 03_croc.cts
Time: 42.357376 sec deltaT: 42.282556
saving image to reports/03_croc.cts.png
[INFO GUI-0001] Command save_clocktree_image is not usable in non-GUI mode
[INFO GUI-0001] Command save_clocktree_image is not usable in non-GUI mode
[INFO GUI-0001] Command save_clocktree_image is not usable in non-GUI mode
###############################################################################
# Stage 03 complete: Checkpoint saved to save/03_croc.cts.zip
###############################################################################Screenshots
No response
Additional Context
This discrepancy was discovered during a CTS parameter sweep designed for ECE 260C at UC San Diego. We initially designed our sweep around values {10, 20, 30} based on the README documentation. After observing size 8 in the log and consulting with course staff, we learned that values below 10 are valid, this required us to redesign our experiment to include values below the auto-selected point (4, 6, 8) for a more complete exploration.
The impact of this documentation inaccuracy is that users designing CTS parameter sweeps will miss the actual operating range of the auto-selection algorithm. For example, we initially designed our sweep around {10, 20, 30} based on the README, only to discover the auto-selected value was 8, outside the documented range entirely. A correct description of the formula would allow users to make more informed decisions about which cluster sizes to explore relative to the auto-selected value for their specific design.
Source code reference: TritonCTS.cpp shows getBufferFanoutLimit() computing the minimum fanout limit and passing it to limitSinkClusteringSizes(), which determines the auto-selected cluster size.
https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/cts/src/TritonCTS.cpp
Describe the bug
The CTS README documentation states that when -sink_clustering_size is not specified, the value is automatically chosen from the set {10, 20, 30}. The exact text from src/cts/README.md is:
"If this is not specified the size will be automatically chosen between 10, 20 or 30 based on the tree buffer max cap."
When running CTS on the Croc SoC design using the IHP SG13G2 130nm open-source PDK, we observed that the auto-selected cluster size was 8, outside the documented range. Upon inspecting TritonCTS.cpp, we found that when -sink_clustering_size is not set, the clustering size is determined by the sink buffer's maximum fanout via getBufferFanoutLimit(), which takes the minimum fanout limit across SDC, Liberty port, and library defaults, and passes it to limitSinkClusteringSizes(). The resulting cluster size is therefore PDK-dependent and is not limited to {10, 20, 30} as the documentation states. This was further confirmed by course staff at UC San Diego (ECE 260C).
Expected Behavior
The documentation should correctly state that:
The documentation should correctly state that when -sink_clustering_size is not set, the clustering size is determined by the sink buffer's maximum fanout via getBufferFanoutLimit() in TritonCTS.cpp. The resulting cluster size is PDK-dependent and is not limited to {10, 20, 30}.
Suggested replacement text:
"If this is not specified, sinks will be clustered based on the sink buffer's maximum fanout. "
Environment
To Reproduce
Step 1: Clone the Croc SoC repository:
git clone https://github.com/pulp-platform/croc
cd croc
git submodule update --init --recursive
Step 2: Run synthesis and placement:
cd yosys && ./run_synthesis.sh --synth
cd ../openroad && ./run_backend.sh --floorplan
cd ../openroad && ./run_backend.sh --placement
Step 3: Run CTS with default parameters (no sink_clustering_size set):
cd openroad && ./run_backend.sh --cts
The relevant section of scripts/03_cts.tcl (attached):
Step 4: Observe the log, as seen below, auto-selected cluster size is 8, not from {10, 20, 30}:
Relevant log output
Screenshots
No response
Additional Context
This discrepancy was discovered during a CTS parameter sweep designed for ECE 260C at UC San Diego. We initially designed our sweep around values {10, 20, 30} based on the README documentation. After observing size 8 in the log and consulting with course staff, we learned that values below 10 are valid, this required us to redesign our experiment to include values below the auto-selected point (4, 6, 8) for a more complete exploration.
The impact of this documentation inaccuracy is that users designing CTS parameter sweeps will miss the actual operating range of the auto-selection algorithm. For example, we initially designed our sweep around {10, 20, 30} based on the README, only to discover the auto-selected value was 8, outside the documented range entirely. A correct description of the formula would allow users to make more informed decisions about which cluster sizes to explore relative to the auto-selected value for their specific design.
Source code reference: TritonCTS.cpp shows getBufferFanoutLimit() computing the minimum fanout limit and passing it to limitSinkClusteringSizes(), which determines the auto-selected cluster size.
https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/cts/src/TritonCTS.cpp