From 7b131661ca70a6ca19f412bd341219a7a8c2028f Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Sun, 7 Jun 2026 10:30:43 -0400 Subject: [PATCH 1/4] pad: avoid segfault when pad placement is not possible Signed-off-by: Peter Gadfort --- src/pad/src/PadPlacer.cpp | 20 +- src/pad/test/BUILD | 1 + src/pad/test/CMakeLists.txt | 1 + .../place_pads_uniform_fullyblocked.defok | 796 ++++++++++++++++++ .../test/place_pads_uniform_fullyblocked.ok | 9 + .../test/place_pads_uniform_fullyblocked.tcl | 33 + 6 files changed, 859 insertions(+), 1 deletion(-) create mode 100755 src/pad/test/place_pads_uniform_fullyblocked.defok create mode 100755 src/pad/test/place_pads_uniform_fullyblocked.ok create mode 100644 src/pad/test/place_pads_uniform_fullyblocked.tcl diff --git a/src/pad/src/PadPlacer.cpp b/src/pad/src/PadPlacer.cpp index b7f6c18d79d..79303004f5d 100644 --- a/src/pad/src/PadPlacer.cpp +++ b/src/pad/src/PadPlacer.cpp @@ -1486,7 +1486,7 @@ bool PlacerPadPlacer::padSpreading( last_idx = j; } } - bound_pos = last_idx == insts.size() + bound_pos = last_idx + 1 == insts.size() ? getRowEnd(insts[last_idx]) : positions[insts[last_idx + 1]]->center; } else { @@ -1582,10 +1582,28 @@ odb::PtrMap PlacerPadPlacer::padSpreading( : kSpringStart; const float kSpring1 = k > kSpringIterEnd ? 0 : kString2; + odb::PtrMap curr_positions; + for (const auto& [inst, anchor] : positions) { + curr_positions[inst] = anchor->center; + } if (padSpreading( positions, initial_positions, k, kSpring1, kRepel1, kDamper)) { break; } + + odb::PtrMap new_positions; + for (const auto& [inst, anchor] : positions) { + new_positions[inst] = anchor->center; + } + if (new_positions == curr_positions) { + // Place instances for better debugging + placeInstances(positions); + getLogger()->error( + utl::PAD, + 47, + "Pad placement unable to legalize pads after {} iterations.", + k); + } } // convert to regular placement information diff --git a/src/pad/test/BUILD b/src/pad/test/BUILD index d57225ce64d..afa0be6a2e7 100644 --- a/src/pad/test/BUILD +++ b/src/pad/test/BUILD @@ -40,6 +40,7 @@ COMPULSORY_TESTS = [ "place_pads_bumps_strategy_placer_blockages", "place_pads_bumps_strategy", "place_pads_too_many", + "place_pads_uniform_fullyblocked", "place_pads_uniform", "place_pads_uniform_slip", "rdl_route", diff --git a/src/pad/test/CMakeLists.txt b/src/pad/test/CMakeLists.txt index 25275ca78e6..dba36ae1fc1 100644 --- a/src/pad/test/CMakeLists.txt +++ b/src/pad/test/CMakeLists.txt @@ -33,6 +33,7 @@ or_integration_tests( place_pad_wrong_master place_pads_bumps place_pads_too_many + place_pads_uniform_fullyblocked place_pads_uniform place_pads_uniform_slip rdl_route diff --git a/src/pad/test/place_pads_uniform_fullyblocked.defok b/src/pad/test/place_pads_uniform_fullyblocked.defok new file mode 100755 index 00000000000..abb9d700f61 --- /dev/null +++ b/src/pad/test/place_pads_uniform_fullyblocked.defok @@ -0,0 +1,796 @@ +VERSION 5.8 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN soc_bsg_black_parrot ; +UNITS DISTANCE MICRONS 2000 ; +DIEAREA ( 0 0 ) ( 6000000 6000000 ) ; +ROW IO_CORNER_NORTH_WEST IOSITE 30000 5690000 FS DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_NORTH_EAST IOSITE 5690000 5690000 S DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_SOUTH_EAST IOSITE 5690000 30000 FN DO 140 BY 1 STEP 2000 0 ; +ROW IO_CORNER_SOUTH_WEST IOSITE 30000 30000 N DO 140 BY 1 STEP 2000 0 ; +ROW IO_NORTH IOSITE 310000 5690000 FS DO 2690 BY 1 STEP 2000 0 ; +ROW IO_EAST IOSITE 5690000 310000 W DO 1 BY 2690 STEP 0 2000 ; +ROW IO_SOUTH IOSITE 310000 30000 N DO 2690 BY 1 STEP 2000 0 ; +ROW IO_WEST IOSITE 30000 310000 FW DO 1 BY 2690 STEP 0 2000 ; +TRACKS X 190 DO 21428 STEP 280 LAYER metal1 ; +TRACKS Y 140 DO 21428 STEP 280 LAYER metal1 ; +TRACKS X 190 DO 15789 STEP 380 LAYER metal2 ; +TRACKS Y 140 DO 15789 STEP 380 LAYER metal2 ; +TRACKS X 190 DO 21428 STEP 280 LAYER metal3 ; +TRACKS Y 140 DO 21428 STEP 280 LAYER metal3 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal4 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal4 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal5 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal5 ; +TRACKS X 190 DO 10714 STEP 560 LAYER metal6 ; +TRACKS Y 140 DO 10714 STEP 560 LAYER metal6 ; +TRACKS X 1790 DO 3749 STEP 1600 LAYER metal7 ; +TRACKS Y 1740 DO 3749 STEP 1600 LAYER metal7 ; +TRACKS X 1790 DO 3749 STEP 1600 LAYER metal8 ; +TRACKS Y 1740 DO 3749 STEP 1600 LAYER metal8 ; +TRACKS X 3390 DO 1874 STEP 3200 LAYER metal9 ; +TRACKS Y 3340 DO 1874 STEP 3200 LAYER metal9 ; +TRACKS X 3390 DO 1874 STEP 3200 LAYER metal10 ; +TRACKS Y 3340 DO 1874 STEP 3200 LAYER metal10 ; +COMPONENTS 267 ; + - u_bsg_tag_clk_i PADCELL_SIG_H ; + - u_bsg_tag_clk_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_bsg_tag_data_i PADCELL_SIG_H ; + - u_bsg_tag_data_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_bsg_tag_en_i PADCELL_SIG_H ; + - u_ci2_0_o PADCELL_SIG_V ; + - u_ci2_1_o PADCELL_SIG_V ; + - u_ci2_2_o PADCELL_SIG_V ; + - u_ci2_3_o PADCELL_SIG_V ; + - u_ci2_4_o PADCELL_SIG_V ; + - u_ci2_5_o PADCELL_SIG_V ; + - u_ci2_6_o PADCELL_SIG_V ; + - u_ci2_7_o PADCELL_SIG_V ; + - u_ci2_8_o PADCELL_SIG_V ; + - u_ci2_clk_o PADCELL_SIG_V ; + - u_ci2_tkn_i PADCELL_SIG_V ; + - u_ci2_v_o PADCELL_SIG_V ; + - u_ci_0_i PADCELL_SIG_H ; + - u_ci_1_i PADCELL_SIG_H ; + - u_ci_2_i PADCELL_SIG_H ; + - u_ci_3_i PADCELL_SIG_H ; + - u_ci_4_i PADCELL_SIG_H ; + - u_ci_5_i PADCELL_SIG_H ; + - u_ci_6_i PADCELL_SIG_H ; + - u_ci_7_i PADCELL_SIG_H ; + - u_ci_8_i PADCELL_SIG_H ; + - u_ci_clk_i PADCELL_SIG_H ; + - u_ci_tkn_o PADCELL_SIG_H ; + - u_ci_v_i PADCELL_SIG_H ; + - u_clk_A_i PADCELL_SIG_V ; + - u_clk_B_i PADCELL_SIG_V ; + - u_clk_C_i PADCELL_SIG_V ; + - u_clk_async_reset_i PADCELL_SIG_V ; + - u_clk_o PADCELL_SIG_V ; + - u_co2_0_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_1_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_2_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_3_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_4_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_5_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_6_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_7_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_8_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_clk_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_tkn_i PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co2_v_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_co_0_i PADCELL_SIG_V ; + - u_co_1_i PADCELL_SIG_V ; + - u_co_2_i PADCELL_SIG_V ; + - u_co_3_i PADCELL_SIG_V ; + - u_co_4_i PADCELL_SIG_V ; + - u_co_5_i PADCELL_SIG_V ; + - u_co_6_i PADCELL_SIG_V ; + - u_co_7_i PADCELL_SIG_V ; + - u_co_8_i PADCELL_SIG_V ; + - u_co_clk_i PADCELL_SIG_V ; + - u_co_tkn_o PADCELL_SIG_V ; + - u_co_v_i PADCELL_SIG_V ; + - u_core_async_reset_i PADCELL_SIG_V ; + - u_ddr_addr_0_o PADCELL_SIG_V ; + - u_ddr_addr_10_o PADCELL_SIG_V ; + - u_ddr_addr_11_o PADCELL_SIG_V ; + - u_ddr_addr_12_o PADCELL_SIG_V ; + - u_ddr_addr_13_o PADCELL_SIG_V ; + - u_ddr_addr_14_o PADCELL_SIG_V ; + - u_ddr_addr_15_o PADCELL_SIG_V ; + - u_ddr_addr_1_o PADCELL_SIG_V ; + - u_ddr_addr_2_o PADCELL_SIG_V ; + - u_ddr_addr_3_o PADCELL_SIG_V ; + - u_ddr_addr_4_o PADCELL_SIG_V ; + - u_ddr_addr_5_o PADCELL_SIG_V ; + - u_ddr_addr_6_o PADCELL_SIG_V ; + - u_ddr_addr_7_o PADCELL_SIG_V ; + - u_ddr_addr_8_o PADCELL_SIG_V ; + - u_ddr_addr_9_o PADCELL_SIG_V ; + - u_ddr_ba_0_o PADCELL_SIG_V ; + - u_ddr_ba_1_o PADCELL_SIG_V ; + - u_ddr_ba_2_o PADCELL_SIG_V ; + - u_ddr_cas_n_o PADCELL_SIG_V ; + - u_ddr_ck_n_o PADCELL_SIG_V ; + - u_ddr_ck_p_o PADCELL_SIG_V ; + - u_ddr_cke_o PADCELL_SIG_V ; + - u_ddr_cs_n_o PADCELL_SIG_V ; + - u_ddr_dm_0_o PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dm_1_o PADCELL_SIG_V ; + - u_ddr_dm_2_o PADCELL_SIG_V ; + - u_ddr_dm_3_o PADCELL_SIG_H ; + - u_ddr_dq_0_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_10_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_11_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_12_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_13_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_14_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_15_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_16_io PADCELL_SIG_H ; + - u_ddr_dq_17_io PADCELL_SIG_H ; + - u_ddr_dq_18_io PADCELL_SIG_H ; + - u_ddr_dq_19_io PADCELL_SIG_H ; + - u_ddr_dq_1_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_20_io PADCELL_SIG_H ; + - u_ddr_dq_21_io PADCELL_SIG_H ; + - u_ddr_dq_22_io PADCELL_SIG_H ; + - u_ddr_dq_23_io PADCELL_SIG_H ; + - u_ddr_dq_24_io PADCELL_SIG_H ; + - u_ddr_dq_25_io PADCELL_SIG_H ; + - u_ddr_dq_26_io PADCELL_SIG_H ; + - u_ddr_dq_27_io PADCELL_SIG_H ; + - u_ddr_dq_28_io PADCELL_SIG_H ; + - u_ddr_dq_29_io PADCELL_SIG_H ; + - u_ddr_dq_2_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_30_io PADCELL_SIG_H ; + - u_ddr_dq_31_io PADCELL_SIG_H ; + - u_ddr_dq_3_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_4_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_5_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_6_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_7_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_8_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dq_9_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dqs_n_0_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dqs_n_1_io PADCELL_SIG_V ; + - u_ddr_dqs_n_2_io PADCELL_SIG_V ; + - u_ddr_dqs_n_3_io PADCELL_SIG_H ; + - u_ddr_dqs_p_0_io PADCELL_SIG_H + PLACED ( 30000 5640000 ) FW ; + - u_ddr_dqs_p_1_io PADCELL_SIG_V ; + - u_ddr_dqs_p_2_io PADCELL_SIG_V ; + - u_ddr_dqs_p_3_io PADCELL_SIG_H ; + - u_ddr_odt_o PADCELL_SIG_V ; + - u_ddr_ras_n_o PADCELL_SIG_V ; + - u_ddr_reset_n_o PADCELL_SIG_V ; + - u_ddr_we_n_o PADCELL_SIG_V ; + - u_misc_o PADCELL_SIG_V ; + - u_sel_0_i PADCELL_SIG_V ; + - u_sel_1_i PADCELL_SIG_V ; + - u_sel_2_i PADCELL_SIG_V ; + - u_v18_1 PADCELL_VDDIO_V ; + - u_v18_10 PADCELL_VDDIO_H ; + - u_v18_11 PADCELL_VDDIO_H ; + - u_v18_12 PADCELL_VDDIO_H ; + - u_v18_13 PADCELL_VDDIO_H ; + - u_v18_14 PADCELL_VDDIO_H ; + - u_v18_15 PADCELL_VDDIO_H ; + - u_v18_16 PADCELL_VDDIO_H ; + - u_v18_17 PADCELL_VDDIO_V ; + - u_v18_18 PADCELL_VDDIO_V ; + - u_v18_19 PADCELL_VDDIO_V ; + - u_v18_2 PADCELL_VDDIO_V ; + - u_v18_20 PADCELL_VDDIO_V ; + - u_v18_21 PADCELL_VDDIO_V ; + - u_v18_22 PADCELL_VDDIO_V ; + - u_v18_23 PADCELL_VDDIO_V ; + - u_v18_24 PADCELL_VDDIO_V ; + - u_v18_25 PADCELL_VDDIO_H ; + - u_v18_26 PADCELL_VDDIO_H + PLACED ( 30000 5640000 ) FW ; + - u_v18_27 PADCELL_VDDIO_H + PLACED ( 30000 5640000 ) FW ; + - u_v18_28 PADCELL_VDDIO_H + PLACED ( 30000 5640000 ) FW ; + - u_v18_29 PADCELL_VDDIO_H + PLACED ( 30000 5640000 ) FW ; + - u_v18_3 PADCELL_VDDIO_V ; + - u_v18_30 PADCELL_VDDIO_H + PLACED ( 30000 5640000 ) FW ; + - u_v18_31 PADCELL_VDDIO_H + PLACED ( 30000 5640000 ) FW ; + - u_v18_32 PADCELL_VDDIO_H + PLACED ( 30000 5640000 ) FW ; + - u_v18_4 PADCELL_VDDIO_V ; + - u_v18_5 PADCELL_VDDIO_V ; + - u_v18_6 PADCELL_VDDIO_V ; + - u_v18_7 PADCELL_VDDIO_V ; + - u_v18_8 PADCELL_VDDIO_V ; + - u_v18_9 PADCELL_VDDIO_H ; + - u_vdd_1 PADCELL_VDD_V ; + - u_vdd_10 PADCELL_VDD_H ; + - u_vdd_11 PADCELL_VDD_H ; + - u_vdd_12 PADCELL_VDD_H + PLACED ( 30000 5640000 ) FW ; + - u_vdd_13 PADCELL_VDD_H + PLACED ( 30000 5640000 ) FW ; + - u_vdd_14 PADCELL_VDD_H + PLACED ( 30000 5640000 ) FW ; + - u_vdd_15 PADCELL_VDD_H + PLACED ( 30000 5640000 ) FW ; + - u_vdd_16 PADCELL_VDD_H ; + - u_vdd_17 PADCELL_VDD_V ; + - u_vdd_18 PADCELL_VDD_V ; + - u_vdd_19 PADCELL_VDD_V ; + - u_vdd_2 PADCELL_VDD_V ; + - u_vdd_20 PADCELL_VDD_V ; + - u_vdd_21 PADCELL_VDD_V ; + - u_vdd_22 PADCELL_VDD_V ; + - u_vdd_23 PADCELL_VDD_V ; + - u_vdd_24 PADCELL_VDD_V ; + - u_vdd_25 PADCELL_VDD_H ; + - u_vdd_26 PADCELL_VDD_H ; + - u_vdd_27 PADCELL_VDD_H ; + - u_vdd_28 PADCELL_VDD_H ; + - u_vdd_29 PADCELL_VDD_H ; + - u_vdd_3 PADCELL_VDD_V ; + - u_vdd_30 PADCELL_VDD_H ; + - u_vdd_31 PADCELL_VDD_H ; + - u_vdd_32 PADCELL_VDD_H ; + - u_vdd_4 PADCELL_VDD_V ; + - u_vdd_5 PADCELL_VDD_V ; + - u_vdd_6 PADCELL_VDD_V ; + - u_vdd_7 PADCELL_VDD_V ; + - u_vdd_8 PADCELL_VDD_H ; + - u_vdd_9 PADCELL_VDD_H ; + - u_vdd_pll PADCELL_VDD_V ; + - u_vss_0 PADCELL_VSS_V ; + - u_vss_1 PADCELL_VSS_V ; + - u_vss_10 PADCELL_VSS_H ; + - u_vss_11 PADCELL_VSS_H ; + - u_vss_12 PADCELL_VSS_H + PLACED ( 30000 5640000 ) FW ; + - u_vss_13 PADCELL_VSS_H + PLACED ( 30000 5640000 ) FW ; + - u_vss_14 PADCELL_VSS_H + PLACED ( 30000 5640000 ) FW ; + - u_vss_15 PADCELL_VSS_H + PLACED ( 30000 5640000 ) FW ; + - u_vss_16 PADCELL_VSS_H ; + - u_vss_17 PADCELL_VSS_V ; + - u_vss_18 PADCELL_VSS_V ; + - u_vss_19 PADCELL_VSS_V ; + - u_vss_2 PADCELL_VSS_V ; + - u_vss_20 PADCELL_VSS_V ; + - u_vss_21 PADCELL_VSS_V ; + - u_vss_22 PADCELL_VSS_V ; + - u_vss_23 PADCELL_VSS_V ; + - u_vss_24 PADCELL_VSS_V ; + - u_vss_25 PADCELL_VSS_H ; + - u_vss_26 PADCELL_VSS_H ; + - u_vss_27 PADCELL_VSS_H ; + - u_vss_28 PADCELL_VSS_H ; + - u_vss_29 PADCELL_VSS_H ; + - u_vss_3 PADCELL_VSS_V ; + - u_vss_30 PADCELL_VSS_H ; + - u_vss_31 PADCELL_VSS_H ; + - u_vss_32 PADCELL_VSS_H ; + - u_vss_4 PADCELL_VSS_V ; + - u_vss_5 PADCELL_VSS_V ; + - u_vss_6 PADCELL_VSS_V ; + - u_vss_7 PADCELL_VSS_V ; + - u_vss_8 PADCELL_VSS_H ; + - u_vss_9 PADCELL_VSS_H ; + - u_vss_pll PADCELL_VSS_V ; + - u_vzz_0 PADCELL_VSSIO_V ; + - u_vzz_1 PADCELL_VSSIO_V ; + - u_vzz_10 PADCELL_VSSIO_H ; + - u_vzz_11 PADCELL_VSSIO_H ; + - u_vzz_12 PADCELL_VSSIO_H ; + - u_vzz_13 PADCELL_VSSIO_H ; + - u_vzz_14 PADCELL_VSSIO_H ; + - u_vzz_15 PADCELL_VSSIO_H ; + - u_vzz_16 PADCELL_VSSIO_H ; + - u_vzz_17 PADCELL_VSSIO_V ; + - u_vzz_18 PADCELL_VSSIO_V ; + - u_vzz_19 PADCELL_VSSIO_V ; + - u_vzz_2 PADCELL_VSSIO_V ; + - u_vzz_20 PADCELL_VSSIO_V ; + - u_vzz_21 PADCELL_VSSIO_V ; + - u_vzz_22 PADCELL_VSSIO_V ; + - u_vzz_23 PADCELL_VSSIO_V ; + - u_vzz_24 PADCELL_VSSIO_V ; + - u_vzz_25 PADCELL_VSSIO_H ; + - u_vzz_26 PADCELL_VSSIO_H + PLACED ( 30000 5640000 ) FW ; + - u_vzz_27 PADCELL_VSSIO_H + PLACED ( 30000 5640000 ) FW ; + - u_vzz_28 PADCELL_VSSIO_H + PLACED ( 30000 5640000 ) FW ; + - u_vzz_29 PADCELL_VSSIO_H + PLACED ( 30000 5640000 ) FW ; + - u_vzz_3 PADCELL_VSSIO_V ; + - u_vzz_30 PADCELL_VSSIO_H + PLACED ( 30000 5640000 ) FW ; + - u_vzz_31 PADCELL_VSSIO_H + PLACED ( 30000 5640000 ) FW ; + - u_vzz_32 PADCELL_VSSIO_H + PLACED ( 30000 5640000 ) FW ; + - u_vzz_4 PADCELL_VSSIO_V ; + - u_vzz_5 PADCELL_VSSIO_V ; + - u_vzz_6 PADCELL_VSSIO_V ; + - u_vzz_7 PADCELL_VSSIO_V ; + - u_vzz_8 PADCELL_VSSIO_V ; + - u_vzz_9 PADCELL_VSSIO_H ; +END COMPONENTS +PINS 135 ; + - p_bsg_tag_clk_i + NET p_bsg_tag_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_bsg_tag_clk_o + NET p_bsg_tag_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_bsg_tag_data_i + NET p_bsg_tag_data_i + DIRECTION INPUT + USE SIGNAL ; + - p_bsg_tag_data_o + NET p_bsg_tag_data_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_bsg_tag_en_i + NET p_bsg_tag_en_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci2_0_o + NET p_ci2_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_1_o + NET p_ci2_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_2_o + NET p_ci2_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_3_o + NET p_ci2_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_4_o + NET p_ci2_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_5_o + NET p_ci2_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_6_o + NET p_ci2_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_7_o + NET p_ci2_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_8_o + NET p_ci2_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_clk_o + NET p_ci2_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci2_tkn_i + NET p_ci2_tkn_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci2_v_o + NET p_ci2_v_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci_0_i + NET p_ci_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_1_i + NET p_ci_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_2_i + NET p_ci_2_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_3_i + NET p_ci_3_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_4_i + NET p_ci_4_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_5_i + NET p_ci_5_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_6_i + NET p_ci_6_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_7_i + NET p_ci_7_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_8_i + NET p_ci_8_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_clk_i + NET p_ci_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_ci_tkn_o + NET p_ci_tkn_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ci_v_i + NET p_ci_v_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_A_i + NET p_clk_A_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_B_i + NET p_clk_B_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_C_i + NET p_clk_C_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_async_reset_i + NET p_clk_async_reset_i + DIRECTION INPUT + USE SIGNAL ; + - p_clk_o + NET p_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_0_o + NET p_co2_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_1_o + NET p_co2_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_2_o + NET p_co2_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_3_o + NET p_co2_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_4_o + NET p_co2_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_5_o + NET p_co2_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_6_o + NET p_co2_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_7_o + NET p_co2_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_8_o + NET p_co2_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_clk_o + NET p_co2_clk_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co2_tkn_i + NET p_co2_tkn_i + DIRECTION INPUT + USE SIGNAL ; + - p_co2_v_o + NET p_co2_v_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co_0_i + NET p_co_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_1_i + NET p_co_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_2_i + NET p_co_2_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_3_i + NET p_co_3_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_4_i + NET p_co_4_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_5_i + NET p_co_5_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_6_i + NET p_co_6_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_7_i + NET p_co_7_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_8_i + NET p_co_8_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_clk_i + NET p_co_clk_i + DIRECTION INPUT + USE SIGNAL ; + - p_co_tkn_o + NET p_co_tkn_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_co_v_i + NET p_co_v_i + DIRECTION INPUT + USE SIGNAL ; + - p_core_async_reset_i + NET p_core_async_reset_i + DIRECTION INPUT + USE SIGNAL ; + - p_ddr_addr_0_o + NET p_ddr_addr_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_10_o + NET p_ddr_addr_10_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_11_o + NET p_ddr_addr_11_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_12_o + NET p_ddr_addr_12_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_13_o + NET p_ddr_addr_13_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_14_o + NET p_ddr_addr_14_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_15_o + NET p_ddr_addr_15_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_1_o + NET p_ddr_addr_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_2_o + NET p_ddr_addr_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_3_o + NET p_ddr_addr_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_4_o + NET p_ddr_addr_4_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_5_o + NET p_ddr_addr_5_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_6_o + NET p_ddr_addr_6_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_7_o + NET p_ddr_addr_7_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_8_o + NET p_ddr_addr_8_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_addr_9_o + NET p_ddr_addr_9_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_0_o + NET p_ddr_ba_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_1_o + NET p_ddr_ba_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ba_2_o + NET p_ddr_ba_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cas_n_o + NET p_ddr_cas_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ck_n_o + NET p_ddr_ck_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ck_p_o + NET p_ddr_ck_p_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cke_o + NET p_ddr_cke_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_cs_n_o + NET p_ddr_cs_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_0_o + NET p_ddr_dm_0_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_1_o + NET p_ddr_dm_1_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_2_o + NET p_ddr_dm_2_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dm_3_o + NET p_ddr_dm_3_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_dq_0_io + NET p_ddr_dq_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_10_io + NET p_ddr_dq_10_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_11_io + NET p_ddr_dq_11_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_12_io + NET p_ddr_dq_12_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_13_io + NET p_ddr_dq_13_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_14_io + NET p_ddr_dq_14_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_15_io + NET p_ddr_dq_15_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_16_io + NET p_ddr_dq_16_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_17_io + NET p_ddr_dq_17_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_18_io + NET p_ddr_dq_18_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_19_io + NET p_ddr_dq_19_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_1_io + NET p_ddr_dq_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_20_io + NET p_ddr_dq_20_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_21_io + NET p_ddr_dq_21_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_22_io + NET p_ddr_dq_22_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_23_io + NET p_ddr_dq_23_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_24_io + NET p_ddr_dq_24_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_25_io + NET p_ddr_dq_25_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_26_io + NET p_ddr_dq_26_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_27_io + NET p_ddr_dq_27_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_28_io + NET p_ddr_dq_28_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_29_io + NET p_ddr_dq_29_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_2_io + NET p_ddr_dq_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_30_io + NET p_ddr_dq_30_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_31_io + NET p_ddr_dq_31_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_3_io + NET p_ddr_dq_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_4_io + NET p_ddr_dq_4_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_5_io + NET p_ddr_dq_5_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_6_io + NET p_ddr_dq_6_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_7_io + NET p_ddr_dq_7_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_8_io + NET p_ddr_dq_8_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dq_9_io + NET p_ddr_dq_9_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_0_io + NET p_ddr_dqs_n_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_1_io + NET p_ddr_dqs_n_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_2_io + NET p_ddr_dqs_n_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_n_3_io + NET p_ddr_dqs_n_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_0_io + NET p_ddr_dqs_p_0_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_1_io + NET p_ddr_dqs_p_1_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_2_io + NET p_ddr_dqs_p_2_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_dqs_p_3_io + NET p_ddr_dqs_p_3_io + DIRECTION INOUT + USE SIGNAL ; + - p_ddr_odt_o + NET p_ddr_odt_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_ras_n_o + NET p_ddr_ras_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_reset_n_o + NET p_ddr_reset_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_ddr_we_n_o + NET p_ddr_we_n_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_misc_o + NET p_misc_o + DIRECTION OUTPUT + USE SIGNAL ; + - p_sel_0_i + NET p_sel_0_i + DIRECTION INPUT + USE SIGNAL ; + - p_sel_1_i + NET p_sel_1_i + DIRECTION INPUT + USE SIGNAL ; + - p_sel_2_i + NET p_sel_2_i + DIRECTION INPUT + USE SIGNAL ; +END PINS +BLOCKAGES 1 ; + - LAYER metal10 RECT ( 0 0 ) ( 200000 6000000 ) ; +END BLOCKAGES +NETS 350 ; + - core_bsg_tag_clk_i ( u_bsg_tag_clk_i Y ) + USE SIGNAL ; + - core_bsg_tag_clk_o ( u_bsg_tag_clk_o A ) + USE SIGNAL ; + - core_bsg_tag_data_i ( u_bsg_tag_data_i Y ) + USE SIGNAL ; + - core_bsg_tag_data_o ( u_bsg_tag_data_o A ) + USE SIGNAL ; + - core_bsg_tag_en_i ( u_bsg_tag_en_i Y ) + USE SIGNAL ; + - core_ci2_0_o ( u_ci2_0_o A ) + USE SIGNAL ; + - core_ci2_1_o ( u_ci2_1_o A ) + USE SIGNAL ; + - core_ci2_2_o ( u_ci2_2_o A ) + USE SIGNAL ; + - core_ci2_3_o ( u_ci2_3_o A ) + USE SIGNAL ; + - core_ci2_4_o ( u_ci2_4_o A ) + USE SIGNAL ; + - core_ci2_5_o ( u_ci2_5_o A ) + USE SIGNAL ; + - core_ci2_6_o ( u_ci2_6_o A ) + USE SIGNAL ; + - core_ci2_7_o ( u_ci2_7_o A ) + USE SIGNAL ; + - core_ci2_8_o ( u_ci2_8_o A ) + USE SIGNAL ; + - core_ci2_clk_o ( u_ci2_clk_o A ) + USE SIGNAL ; + - core_ci2_tkn_i ( u_ci2_tkn_i Y ) + USE SIGNAL ; + - core_ci2_v_o ( u_ci2_v_o A ) + USE SIGNAL ; + - core_ci_0_i ( u_ci_0_i Y ) + USE SIGNAL ; + - core_ci_1_i ( u_ci_1_i Y ) + USE SIGNAL ; + - core_ci_2_i ( u_ci_2_i Y ) + USE SIGNAL ; + - core_ci_3_i ( u_ci_3_i Y ) + USE SIGNAL ; + - core_ci_4_i ( u_ci_4_i Y ) + USE SIGNAL ; + - core_ci_5_i ( u_ci_5_i Y ) + USE SIGNAL ; + - core_ci_6_i ( u_ci_6_i Y ) + USE SIGNAL ; + - core_ci_7_i ( u_ci_7_i Y ) + USE SIGNAL ; + - core_ci_8_i ( u_ci_8_i Y ) + USE SIGNAL ; + - core_ci_clk_i ( u_ci_clk_i Y ) + USE SIGNAL ; + - core_ci_tkn_o ( u_ci_tkn_o A ) + USE SIGNAL ; + - core_ci_v_i ( u_ci_v_i Y ) + USE SIGNAL ; + - core_clk_A_i ( u_clk_A_i Y ) + USE SIGNAL ; + - core_clk_B_i ( u_clk_B_i Y ) + USE SIGNAL ; + - core_clk_C_i ( u_clk_C_i Y ) + USE SIGNAL ; + - core_clk_async_reset_i ( u_clk_async_reset_i Y ) + USE SIGNAL ; + - core_clk_o ( u_clk_o A ) + USE SIGNAL ; + - core_co2_0_o ( u_co2_0_o A ) + USE SIGNAL ; + - core_co2_1_o ( u_co2_1_o A ) + USE SIGNAL ; + - core_co2_2_o ( u_co2_2_o A ) + USE SIGNAL ; + - core_co2_3_o ( u_co2_3_o A ) + USE SIGNAL ; + - core_co2_4_o ( u_co2_4_o A ) + USE SIGNAL ; + - core_co2_5_o ( u_co2_5_o A ) + USE SIGNAL ; + - core_co2_6_o ( u_co2_6_o A ) + USE SIGNAL ; + - core_co2_7_o ( u_co2_7_o A ) + USE SIGNAL ; + - core_co2_8_o ( u_co2_8_o A ) + USE SIGNAL ; + - core_co2_clk_o ( u_co2_clk_o A ) + USE SIGNAL ; + - core_co2_tkn_i ( u_co2_tkn_i Y ) + USE SIGNAL ; + - core_co2_v_o ( u_co2_v_o A ) + USE SIGNAL ; + - core_co_0_i ( u_co_0_i Y ) + USE SIGNAL ; + - core_co_1_i ( u_co_1_i Y ) + USE SIGNAL ; + - core_co_2_i ( u_co_2_i Y ) + USE SIGNAL ; + - core_co_3_i ( u_co_3_i Y ) + USE SIGNAL ; + - core_co_4_i ( u_co_4_i Y ) + USE SIGNAL ; + - core_co_5_i ( u_co_5_i Y ) + USE SIGNAL ; + - core_co_6_i ( u_co_6_i Y ) + USE SIGNAL ; + - core_co_7_i ( u_co_7_i Y ) + USE SIGNAL ; + - core_co_8_i ( u_co_8_i Y ) + USE SIGNAL ; + - core_co_clk_i ( u_co_clk_i Y ) + USE SIGNAL ; + - core_co_tkn_o ( u_co_tkn_o A ) + USE SIGNAL ; + - core_co_v_i ( u_co_v_i Y ) + USE SIGNAL ; + - core_core_async_reset_i ( u_core_async_reset_i Y ) + USE SIGNAL ; + - core_ddr_addr_0_o ( u_ddr_addr_0_o A ) + USE SIGNAL ; + - core_ddr_addr_10_o ( u_ddr_addr_10_o A ) + USE SIGNAL ; + - core_ddr_addr_11_o ( u_ddr_addr_11_o A ) + USE SIGNAL ; + - core_ddr_addr_12_o ( u_ddr_addr_12_o A ) + USE SIGNAL ; + - core_ddr_addr_13_o ( u_ddr_addr_13_o A ) + USE SIGNAL ; + - core_ddr_addr_14_o ( u_ddr_addr_14_o A ) + USE SIGNAL ; + - core_ddr_addr_15_o ( u_ddr_addr_15_o A ) + USE SIGNAL ; + - core_ddr_addr_1_o ( u_ddr_addr_1_o A ) + USE SIGNAL ; + - core_ddr_addr_2_o ( u_ddr_addr_2_o A ) + USE SIGNAL ; + - core_ddr_addr_3_o ( u_ddr_addr_3_o A ) + USE SIGNAL ; + - core_ddr_addr_4_o ( u_ddr_addr_4_o A ) + USE SIGNAL ; + - core_ddr_addr_5_o ( u_ddr_addr_5_o A ) + USE SIGNAL ; + - core_ddr_addr_6_o ( u_ddr_addr_6_o A ) + USE SIGNAL ; + - core_ddr_addr_7_o ( u_ddr_addr_7_o A ) + USE SIGNAL ; + - core_ddr_addr_8_o ( u_ddr_addr_8_o A ) + USE SIGNAL ; + - core_ddr_addr_9_o ( u_ddr_addr_9_o A ) + USE SIGNAL ; + - core_ddr_ba_0_o ( u_ddr_ba_0_o A ) + USE SIGNAL ; + - core_ddr_ba_1_o ( u_ddr_ba_1_o A ) + USE SIGNAL ; + - core_ddr_ba_2_o ( u_ddr_ba_2_o A ) + USE SIGNAL ; + - core_ddr_cas_n_o ( u_ddr_cas_n_o A ) + USE SIGNAL ; + - core_ddr_ck_n_o ( u_ddr_ck_n_o A ) + USE SIGNAL ; + - core_ddr_ck_p_o ( u_ddr_ck_p_o A ) + USE SIGNAL ; + - core_ddr_cke_o ( u_ddr_cke_o A ) + USE SIGNAL ; + - core_ddr_cs_n_o ( u_ddr_cs_n_o A ) + USE SIGNAL ; + - core_ddr_dm_0_o ( u_ddr_dm_0_o A ) + USE SIGNAL ; + - core_ddr_dm_1_o ( u_ddr_dm_1_o A ) + USE SIGNAL ; + - core_ddr_dm_2_o ( u_ddr_dm_2_o A ) + USE SIGNAL ; + - core_ddr_dm_3_o ( u_ddr_dm_3_o A ) + USE SIGNAL ; + - core_ddr_dq_0_i ( u_ddr_dq_0_io Y ) + USE SIGNAL ; + - core_ddr_dq_0_o ( u_ddr_dq_0_io A ) + USE SIGNAL ; + - core_ddr_dq_0_sel ( u_ddr_dq_0_io PU ) ( u_ddr_dq_0_io OE ) + USE SIGNAL ; + - core_ddr_dq_10_i ( u_ddr_dq_10_io Y ) + USE SIGNAL ; + - core_ddr_dq_10_o ( u_ddr_dq_10_io A ) + USE SIGNAL ; + - core_ddr_dq_10_sel ( u_ddr_dq_10_io PU ) ( u_ddr_dq_10_io OE ) + USE SIGNAL ; + - core_ddr_dq_11_i ( u_ddr_dq_11_io Y ) + USE SIGNAL ; + - core_ddr_dq_11_o ( u_ddr_dq_11_io A ) + USE SIGNAL ; + - core_ddr_dq_11_sel ( u_ddr_dq_11_io PU ) ( u_ddr_dq_11_io OE ) + USE SIGNAL ; + - core_ddr_dq_12_i ( u_ddr_dq_12_io Y ) + USE SIGNAL ; + - core_ddr_dq_12_o ( u_ddr_dq_12_io A ) + USE SIGNAL ; + - core_ddr_dq_12_sel ( u_ddr_dq_12_io PU ) ( u_ddr_dq_12_io OE ) + USE SIGNAL ; + - core_ddr_dq_13_i ( u_ddr_dq_13_io Y ) + USE SIGNAL ; + - core_ddr_dq_13_o ( u_ddr_dq_13_io A ) + USE SIGNAL ; + - core_ddr_dq_13_sel ( u_ddr_dq_13_io PU ) ( u_ddr_dq_13_io OE ) + USE SIGNAL ; + - core_ddr_dq_14_i ( u_ddr_dq_14_io Y ) + USE SIGNAL ; + - core_ddr_dq_14_o ( u_ddr_dq_14_io A ) + USE SIGNAL ; + - core_ddr_dq_14_sel ( u_ddr_dq_14_io PU ) ( u_ddr_dq_14_io OE ) + USE SIGNAL ; + - core_ddr_dq_15_i ( u_ddr_dq_15_io Y ) + USE SIGNAL ; + - core_ddr_dq_15_o ( u_ddr_dq_15_io A ) + USE SIGNAL ; + - core_ddr_dq_15_sel ( u_ddr_dq_15_io PU ) ( u_ddr_dq_15_io OE ) + USE SIGNAL ; + - core_ddr_dq_16_i ( u_ddr_dq_16_io Y ) + USE SIGNAL ; + - core_ddr_dq_16_o ( u_ddr_dq_16_io A ) + USE SIGNAL ; + - core_ddr_dq_16_sel ( u_ddr_dq_16_io PU ) ( u_ddr_dq_16_io OE ) + USE SIGNAL ; + - core_ddr_dq_17_i ( u_ddr_dq_17_io Y ) + USE SIGNAL ; + - core_ddr_dq_17_o ( u_ddr_dq_17_io A ) + USE SIGNAL ; + - core_ddr_dq_17_sel ( u_ddr_dq_17_io PU ) ( u_ddr_dq_17_io OE ) + USE SIGNAL ; + - core_ddr_dq_18_i ( u_ddr_dq_18_io Y ) + USE SIGNAL ; + - core_ddr_dq_18_o ( u_ddr_dq_18_io A ) + USE SIGNAL ; + - core_ddr_dq_18_sel ( u_ddr_dq_18_io PU ) ( u_ddr_dq_18_io OE ) + USE SIGNAL ; + - core_ddr_dq_19_i ( u_ddr_dq_19_io Y ) + USE SIGNAL ; + - core_ddr_dq_19_o ( u_ddr_dq_19_io A ) + USE SIGNAL ; + - core_ddr_dq_19_sel ( u_ddr_dq_19_io PU ) ( u_ddr_dq_19_io OE ) + USE SIGNAL ; + - core_ddr_dq_1_i ( u_ddr_dq_1_io Y ) + USE SIGNAL ; + - core_ddr_dq_1_o ( u_ddr_dq_1_io A ) + USE SIGNAL ; + - core_ddr_dq_1_sel ( u_ddr_dq_1_io PU ) ( u_ddr_dq_1_io OE ) + USE SIGNAL ; + - core_ddr_dq_20_i ( u_ddr_dq_20_io Y ) + USE SIGNAL ; + - core_ddr_dq_20_o ( u_ddr_dq_20_io A ) + USE SIGNAL ; + - core_ddr_dq_20_sel ( u_ddr_dq_20_io PU ) ( u_ddr_dq_20_io OE ) + USE SIGNAL ; + - core_ddr_dq_21_i ( u_ddr_dq_21_io Y ) + USE SIGNAL ; + - core_ddr_dq_21_o ( u_ddr_dq_21_io A ) + USE SIGNAL ; + - core_ddr_dq_21_sel ( u_ddr_dq_21_io PU ) ( u_ddr_dq_21_io OE ) + USE SIGNAL ; + - core_ddr_dq_22_i ( u_ddr_dq_22_io Y ) + USE SIGNAL ; + - core_ddr_dq_22_o ( u_ddr_dq_22_io A ) + USE SIGNAL ; + - core_ddr_dq_22_sel ( u_ddr_dq_22_io PU ) ( u_ddr_dq_22_io OE ) + USE SIGNAL ; + - core_ddr_dq_23_i ( u_ddr_dq_23_io Y ) + USE SIGNAL ; + - core_ddr_dq_23_o ( u_ddr_dq_23_io A ) + USE SIGNAL ; + - core_ddr_dq_23_sel ( u_ddr_dq_23_io PU ) ( u_ddr_dq_23_io OE ) + USE SIGNAL ; + - core_ddr_dq_24_i ( u_ddr_dq_24_io Y ) + USE SIGNAL ; + - core_ddr_dq_24_o ( u_ddr_dq_24_io A ) + USE SIGNAL ; + - core_ddr_dq_24_sel ( u_ddr_dq_24_io PU ) ( u_ddr_dq_24_io OE ) + USE SIGNAL ; + - core_ddr_dq_25_i ( u_ddr_dq_25_io Y ) + USE SIGNAL ; + - core_ddr_dq_25_o ( u_ddr_dq_25_io A ) + USE SIGNAL ; + - core_ddr_dq_25_sel ( u_ddr_dq_25_io PU ) ( u_ddr_dq_25_io OE ) + USE SIGNAL ; + - core_ddr_dq_26_i ( u_ddr_dq_26_io Y ) + USE SIGNAL ; + - core_ddr_dq_26_o ( u_ddr_dq_26_io A ) + USE SIGNAL ; + - core_ddr_dq_26_sel ( u_ddr_dq_26_io PU ) ( u_ddr_dq_26_io OE ) + USE SIGNAL ; + - core_ddr_dq_27_i ( u_ddr_dq_27_io Y ) + USE SIGNAL ; + - core_ddr_dq_27_o ( u_ddr_dq_27_io A ) + USE SIGNAL ; + - core_ddr_dq_27_sel ( u_ddr_dq_27_io PU ) ( u_ddr_dq_27_io OE ) + USE SIGNAL ; + - core_ddr_dq_28_i ( u_ddr_dq_28_io Y ) + USE SIGNAL ; + - core_ddr_dq_28_o ( u_ddr_dq_28_io A ) + USE SIGNAL ; + - core_ddr_dq_28_sel ( u_ddr_dq_28_io PU ) ( u_ddr_dq_28_io OE ) + USE SIGNAL ; + - core_ddr_dq_29_i ( u_ddr_dq_29_io Y ) + USE SIGNAL ; + - core_ddr_dq_29_o ( u_ddr_dq_29_io A ) + USE SIGNAL ; + - core_ddr_dq_29_sel ( u_ddr_dq_29_io PU ) ( u_ddr_dq_29_io OE ) + USE SIGNAL ; + - core_ddr_dq_2_i ( u_ddr_dq_2_io Y ) + USE SIGNAL ; + - core_ddr_dq_2_o ( u_ddr_dq_2_io A ) + USE SIGNAL ; + - core_ddr_dq_2_sel ( u_ddr_dq_2_io PU ) ( u_ddr_dq_2_io OE ) + USE SIGNAL ; + - core_ddr_dq_30_i ( u_ddr_dq_30_io Y ) + USE SIGNAL ; + - core_ddr_dq_30_o ( u_ddr_dq_30_io A ) + USE SIGNAL ; + - core_ddr_dq_30_sel ( u_ddr_dq_30_io PU ) ( u_ddr_dq_30_io OE ) + USE SIGNAL ; + - core_ddr_dq_31_i ( u_ddr_dq_31_io Y ) + USE SIGNAL ; + - core_ddr_dq_31_o ( u_ddr_dq_31_io A ) + USE SIGNAL ; + - core_ddr_dq_31_sel ( u_ddr_dq_31_io PU ) ( u_ddr_dq_31_io OE ) + USE SIGNAL ; + - core_ddr_dq_3_i ( u_ddr_dq_3_io Y ) + USE SIGNAL ; + - core_ddr_dq_3_o ( u_ddr_dq_3_io A ) + USE SIGNAL ; + - core_ddr_dq_3_sel ( u_ddr_dq_3_io PU ) ( u_ddr_dq_3_io OE ) + USE SIGNAL ; + - core_ddr_dq_4_i ( u_ddr_dq_4_io Y ) + USE SIGNAL ; + - core_ddr_dq_4_o ( u_ddr_dq_4_io A ) + USE SIGNAL ; + - core_ddr_dq_4_sel ( u_ddr_dq_4_io PU ) ( u_ddr_dq_4_io OE ) + USE SIGNAL ; + - core_ddr_dq_5_i ( u_ddr_dq_5_io Y ) + USE SIGNAL ; + - core_ddr_dq_5_o ( u_ddr_dq_5_io A ) + USE SIGNAL ; + - core_ddr_dq_5_sel ( u_ddr_dq_5_io PU ) ( u_ddr_dq_5_io OE ) + USE SIGNAL ; + - core_ddr_dq_6_i ( u_ddr_dq_6_io Y ) + USE SIGNAL ; + - core_ddr_dq_6_o ( u_ddr_dq_6_io A ) + USE SIGNAL ; + - core_ddr_dq_6_sel ( u_ddr_dq_6_io PU ) ( u_ddr_dq_6_io OE ) + USE SIGNAL ; + - core_ddr_dq_7_i ( u_ddr_dq_7_io Y ) + USE SIGNAL ; + - core_ddr_dq_7_o ( u_ddr_dq_7_io A ) + USE SIGNAL ; + - core_ddr_dq_7_sel ( u_ddr_dq_7_io PU ) ( u_ddr_dq_7_io OE ) + USE SIGNAL ; + - core_ddr_dq_8_i ( u_ddr_dq_8_io Y ) + USE SIGNAL ; + - core_ddr_dq_8_o ( u_ddr_dq_8_io A ) + USE SIGNAL ; + - core_ddr_dq_8_sel ( u_ddr_dq_8_io PU ) ( u_ddr_dq_8_io OE ) + USE SIGNAL ; + - core_ddr_dq_9_i ( u_ddr_dq_9_io Y ) + USE SIGNAL ; + - core_ddr_dq_9_o ( u_ddr_dq_9_io A ) + USE SIGNAL ; + - core_ddr_dq_9_sel ( u_ddr_dq_9_io PU ) ( u_ddr_dq_9_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_0_i ( u_ddr_dqs_n_0_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_0_o ( u_ddr_dqs_n_0_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_0_sel ( u_ddr_dqs_n_0_io PU ) ( u_ddr_dqs_n_0_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_1_i ( u_ddr_dqs_n_1_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_1_o ( u_ddr_dqs_n_1_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_1_sel ( u_ddr_dqs_n_1_io PU ) ( u_ddr_dqs_n_1_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_2_i ( u_ddr_dqs_n_2_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_2_o ( u_ddr_dqs_n_2_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_2_sel ( u_ddr_dqs_n_2_io PU ) ( u_ddr_dqs_n_2_io OE ) + USE SIGNAL ; + - core_ddr_dqs_n_3_i ( u_ddr_dqs_n_3_io Y ) + USE SIGNAL ; + - core_ddr_dqs_n_3_o ( u_ddr_dqs_n_3_io A ) + USE SIGNAL ; + - core_ddr_dqs_n_3_sel ( u_ddr_dqs_n_3_io PU ) ( u_ddr_dqs_n_3_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_0_i ( u_ddr_dqs_p_0_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_0_o ( u_ddr_dqs_p_0_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_0_sel ( u_ddr_dqs_p_0_io PU ) ( u_ddr_dqs_p_0_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_1_i ( u_ddr_dqs_p_1_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_1_o ( u_ddr_dqs_p_1_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_1_sel ( u_ddr_dqs_p_1_io PU ) ( u_ddr_dqs_p_1_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_2_i ( u_ddr_dqs_p_2_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_2_o ( u_ddr_dqs_p_2_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_2_sel ( u_ddr_dqs_p_2_io PU ) ( u_ddr_dqs_p_2_io OE ) + USE SIGNAL ; + - core_ddr_dqs_p_3_i ( u_ddr_dqs_p_3_io Y ) + USE SIGNAL ; + - core_ddr_dqs_p_3_o ( u_ddr_dqs_p_3_io A ) + USE SIGNAL ; + - core_ddr_dqs_p_3_sel ( u_ddr_dqs_p_3_io PU ) ( u_ddr_dqs_p_3_io OE ) + USE SIGNAL ; + - core_ddr_odt_o ( u_ddr_odt_o A ) + USE SIGNAL ; + - core_ddr_ras_n_o ( u_ddr_ras_n_o A ) + USE SIGNAL ; + - core_ddr_reset_n_o ( u_ddr_reset_n_o A ) + USE SIGNAL ; + - core_ddr_we_n_o ( u_ddr_we_n_o A ) + USE SIGNAL ; + - core_misc_o ( u_misc_o A ) + USE SIGNAL ; + - core_sel_0_i ( u_sel_0_i Y ) + USE SIGNAL ; + - core_sel_1_i ( u_sel_1_i Y ) + USE SIGNAL ; + - core_sel_2_i ( u_sel_2_i Y ) + USE SIGNAL ; + - p_bsg_tag_clk_i ( PIN p_bsg_tag_clk_i ) ( u_bsg_tag_clk_i PAD ) + USE SIGNAL ; + - p_bsg_tag_clk_o ( PIN p_bsg_tag_clk_o ) ( u_bsg_tag_clk_o PAD ) + USE SIGNAL ; + - p_bsg_tag_data_i ( PIN p_bsg_tag_data_i ) ( u_bsg_tag_data_i PAD ) + USE SIGNAL ; + - p_bsg_tag_data_o ( PIN p_bsg_tag_data_o ) ( u_bsg_tag_data_o PAD ) + USE SIGNAL ; + - p_bsg_tag_en_i ( PIN p_bsg_tag_en_i ) ( u_bsg_tag_en_i PAD ) + USE SIGNAL ; + - p_ci2_0_o ( PIN p_ci2_0_o ) ( u_ci2_0_o PAD ) + USE SIGNAL ; + - p_ci2_1_o ( PIN p_ci2_1_o ) ( u_ci2_1_o PAD ) + USE SIGNAL ; + - p_ci2_2_o ( PIN p_ci2_2_o ) ( u_ci2_2_o PAD ) + USE SIGNAL ; + - p_ci2_3_o ( PIN p_ci2_3_o ) ( u_ci2_3_o PAD ) + USE SIGNAL ; + - p_ci2_4_o ( PIN p_ci2_4_o ) ( u_ci2_4_o PAD ) + USE SIGNAL ; + - p_ci2_5_o ( PIN p_ci2_5_o ) ( u_ci2_5_o PAD ) + USE SIGNAL ; + - p_ci2_6_o ( PIN p_ci2_6_o ) ( u_ci2_6_o PAD ) + USE SIGNAL ; + - p_ci2_7_o ( PIN p_ci2_7_o ) ( u_ci2_7_o PAD ) + USE SIGNAL ; + - p_ci2_8_o ( PIN p_ci2_8_o ) ( u_ci2_8_o PAD ) + USE SIGNAL ; + - p_ci2_clk_o ( PIN p_ci2_clk_o ) ( u_ci2_clk_o PAD ) + USE SIGNAL ; + - p_ci2_tkn_i ( PIN p_ci2_tkn_i ) ( u_ci2_tkn_i PAD ) + USE SIGNAL ; + - p_ci2_v_o ( PIN p_ci2_v_o ) ( u_ci2_v_o PAD ) + USE SIGNAL ; + - p_ci_0_i ( PIN p_ci_0_i ) ( u_ci_0_i PAD ) + USE SIGNAL ; + - p_ci_1_i ( PIN p_ci_1_i ) ( u_ci_1_i PAD ) + USE SIGNAL ; + - p_ci_2_i ( PIN p_ci_2_i ) ( u_ci_2_i PAD ) + USE SIGNAL ; + - p_ci_3_i ( PIN p_ci_3_i ) ( u_ci_3_i PAD ) + USE SIGNAL ; + - p_ci_4_i ( PIN p_ci_4_i ) ( u_ci_4_i PAD ) + USE SIGNAL ; + - p_ci_5_i ( PIN p_ci_5_i ) ( u_ci_5_i PAD ) + USE SIGNAL ; + - p_ci_6_i ( PIN p_ci_6_i ) ( u_ci_6_i PAD ) + USE SIGNAL ; + - p_ci_7_i ( PIN p_ci_7_i ) ( u_ci_7_i PAD ) + USE SIGNAL ; + - p_ci_8_i ( PIN p_ci_8_i ) ( u_ci_8_i PAD ) + USE SIGNAL ; + - p_ci_clk_i ( PIN p_ci_clk_i ) ( u_ci_clk_i PAD ) + USE SIGNAL ; + - p_ci_tkn_o ( PIN p_ci_tkn_o ) ( u_ci_tkn_o PAD ) + USE SIGNAL ; + - p_ci_v_i ( PIN p_ci_v_i ) ( u_ci_v_i PAD ) + USE SIGNAL ; + - p_clk_A_i ( PIN p_clk_A_i ) ( u_clk_A_i PAD ) + USE SIGNAL ; + - p_clk_B_i ( PIN p_clk_B_i ) ( u_clk_B_i PAD ) + USE SIGNAL ; + - p_clk_C_i ( PIN p_clk_C_i ) ( u_clk_C_i PAD ) + USE SIGNAL ; + - p_clk_async_reset_i ( PIN p_clk_async_reset_i ) ( u_clk_async_reset_i PAD ) + USE SIGNAL ; + - p_clk_o ( PIN p_clk_o ) ( u_clk_o PAD ) + USE SIGNAL ; + - p_co2_0_o ( PIN p_co2_0_o ) ( u_co2_0_o PAD ) + USE SIGNAL ; + - p_co2_1_o ( PIN p_co2_1_o ) ( u_co2_1_o PAD ) + USE SIGNAL ; + - p_co2_2_o ( PIN p_co2_2_o ) ( u_co2_2_o PAD ) + USE SIGNAL ; + - p_co2_3_o ( PIN p_co2_3_o ) ( u_co2_3_o PAD ) + USE SIGNAL ; + - p_co2_4_o ( PIN p_co2_4_o ) ( u_co2_4_o PAD ) + USE SIGNAL ; + - p_co2_5_o ( PIN p_co2_5_o ) ( u_co2_5_o PAD ) + USE SIGNAL ; + - p_co2_6_o ( PIN p_co2_6_o ) ( u_co2_6_o PAD ) + USE SIGNAL ; + - p_co2_7_o ( PIN p_co2_7_o ) ( u_co2_7_o PAD ) + USE SIGNAL ; + - p_co2_8_o ( PIN p_co2_8_o ) ( u_co2_8_o PAD ) + USE SIGNAL ; + - p_co2_clk_o ( PIN p_co2_clk_o ) ( u_co2_clk_o PAD ) + USE SIGNAL ; + - p_co2_tkn_i ( PIN p_co2_tkn_i ) ( u_co2_tkn_i PAD ) + USE SIGNAL ; + - p_co2_v_o ( PIN p_co2_v_o ) ( u_co2_v_o PAD ) + USE SIGNAL ; + - p_co_0_i ( PIN p_co_0_i ) ( u_co_0_i PAD ) + USE SIGNAL ; + - p_co_1_i ( PIN p_co_1_i ) ( u_co_1_i PAD ) + USE SIGNAL ; + - p_co_2_i ( PIN p_co_2_i ) ( u_co_2_i PAD ) + USE SIGNAL ; + - p_co_3_i ( PIN p_co_3_i ) ( u_co_3_i PAD ) + USE SIGNAL ; + - p_co_4_i ( PIN p_co_4_i ) ( u_co_4_i PAD ) + USE SIGNAL ; + - p_co_5_i ( PIN p_co_5_i ) ( u_co_5_i PAD ) + USE SIGNAL ; + - p_co_6_i ( PIN p_co_6_i ) ( u_co_6_i PAD ) + USE SIGNAL ; + - p_co_7_i ( PIN p_co_7_i ) ( u_co_7_i PAD ) + USE SIGNAL ; + - p_co_8_i ( PIN p_co_8_i ) ( u_co_8_i PAD ) + USE SIGNAL ; + - p_co_clk_i ( PIN p_co_clk_i ) ( u_co_clk_i PAD ) + USE SIGNAL ; + - p_co_tkn_o ( PIN p_co_tkn_o ) ( u_co_tkn_o PAD ) + USE SIGNAL ; + - p_co_v_i ( PIN p_co_v_i ) ( u_co_v_i PAD ) + USE SIGNAL ; + - p_core_async_reset_i ( PIN p_core_async_reset_i ) ( u_core_async_reset_i PAD ) + USE SIGNAL ; + - p_ddr_addr_0_o ( PIN p_ddr_addr_0_o ) ( u_ddr_addr_0_o PAD ) + USE SIGNAL ; + - p_ddr_addr_10_o ( PIN p_ddr_addr_10_o ) ( u_ddr_addr_10_o PAD ) + USE SIGNAL ; + - p_ddr_addr_11_o ( PIN p_ddr_addr_11_o ) ( u_ddr_addr_11_o PAD ) + USE SIGNAL ; + - p_ddr_addr_12_o ( PIN p_ddr_addr_12_o ) ( u_ddr_addr_12_o PAD ) + USE SIGNAL ; + - p_ddr_addr_13_o ( PIN p_ddr_addr_13_o ) ( u_ddr_addr_13_o PAD ) + USE SIGNAL ; + - p_ddr_addr_14_o ( PIN p_ddr_addr_14_o ) ( u_ddr_addr_14_o PAD ) + USE SIGNAL ; + - p_ddr_addr_15_o ( PIN p_ddr_addr_15_o ) ( u_ddr_addr_15_o PAD ) + USE SIGNAL ; + - p_ddr_addr_1_o ( PIN p_ddr_addr_1_o ) ( u_ddr_addr_1_o PAD ) + USE SIGNAL ; + - p_ddr_addr_2_o ( PIN p_ddr_addr_2_o ) ( u_ddr_addr_2_o PAD ) + USE SIGNAL ; + - p_ddr_addr_3_o ( PIN p_ddr_addr_3_o ) ( u_ddr_addr_3_o PAD ) + USE SIGNAL ; + - p_ddr_addr_4_o ( PIN p_ddr_addr_4_o ) ( u_ddr_addr_4_o PAD ) + USE SIGNAL ; + - p_ddr_addr_5_o ( PIN p_ddr_addr_5_o ) ( u_ddr_addr_5_o PAD ) + USE SIGNAL ; + - p_ddr_addr_6_o ( PIN p_ddr_addr_6_o ) ( u_ddr_addr_6_o PAD ) + USE SIGNAL ; + - p_ddr_addr_7_o ( PIN p_ddr_addr_7_o ) ( u_ddr_addr_7_o PAD ) + USE SIGNAL ; + - p_ddr_addr_8_o ( PIN p_ddr_addr_8_o ) ( u_ddr_addr_8_o PAD ) + USE SIGNAL ; + - p_ddr_addr_9_o ( PIN p_ddr_addr_9_o ) ( u_ddr_addr_9_o PAD ) + USE SIGNAL ; + - p_ddr_ba_0_o ( PIN p_ddr_ba_0_o ) ( u_ddr_ba_0_o PAD ) + USE SIGNAL ; + - p_ddr_ba_1_o ( PIN p_ddr_ba_1_o ) ( u_ddr_ba_1_o PAD ) + USE SIGNAL ; + - p_ddr_ba_2_o ( PIN p_ddr_ba_2_o ) ( u_ddr_ba_2_o PAD ) + USE SIGNAL ; + - p_ddr_cas_n_o ( PIN p_ddr_cas_n_o ) ( u_ddr_cas_n_o PAD ) + USE SIGNAL ; + - p_ddr_ck_n_o ( PIN p_ddr_ck_n_o ) ( u_ddr_ck_n_o PAD ) + USE SIGNAL ; + - p_ddr_ck_p_o ( PIN p_ddr_ck_p_o ) ( u_ddr_ck_p_o PAD ) + USE SIGNAL ; + - p_ddr_cke_o ( PIN p_ddr_cke_o ) ( u_ddr_cke_o PAD ) + USE SIGNAL ; + - p_ddr_cs_n_o ( PIN p_ddr_cs_n_o ) ( u_ddr_cs_n_o PAD ) + USE SIGNAL ; + - p_ddr_dm_0_o ( PIN p_ddr_dm_0_o ) ( u_ddr_dm_0_o PAD ) + USE SIGNAL ; + - p_ddr_dm_1_o ( PIN p_ddr_dm_1_o ) ( u_ddr_dm_1_o PAD ) + USE SIGNAL ; + - p_ddr_dm_2_o ( PIN p_ddr_dm_2_o ) ( u_ddr_dm_2_o PAD ) + USE SIGNAL ; + - p_ddr_dm_3_o ( PIN p_ddr_dm_3_o ) ( u_ddr_dm_3_o PAD ) + USE SIGNAL ; + - p_ddr_dq_0_io ( PIN p_ddr_dq_0_io ) ( u_ddr_dq_0_io PAD ) + USE SIGNAL ; + - p_ddr_dq_10_io ( PIN p_ddr_dq_10_io ) ( u_ddr_dq_10_io PAD ) + USE SIGNAL ; + - p_ddr_dq_11_io ( PIN p_ddr_dq_11_io ) ( u_ddr_dq_11_io PAD ) + USE SIGNAL ; + - p_ddr_dq_12_io ( PIN p_ddr_dq_12_io ) ( u_ddr_dq_12_io PAD ) + USE SIGNAL ; + - p_ddr_dq_13_io ( PIN p_ddr_dq_13_io ) ( u_ddr_dq_13_io PAD ) + USE SIGNAL ; + - p_ddr_dq_14_io ( PIN p_ddr_dq_14_io ) ( u_ddr_dq_14_io PAD ) + USE SIGNAL ; + - p_ddr_dq_15_io ( PIN p_ddr_dq_15_io ) ( u_ddr_dq_15_io PAD ) + USE SIGNAL ; + - p_ddr_dq_16_io ( PIN p_ddr_dq_16_io ) ( u_ddr_dq_16_io PAD ) + USE SIGNAL ; + - p_ddr_dq_17_io ( PIN p_ddr_dq_17_io ) ( u_ddr_dq_17_io PAD ) + USE SIGNAL ; + - p_ddr_dq_18_io ( PIN p_ddr_dq_18_io ) ( u_ddr_dq_18_io PAD ) + USE SIGNAL ; + - p_ddr_dq_19_io ( PIN p_ddr_dq_19_io ) ( u_ddr_dq_19_io PAD ) + USE SIGNAL ; + - p_ddr_dq_1_io ( PIN p_ddr_dq_1_io ) ( u_ddr_dq_1_io PAD ) + USE SIGNAL ; + - p_ddr_dq_20_io ( PIN p_ddr_dq_20_io ) ( u_ddr_dq_20_io PAD ) + USE SIGNAL ; + - p_ddr_dq_21_io ( PIN p_ddr_dq_21_io ) ( u_ddr_dq_21_io PAD ) + USE SIGNAL ; + - p_ddr_dq_22_io ( PIN p_ddr_dq_22_io ) ( u_ddr_dq_22_io PAD ) + USE SIGNAL ; + - p_ddr_dq_23_io ( PIN p_ddr_dq_23_io ) ( u_ddr_dq_23_io PAD ) + USE SIGNAL ; + - p_ddr_dq_24_io ( PIN p_ddr_dq_24_io ) ( u_ddr_dq_24_io PAD ) + USE SIGNAL ; + - p_ddr_dq_25_io ( PIN p_ddr_dq_25_io ) ( u_ddr_dq_25_io PAD ) + USE SIGNAL ; + - p_ddr_dq_26_io ( PIN p_ddr_dq_26_io ) ( u_ddr_dq_26_io PAD ) + USE SIGNAL ; + - p_ddr_dq_27_io ( PIN p_ddr_dq_27_io ) ( u_ddr_dq_27_io PAD ) + USE SIGNAL ; + - p_ddr_dq_28_io ( PIN p_ddr_dq_28_io ) ( u_ddr_dq_28_io PAD ) + USE SIGNAL ; + - p_ddr_dq_29_io ( PIN p_ddr_dq_29_io ) ( u_ddr_dq_29_io PAD ) + USE SIGNAL ; + - p_ddr_dq_2_io ( PIN p_ddr_dq_2_io ) ( u_ddr_dq_2_io PAD ) + USE SIGNAL ; + - p_ddr_dq_30_io ( PIN p_ddr_dq_30_io ) ( u_ddr_dq_30_io PAD ) + USE SIGNAL ; + - p_ddr_dq_31_io ( PIN p_ddr_dq_31_io ) ( u_ddr_dq_31_io PAD ) + USE SIGNAL ; + - p_ddr_dq_3_io ( PIN p_ddr_dq_3_io ) ( u_ddr_dq_3_io PAD ) + USE SIGNAL ; + - p_ddr_dq_4_io ( PIN p_ddr_dq_4_io ) ( u_ddr_dq_4_io PAD ) + USE SIGNAL ; + - p_ddr_dq_5_io ( PIN p_ddr_dq_5_io ) ( u_ddr_dq_5_io PAD ) + USE SIGNAL ; + - p_ddr_dq_6_io ( PIN p_ddr_dq_6_io ) ( u_ddr_dq_6_io PAD ) + USE SIGNAL ; + - p_ddr_dq_7_io ( PIN p_ddr_dq_7_io ) ( u_ddr_dq_7_io PAD ) + USE SIGNAL ; + - p_ddr_dq_8_io ( PIN p_ddr_dq_8_io ) ( u_ddr_dq_8_io PAD ) + USE SIGNAL ; + - p_ddr_dq_9_io ( PIN p_ddr_dq_9_io ) ( u_ddr_dq_9_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_0_io ( PIN p_ddr_dqs_n_0_io ) ( u_ddr_dqs_n_0_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_1_io ( PIN p_ddr_dqs_n_1_io ) ( u_ddr_dqs_n_1_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_2_io ( PIN p_ddr_dqs_n_2_io ) ( u_ddr_dqs_n_2_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_n_3_io ( PIN p_ddr_dqs_n_3_io ) ( u_ddr_dqs_n_3_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_0_io ( PIN p_ddr_dqs_p_0_io ) ( u_ddr_dqs_p_0_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_1_io ( PIN p_ddr_dqs_p_1_io ) ( u_ddr_dqs_p_1_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_2_io ( PIN p_ddr_dqs_p_2_io ) ( u_ddr_dqs_p_2_io PAD ) + USE SIGNAL ; + - p_ddr_dqs_p_3_io ( PIN p_ddr_dqs_p_3_io ) ( u_ddr_dqs_p_3_io PAD ) + USE SIGNAL ; + - p_ddr_odt_o ( PIN p_ddr_odt_o ) ( u_ddr_odt_o PAD ) + USE SIGNAL ; + - p_ddr_ras_n_o ( PIN p_ddr_ras_n_o ) ( u_ddr_ras_n_o PAD ) + USE SIGNAL ; + - p_ddr_reset_n_o ( PIN p_ddr_reset_n_o ) ( u_ddr_reset_n_o PAD ) + USE SIGNAL ; + - p_ddr_we_n_o ( PIN p_ddr_we_n_o ) ( u_ddr_we_n_o PAD ) + USE SIGNAL ; + - p_misc_o ( PIN p_misc_o ) ( u_misc_o PAD ) + USE SIGNAL ; + - p_sel_0_i ( PIN p_sel_0_i ) ( u_sel_0_i PAD ) + USE SIGNAL ; + - p_sel_1_i ( PIN p_sel_1_i ) ( u_sel_1_i PAD ) + USE SIGNAL ; + - p_sel_2_i ( PIN p_sel_2_i ) ( u_sel_2_i PAD ) + USE SIGNAL ; +END NETS +END DESIGN diff --git a/src/pad/test/place_pads_uniform_fullyblocked.ok b/src/pad/test/place_pads_uniform_fullyblocked.ok new file mode 100755 index 00000000000..c373782ea21 --- /dev/null +++ b/src/pad/test/place_pads_uniform_fullyblocked.ok @@ -0,0 +1,9 @@ +[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells +[INFO ODB-0227] LEF file: Nangate45_io/dummy_pads.lef, created 30 library cells +[INFO ODB-0128] Design: soc_bsg_black_parrot +[INFO ODB-0130] Created 135 pins. +[INFO ODB-0131] Created 267 components and 2277 component-terminals. +[INFO ODB-0133] Created 350 nets and 390 connections. +[ERROR PAD-0047] Pad placement unable to legalize pads after 2 iterations. +PAD-0047 +No differences found. diff --git a/src/pad/test/place_pads_uniform_fullyblocked.tcl b/src/pad/test/place_pads_uniform_fullyblocked.tcl new file mode 100644 index 00000000000..a1a59df7f3b --- /dev/null +++ b/src/pad/test/place_pads_uniform_fullyblocked.tcl @@ -0,0 +1,33 @@ +# Test for placing pads using place_pads with uniform spacing +source "helpers.tcl" + +# Init chip +read_lef Nangate45/Nangate45.lef +read_lef Nangate45_io/dummy_pads.lef + +read_def Nangate45_blackparrot/floorplan.def + +# Test place_pad +make_io_sites -horizontal_site IOSITE -vertical_site IOSITE -corner_site IOSITE -offset 15 + +# Create blockage that blocks all of the row +create_obstruction -region {0 0 100 3000} -layer metal10 + +catch { + place_pads -mode placer -row IO_WEST u_vss_15 u_vdd_15 u_ddr_dq_8_io u_ddr_dq_9_io \ + u_ddr_dq_10_io u_ddr_dq_11_io u_ddr_dq_12_io u_v18_32 u_vzz_32 \ + u_ddr_dq_13_io u_ddr_dq_14_io u_ddr_dq_15_io u_ddr_dqs_p_0_io \ + u_v18_31 u_vzz_31 u_ddr_dqs_n_0_io u_ddr_dm_0_o u_vss_14 u_vdd_14 \ + u_ddr_dq_0_io u_ddr_dq_1_io u_v18_30 u_vzz_30 u_ddr_dq_2_io \ + u_ddr_dq_3_io u_ddr_dq_4_io u_ddr_dq_5_io u_v18_29 u_vzz_29 \ + u_ddr_dq_6_io u_ddr_dq_7_io u_bsg_tag_data_o u_vss_13 u_vdd_13 \ + u_bsg_tag_clk_o u_v18_28 u_vzz_28 u_co2_0_o u_co2_1_o u_co2_2_o \ + u_co2_3_o u_v18_27 u_vzz_27 u_co2_4_o u_co2_clk_o u_co2_tkn_i \ + u_co2_v_o u_v18_26 u_vzz_26 u_vss_12 u_vdd_12 u_co2_5_o u_co2_6_o \ + u_co2_7_o u_co2_8_o +} err +puts $err + +set def_file [make_result_file "place_pads_uniform_fullyblocked.def"] +write_def $def_file +diff_files $def_file "place_pads_uniform_fullyblocked.defok" From a2e45d7ddea7adb3ac5dab43d49a1eb675fcb2ee Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Sun, 7 Jun 2026 16:14:59 -0400 Subject: [PATCH 2/4] pad: fix name of test Signed-off-by: Peter Gadfort --- src/pad/test/BUILD | 2 +- src/pad/test/CMakeLists.txt | 2 +- ...lyblocked.defok => place_pads_placer_fullyblocked.defok} | 0 ...rm_fullyblocked.ok => place_pads_placer_fullyblocked.ok} | 0 ..._fullyblocked.tcl => place_pads_placer_fullyblocked.tcl} | 6 +++--- 5 files changed, 5 insertions(+), 5 deletions(-) rename src/pad/test/{place_pads_uniform_fullyblocked.defok => place_pads_placer_fullyblocked.defok} (100%) rename src/pad/test/{place_pads_uniform_fullyblocked.ok => place_pads_placer_fullyblocked.ok} (100%) rename src/pad/test/{place_pads_uniform_fullyblocked.tcl => place_pads_placer_fullyblocked.tcl} (85%) diff --git a/src/pad/test/BUILD b/src/pad/test/BUILD index afa0be6a2e7..a1258325346 100644 --- a/src/pad/test/BUILD +++ b/src/pad/test/BUILD @@ -39,8 +39,8 @@ COMPULSORY_TESTS = [ "place_pads_bumps_bump_overlap", "place_pads_bumps_strategy_placer_blockages", "place_pads_bumps_strategy", + "place_pads_placer_fullyblocked", "place_pads_too_many", - "place_pads_uniform_fullyblocked", "place_pads_uniform", "place_pads_uniform_slip", "rdl_route", diff --git a/src/pad/test/CMakeLists.txt b/src/pad/test/CMakeLists.txt index dba36ae1fc1..3aadbb1c855 100644 --- a/src/pad/test/CMakeLists.txt +++ b/src/pad/test/CMakeLists.txt @@ -32,8 +32,8 @@ or_integration_tests( place_pads_bumps_strategy place_pad_wrong_master place_pads_bumps + place_pads_placer_fullyblocked place_pads_too_many - place_pads_uniform_fullyblocked place_pads_uniform place_pads_uniform_slip rdl_route diff --git a/src/pad/test/place_pads_uniform_fullyblocked.defok b/src/pad/test/place_pads_placer_fullyblocked.defok similarity index 100% rename from src/pad/test/place_pads_uniform_fullyblocked.defok rename to src/pad/test/place_pads_placer_fullyblocked.defok diff --git a/src/pad/test/place_pads_uniform_fullyblocked.ok b/src/pad/test/place_pads_placer_fullyblocked.ok similarity index 100% rename from src/pad/test/place_pads_uniform_fullyblocked.ok rename to src/pad/test/place_pads_placer_fullyblocked.ok diff --git a/src/pad/test/place_pads_uniform_fullyblocked.tcl b/src/pad/test/place_pads_placer_fullyblocked.tcl similarity index 85% rename from src/pad/test/place_pads_uniform_fullyblocked.tcl rename to src/pad/test/place_pads_placer_fullyblocked.tcl index a1a59df7f3b..8e6fe328f21 100644 --- a/src/pad/test/place_pads_uniform_fullyblocked.tcl +++ b/src/pad/test/place_pads_placer_fullyblocked.tcl @@ -1,4 +1,4 @@ -# Test for placing pads using place_pads with uniform spacing +# Test for placing pads using place_pads placer mode source "helpers.tcl" # Init chip @@ -28,6 +28,6 @@ catch { } err puts $err -set def_file [make_result_file "place_pads_uniform_fullyblocked.def"] +set def_file [make_result_file "place_pads_placer_fullyblocked.def"] write_def $def_file -diff_files $def_file "place_pads_uniform_fullyblocked.defok" +diff_files $def_file "place_pads_placer_fullyblocked.defok" From 70df408cdad5f69fb303fcc5abdfefa6843823b5 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Sun, 7 Jun 2026 16:15:40 -0400 Subject: [PATCH 3/4] pad: avoid additional allocations in run Signed-off-by: Peter Gadfort --- src/pad/src/PadPlacer.cpp | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/src/pad/src/PadPlacer.cpp b/src/pad/src/PadPlacer.cpp index 79303004f5d..0c7b67bb862 100644 --- a/src/pad/src/PadPlacer.cpp +++ b/src/pad/src/PadPlacer.cpp @@ -1570,6 +1570,12 @@ odb::PtrMap PlacerPadPlacer::padSpreading( positions[inst] = std::move(anchors); } + std::vector check_positions; + check_positions.reserve(positions.size()); + for (const auto& [inst, anchor] : positions) { + check_positions.push_back(anchor->center); + } + for (int k = 0; k < kMaxIterations; k++) { // Update coeff schedule const float kRepel1 = kRepelStart @@ -1582,20 +1588,22 @@ odb::PtrMap PlacerPadPlacer::padSpreading( : kSpringStart; const float kSpring1 = k > kSpringIterEnd ? 0 : kString2; - odb::PtrMap curr_positions; - for (const auto& [inst, anchor] : positions) { - curr_positions[inst] = anchor->center; - } if (padSpreading( positions, initial_positions, k, kSpring1, kRepel1, kDamper)) { break; } - odb::PtrMap new_positions; + bool changed = false; + size_t idx = 0; for (const auto& [inst, anchor] : positions) { - new_positions[inst] = anchor->center; + if (anchor->center != check_positions[idx]) { + changed = true; + } + // update check positions + check_positions[idx] = anchor->center; + idx++; } - if (new_positions == curr_positions) { + if (!changed) { // Place instances for better debugging placeInstances(positions); getLogger()->error( From 43e1e44669b2c2f93a58a1159c456f8e71aaa5b6 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Sun, 7 Jun 2026 16:34:10 -0400 Subject: [PATCH 4/4] pad: add missing header Signed-off-by: Peter Gadfort --- src/pad/src/PadPlacer.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/pad/src/PadPlacer.cpp b/src/pad/src/PadPlacer.cpp index 0c7b67bb862..e4f9b6dea21 100644 --- a/src/pad/src/PadPlacer.cpp +++ b/src/pad/src/PadPlacer.cpp @@ -5,6 +5,7 @@ #include #include +#include #include #include #include