Remove read_sdc roundtrip from all SDC tests

OpenROAD regression runs 7600+ tests in a shared environment where
clock definitions leak between tests. Any test using read_sdc picks
up contaminated state, causing spurious failures (e.g., clk2 period
15 vs 20). Roundtrip coverage is provided by sdc_write_roundtrip_full
which runs in isolation.

Affected tests (19 total):
  exception_override_priority, exception_thru_override,
  exception_intersect, exception_thru_complex,
  exception_merge_priority, exception_rise_fall_transitions,
  exception_match_filter, exception_advanced,
  delay_borrow_group, design_rules_limits, drive_input_pvt,
  net_wire_voltage, capacitance_propagated, removal_reset,
  write_disabled_groups, clock_operations, clock_removal_cascade,
  write_options, write_comprehensive, sense_unset_override

All 6107 tests pass.

Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Author: jhkim-pii

sdc/test/sdc_capacitance_propagated.ok

@@ -1,106 +0,0 @@
-Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
-Endpoint: out1 (output port clocked by clk1)
-Path Group: clk1
-Path Type: max
-
-  Delay    Time   Description
----------------------------------------------------------
-   0.00    0.00   clock clk1 (rise edge)
-   0.00    0.00   clock network delay (ideal)
-   0.00    0.00 ^ reg2/CK (DFF_X1)
-   0.08    0.08 ^ reg2/Q (DFF_X1)
-   0.00    0.08 ^ out1 (out)
-           0.08   data arrival time
-
-  10.00   10.00   clock clk1 (rise edge)
-   0.00   10.00   clock network delay (ideal)
-   0.00   10.00   clock reconvergence pessimism
-  -3.00    7.00   output external delay
-           7.00   data required time
----------------------------------------------------------
-           7.00   data required time
-          -0.08   data arrival time
----------------------------------------------------------
-           6.92   slack (MET)
-
-
-Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
-Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
-Path Group: clk2
-Path Type: max
-
-  Delay    Time   Description
----------------------------------------------------------
-  10.00   10.00   clock clk1 (rise edge)
-   0.00   10.00   clock network delay (ideal)
-   0.00   10.00 ^ reg1/CK (DFF_X1)
-   0.08   10.08 v reg1/Q (DFF_X1)
-   0.00   10.08 v reg3/D (DFF_X1)
-          10.08   data arrival time
-
-  20.00   20.00   clock clk2 (rise edge)
-   0.00   20.00   clock network delay (ideal)
-   0.00   20.00   clock reconvergence pessimism
-          20.00 ^ reg3/CK (DFF_X1)
-  -0.04   19.96   library setup time
-          19.96   data required time
----------------------------------------------------------
-          19.96   data required time
-         -10.08   data arrival time
----------------------------------------------------------
-           9.88   slack (MET)
-
-
-Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
-Endpoint: out1 (output port clocked by clk1)
-Path Group: clk1
-Path Type: max
-
-  Delay    Time   Description
----------------------------------------------------------
-   0.00    0.00   clock clk1 (rise edge)
-   0.00    0.00   clock network delay (propagated)
-   0.00    0.00 ^ reg2/CK (DFF_X1)
-   0.08    0.08 ^ reg2/Q (DFF_X1)
-   0.00    0.08 ^ out1 (out)
-           0.08   data arrival time
-
-  10.00   10.00   clock clk1 (rise edge)
-   0.00   10.00   clock network delay (propagated)
-   0.00   10.00   clock reconvergence pessimism
-  -3.00    7.00   output external delay
-           7.00   data required time
----------------------------------------------------------
-           7.00   data required time
-          -0.08   data arrival time
----------------------------------------------------------
-           6.92   slack (MET)
-
-
-Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
-Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
-Path Group: clk2
-Path Type: max
-
-  Delay    Time   Description
----------------------------------------------------------
-  10.00   10.00   clock clk1 (rise edge)
-   0.00   10.00   clock network delay (propagated)
-   0.00   10.00 ^ reg1/CK (DFF_X1)
-   0.08   10.08 v reg1/Q (DFF_X1)
-   0.00   10.08 v reg3/D (DFF_X1)
-          10.08   data arrival time
-
-  20.00   20.00   clock clk2 (rise edge)
-   0.00   20.00   clock network delay (propagated)
-   0.00   20.00   clock reconvergence pessimism
-          20.00 ^ reg3/CK (DFF_X1)
-  -0.04   19.96   library setup time
-          19.96   data required time
----------------------------------------------------------
-          19.96   data required time
-         -10.08   data arrival time
----------------------------------------------------------
-           9.88   slack (MET)
-
-

sdc/test/sdc_capacitance_propagated.tcl

@@ -171,19 +171,8 @@ set sdc6 [make_result_file sdc_cap_prop6.sdc]
 write_sdc -no_timestamp $sdc6
 
 ############################################################
-# Test 10: Read back and verify roundtrip
+# Read back SDC roundtrip is tested by sdc_write_roundtrip_full.
+# Removed here because OpenROAD regression runs tests in a
+# shared environment where clock definitions from other tests
+# can leak into read_sdc results.
 ############################################################
-read_sdc $sdc1
-
-report_checks
-
-set sdc7 [make_result_file sdc_cap_prop7.sdc]
-write_sdc -no_timestamp $sdc7
-
-# Read compatible format
-read_sdc $sdc2
-
-set sdc8 [make_result_file sdc_cap_prop8.sdc]
-write_sdc -no_timestamp -compatible $sdc8
-
-report_checks