Merge pull request #332 from The-OpenROAD-Project-staging/secure-test-suite-cleanup

Clean up test suite: remove dead code, fix race conditions, centralize helpers

Author: maliberty

.gitignore

@@ -30,3 +30,7 @@ doc/messages.txt
 
 # clangd turds
 .cache/
+
+# test artifacts
+*/test/*.log
+Testing/

dcalc/test/cpp/TestDcalc.cc

@@ -1467,15 +1467,14 @@ TEST_F(ArcDcalcResultTest, CopyResult) {
   EXPECT_FLOAT_EQ(delayAsFloat(copy.loadSlew(1)), 6e-12f);
 }
 
-// Test ArcDcalcArg assignment
-TEST_F(ArcDcalcArgTest, Assignment) {
+// Test ArcDcalcArg copy construction with alternate values
+TEST_F(ArcDcalcArgTest, CopyConstructionAltValues) {
   ArcDcalcArg arg;
   arg.setLoadCap(3.5e-12f);
   arg.setInputDelay(1.5e-9f);
   arg.setInSlew(200e-12f);
 
-  ArcDcalcArg other;
-  other = arg;
+  ArcDcalcArg other(arg);
   EXPECT_FLOAT_EQ(other.loadCap(), 3.5e-12f);
   EXPECT_FLOAT_EQ(other.inputDelay(), 1.5e-9f);
   EXPECT_FLOAT_EQ(other.inSlewFlt(), 200e-12f);
@@ -2829,14 +2828,13 @@ TEST_F(ArcDcalcArgTest, InputDelayConstructorZero) {
   EXPECT_FLOAT_EQ(arg.inputDelay(), 0.0f);
 }
 
-TEST_F(ArcDcalcArgTest, CopyAssignment) {
+TEST_F(ArcDcalcArgTest, CopyConstructionAltValues2) {
   ArcDcalcArg arg;
   arg.setLoadCap(3.0e-12f);
   arg.setInputDelay(2.0e-9f);
   arg.setInSlew(75e-12f);
 
-  ArcDcalcArg copy;
-  copy = arg;
+  ArcDcalcArg copy(arg);
   EXPECT_FLOAT_EQ(copy.loadCap(), 3.0e-12f);
   EXPECT_FLOAT_EQ(copy.inputDelay(), 2.0e-9f);
   EXPECT_FLOAT_EQ(copy.inSlewFlt(), 75e-12f);

etc/Build.sh

@@ -16,8 +16,8 @@ elif [[ "$OSTYPE" == "darwin"* ]]; then
   numThreads=$(sysctl -n hw.ncpu)
 else
   cat << EOF
-WARNING: Unsupported OSTYPE: cannot determine number of host CPUs"
-  Defaulting to 2 threads. Use -threads=N to use N threads"
+WARNING: Unsupported OSTYPE: cannot determine number of host CPUs
+  Defaulting to 2 threads. Use -threads=N to use N threads
 EOF
   numThreads=2
 fi

graph/test/CMakeLists.txt

@@ -5,7 +5,6 @@ sta_module_tests("graph"
     delay_corners
     delete_modify
     incremental
-    make_verify
     modify
     operations
     timing_edges

graph/test/graph_bidirect.ok

@@ -68,7 +68,6 @@ No paths found.
 No paths found.
 No paths found.
 --- Test 3: report with fields ---
-Warning 168: graph_bidirect.tcl line 1, unknown field nets.
 Startpoint: d1 (input port clocked by clk)
 Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
 Path Group: clk
@@ -80,12 +79,16 @@ Fanout     Cap    Slew   Delay    Time   Description
                           0.00    0.00   clock network delay (ideal)
                           0.00    0.00 v input external delay
      1    0.88    0.10    0.00    0.00 v d1 (in)
+                                         d1 (net)
                   0.10    0.00    0.00 v buf1/A (BUF_X1)
      2    1.67    0.01    0.06    0.06 v buf1/Z (BUF_X1)
+                                         n1 (net)
                   0.01    0.00    0.06 v or1/A1 (OR2_X1)
      2    1.96    0.01    0.05    0.10 v or1/ZN (OR2_X1)
+                                         n6 (net)
                   0.01    0.00    0.10 v and2/A2 (AND2_X1)
      1    1.06    0.01    0.03    0.13 v and2/ZN (AND2_X1)
+                                         n9 (net)
                   0.01    0.00    0.13 v reg2/D (DFF_X1)
                                   0.13   data arrival time
 

graph/test/graph_bidirect.tcl

@@ -41,7 +41,7 @@ report_checks -from [get_ports d3] -to [get_ports q4]
 # Test 3: Fields that exercise graph delay/slew queries
 #---------------------------------------------------------------
 puts "--- Test 3: report with fields ---"
-report_checks -fields {slew cap input_pins nets fanout}
+report_checks -fields {slew cap input_pins net fanout}
 
 report_checks -format full_clock
 

graph/test/graph_delete_modify.ok

@@ -58,7 +58,6 @@ Path Type: min
            1.03   slack (MET)
 
 
-Warning 168: graph_delete_modify.tcl line 1, unknown field nets.
 Startpoint: d2 (input port clocked by clk)
 Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
 Path Group: clk
@@ -70,12 +69,16 @@ Fanout     Cap    Slew   Delay    Time   Description
                           0.00    0.00   clock network delay (ideal)
                           1.00    1.00 v input external delay
      1    0.88    0.10    0.00    1.00 v d2 (in)
+                                         d2 (net)
                   0.10    0.00    1.00 v buf2/A (BUF_X1)
      2    1.69    0.01    0.06    1.06 v buf2/Z (BUF_X1)
+                                         n2 (net)
                   0.01    0.00    1.06 v or1/A1 (OR2_X1)
      2    2.56    0.01    0.05    1.11 v or1/ZN (OR2_X1)
+                                         n6 (net)
                   0.01    0.00    1.11 v nand1/A2 (NAND2_X1)
      1    1.14    0.01    0.02    1.12 ^ nand1/ZN (NAND2_X1)
+                                         n7 (net)
                   0.01    0.00    1.12 ^ reg2/D (DFF_X1)
                                   1.12   data arrival time
 

graph/test/graph_delete_modify.tcl

@@ -26,7 +26,7 @@ report_checks
 
 report_checks -path_delay min
 
-report_checks -fields {slew cap input_pins nets fanout}
+report_checks -fields {slew cap input_pins net fanout}
 
 #---------------------------------------------------------------
 # Test 2: Add multiple instances and nets, then delete