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dsengupta0628dsengupta0628
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fix to exclude bias pins from timing graph
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
1 parent 5e2d5e8 commit d47cbeb

11 files changed

Lines changed: 115 additions & 6 deletions

‎include/sta/PortDirection.hh‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ public:
4141
static PortDirection *internal() { return internal_; }
4242
static PortDirection *ground() { return ground_; }
4343
static PortDirection *power() { return power_; }
44+
static PortDirection *bias() { return bias_; }
4445
static PortDirection *unknown() { return unknown_; }
4546
static PortDirection *find(const char *dir_name);
4647
std::string_view name() const { return name_; }
@@ -57,7 +58,8 @@ public:
5758
bool isAnyTristate() const;
5859
bool isGround() const { return this == ground_; }
5960
bool isPower() const { return this == power_; }
60-
// Ground or power.
61+
bool isBias() const { return this == bias_; }
62+
// Ground, power, or bias.
6163
bool isPowerGround() const;
6264
bool isInternal() const { return this == internal_; }
6365
bool isUnknown() const { return this == unknown_; }
@@ -76,6 +78,7 @@ private:
7678
static PortDirection *internal_;
7779
static PortDirection *ground_;
7880
static PortDirection *power_;
81+
static PortDirection *bias_;
7982
static PortDirection *unknown_;
8083
};
8184

‎liberty/LibertyReader.cc‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1217,6 +1217,12 @@ LibertyReader::makePgPinPort(LibertyCell *cell,
12171217
case PwrGndType::internal_power:
12181218
dir = PortDirection::power();
12191219
break;
1220+
case PwrGndType::nwell:
1221+
case PwrGndType::pwell:
1222+
case PwrGndType::deepnwell:
1223+
case PwrGndType::deeppwell:
1224+
dir = PortDirection::bias();
1225+
break;
12201226
case PwrGndType::none:
12211227
error(1291, pg_pin_group, "unknown pg_type.");
12221228
break;

‎liberty/LibertyWriter.cc‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -569,7 +569,8 @@ LibertyWriter::asString(const PortDirection *dir)
569569
return "internal";
570570
else if (dir == PortDirection::bidirect())
571571
return "inout";
572-
else if (dir == PortDirection::ground() || dir == PortDirection::power())
572+
else if (dir == PortDirection::ground() || dir == PortDirection::power()
573+
|| dir == PortDirection::bias())
573574
return "input";
574575
return "unknown";
575576
}

‎network/PortDirection.cc‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ PortDirection *PortDirection::bidirect_;
3535
PortDirection *PortDirection::internal_;
3636
PortDirection *PortDirection::ground_;
3737
PortDirection *PortDirection::power_;
38+
PortDirection *PortDirection::bias_;
3839
PortDirection *PortDirection::unknown_;
3940

4041
void
@@ -47,7 +48,8 @@ PortDirection::init()
4748
internal_ = new PortDirection("internal", 4);
4849
ground_ = new PortDirection("ground", 5);
4950
power_ = new PortDirection("power", 6);
50-
unknown_ = new PortDirection("unknown", 7);
51+
bias_ = new PortDirection("bias", 7);
52+
unknown_ = new PortDirection("unknown", 8);
5153
}
5254

5355
void
@@ -67,6 +69,8 @@ PortDirection::destroy()
6769
ground_ = nullptr;
6870
delete power_;
6971
power_ = nullptr;
72+
delete bias_;
73+
bias_ = nullptr;
7074
delete unknown_;
7175
unknown_ = nullptr;
7276
}
@@ -95,6 +99,8 @@ PortDirection::find(const char *dir_name)
9599
return ground_;
96100
else if (stringEqual(dir_name, "power"))
97101
return power_;
102+
else if (stringEqual(dir_name, "bias"))
103+
return bias_;
98104
else
99105
return nullptr;
100106
}
@@ -124,8 +130,7 @@ PortDirection::isAnyTristate() const
124130
bool
125131
PortDirection::isPowerGround() const
126132
{
127-
return this == ground_
128-
|| this == power_;
133+
return this == ground_ || this == power_ || this == bias_;
129134
}
130135

131136
} // namespace

‎network/test/cpp/TestNetwork.cc‎

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,11 +161,20 @@ TEST_F(PortDirectionTest, PowerSingleton) {
161161
EXPECT_TRUE(dir->isPower());
162162
}
163163

164+
TEST_F(PortDirectionTest, BiasSingleton)
165+
{
166+
PortDirection *dir = PortDirection::bias();
167+
EXPECT_NE(dir, nullptr);
168+
EXPECT_EQ(dir->name(), "bias");
169+
EXPECT_EQ(dir->index(), 7);
170+
EXPECT_TRUE(dir->isBias());
171+
}
172+
164173
TEST_F(PortDirectionTest, UnknownSingleton) {
165174
PortDirection *dir = PortDirection::unknown();
166175
EXPECT_NE(dir, nullptr);
167176
EXPECT_EQ(dir->name(), "unknown");
168-
EXPECT_EQ(dir->index(), 7);
177+
EXPECT_EQ(dir->index(), 8);
169178
EXPECT_TRUE(dir->isUnknown());
170179
}
171180

@@ -177,6 +186,7 @@ TEST_F(PortDirectionTest, FindByName) {
177186
EXPECT_EQ(PortDirection::find("internal"), PortDirection::internal());
178187
EXPECT_EQ(PortDirection::find("ground"), PortDirection::ground());
179188
EXPECT_EQ(PortDirection::find("power"), PortDirection::power());
189+
EXPECT_EQ(PortDirection::find("bias"), PortDirection::bias());
180190
EXPECT_EQ(PortDirection::find("nonexistent"), nullptr);
181191
}
182192

@@ -188,6 +198,7 @@ TEST_F(PortDirectionTest, IsAnyInput) {
188198
EXPECT_FALSE(PortDirection::internal()->isAnyInput());
189199
EXPECT_FALSE(PortDirection::ground()->isAnyInput());
190200
EXPECT_FALSE(PortDirection::power()->isAnyInput());
201+
EXPECT_FALSE(PortDirection::bias()->isAnyInput());
191202
EXPECT_FALSE(PortDirection::unknown()->isAnyInput());
192203
}
193204

@@ -199,6 +210,7 @@ TEST_F(PortDirectionTest, IsAnyOutput) {
199210
EXPECT_FALSE(PortDirection::internal()->isAnyOutput());
200211
EXPECT_FALSE(PortDirection::ground()->isAnyOutput());
201212
EXPECT_FALSE(PortDirection::power()->isAnyOutput());
213+
EXPECT_FALSE(PortDirection::bias()->isAnyOutput());
202214
EXPECT_FALSE(PortDirection::unknown()->isAnyOutput());
203215
}
204216

@@ -210,12 +222,14 @@ TEST_F(PortDirectionTest, IsAnyTristate) {
210222
EXPECT_FALSE(PortDirection::internal()->isAnyTristate());
211223
EXPECT_FALSE(PortDirection::ground()->isAnyTristate());
212224
EXPECT_FALSE(PortDirection::power()->isAnyTristate());
225+
EXPECT_FALSE(PortDirection::bias()->isAnyTristate());
213226
EXPECT_FALSE(PortDirection::unknown()->isAnyTristate());
214227
}
215228

216229
TEST_F(PortDirectionTest, IsPowerGround) {
217230
EXPECT_TRUE(PortDirection::power()->isPowerGround());
218231
EXPECT_TRUE(PortDirection::ground()->isPowerGround());
232+
EXPECT_TRUE(PortDirection::bias()->isPowerGround());
219233
EXPECT_FALSE(PortDirection::input()->isPowerGround());
220234
EXPECT_FALSE(PortDirection::output()->isPowerGround());
221235
EXPECT_FALSE(PortDirection::tristate()->isPowerGround());
@@ -851,6 +865,7 @@ TEST(PortDirectionExtraTest, AllDirections) {
851865
EXPECT_NE(PortDirection::internal(), nullptr);
852866
EXPECT_NE(PortDirection::ground(), nullptr);
853867
EXPECT_NE(PortDirection::power(), nullptr);
868+
EXPECT_NE(PortDirection::bias(), nullptr);
854869
EXPECT_NE(PortDirection::unknown(), nullptr);
855870
}
856871

@@ -873,6 +888,7 @@ TEST(PortDirectionExtraTest, DirectionProperties) {
873888

874889
EXPECT_TRUE(PortDirection::ground()->isPowerGround());
875890
EXPECT_TRUE(PortDirection::power()->isPowerGround());
891+
EXPECT_TRUE(PortDirection::bias()->isPowerGround());
876892
}
877893

878894
TEST(PortDirectionExtraTest, DirectionNames) {
@@ -886,6 +902,7 @@ TEST(PortDirectionExtraTest, DirectionNames) {
886902
EXPECT_EQ(PortDirection::internal()->name(), "internal");
887903
EXPECT_EQ(PortDirection::ground()->name(), "ground");
888904
EXPECT_EQ(PortDirection::power()->name(), "power");
905+
EXPECT_EQ(PortDirection::bias()->name(), "bias");
889906
EXPECT_EQ(PortDirection::unknown()->name(), "unknown");
890907
}
891908

@@ -900,6 +917,7 @@ TEST(PortDirectionExtraTest, FindAllByName) {
900917
EXPECT_EQ(PortDirection::find("internal"), PortDirection::internal());
901918
EXPECT_EQ(PortDirection::find("ground"), PortDirection::ground());
902919
EXPECT_EQ(PortDirection::find("power"), PortDirection::power());
920+
EXPECT_EQ(PortDirection::find("bias"), PortDirection::bias());
903921
// "unknown" is not findable by name, returns nullptr
904922
EXPECT_EQ(PortDirection::find("nonexistent"), nullptr);
905923
}

‎verilog/VerilogWriter.cc‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -253,6 +253,8 @@ VerilogWriter::verilogPortDir(PortDirection *dir)
253253
return "inout";
254254
else if (dir == PortDirection::ground())
255255
return "inout";
256+
else if (dir == PortDirection::bias())
257+
return "inout";
256258
else if (dir == PortDirection::internal()
257259
|| dir == PortDirection::unknown())
258260
return "inout";

‎verilog/test/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
sta_module_tests("verilog"
22
TESTS
3+
bias_pins
34
bus
45
)
56

‎verilog/test/verilog_bias_pins.ok‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
--- write_verilog bias pins ---
2+
No differences found.

‎verilog/test/verilog_bias_pins.tcl‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
# Test write_verilog should omit bias pins the same way it omits power/ground.
2+
3+
source ../../test/helpers.tcl
4+
5+
puts "--- write_verilog bias pins ---"
6+
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
7+
read_verilog verilog_bias_pins.v
8+
link_design top
9+
10+
set outfile [make_result_file verilog_bias_pins_out.v]
11+
write_verilog $outfile
12+
13+
set outfile_pwr [make_result_file verilog_bias_pins_pwr.v]
14+
write_verilog -include_pwr_gnd $outfile_pwr
15+
16+
set combined_out [make_result_file verilog_bias_pins_combined.v]
17+
set out_stream [open $combined_out w]
18+
foreach file [list $outfile $outfile_pwr] {
19+
set in_stream [open $file r]
20+
puts -nonewline $out_stream [read $in_stream]
21+
close $in_stream
22+
}
23+
close $out_stream
24+
25+
diff_files verilog_bias_pins_out.vok $combined_out

‎verilog/test/verilog_bias_pins.v‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
module top (
2+
output y,
3+
input a
4+
);
5+
6+
supply1 VPWR;
7+
supply0 VGND;
8+
supply1 VPB;
9+
supply0 VNB;
10+
11+
sky130_fd_sc_hd__buf_1 u1 (
12+
.X(y),
13+
.A(a),
14+
.VPWR(VPWR),
15+
.VGND(VGND),
16+
.VPB(VPB),
17+
.VNB(VNB)
18+
);
19+
20+
endmodule

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