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Migrate PyRTL to uv Run Python tests #162: Pull request #476 synchronize by fdxmw
2m 12s fdxmw:development
fdxmw:development
2m 12s
Allow passing custom module name to output_to_verilog Run Python tests #161: Pull request #474 synchronize by devmam999
1m 19s feature/module_name_param
feature/module_name_param
1m 19s
Allow passing custom module name to output_to_verilog Run Python tests #159: Pull request #474 synchronize by devmam999
1m 13s feature/module_name_param
feature/module_name_param
1m 13s
Migrate PyRTL to uv Run Python tests #158: Pull request #476 opened by fdxmw
1m 27s fdxmw:development
fdxmw:development
1m 27s
Use op_param's readability aliases in Gate.__str__. Run Python tests #157: Commit 001fba1 pushed by fdxmw
1m 19s development
development
1m 19s
Pyrtl floating point library Run Python tests #156: Pull request #475 synchronize by gaborszita
1m 25s gaborszita:pyrtlfloat
gaborszita:pyrtlfloat
1m 25s
Pyrtl floating point library Run Python tests #155: Pull request #475 opened by gaborszita
1m 13s gaborszita:pyrtlfloat
gaborszita:pyrtlfloat
1m 13s
Allow passing custom module name to output_to_verilog Run Python tests #154: Pull request #474 synchronize by devmam999
1m 13s feature/module_name_param
feature/module_name_param
1m 13s
Allow passing custom module name to output_to_verilog Run Python tests #150: Pull request #474 synchronize by devmam999
1m 13s feature/module_name_param
feature/module_name_param
1m 13s
Allow passing custom module name to output_to_verilog Run Python tests #149: Pull request #474 opened by devmam999
1m 19s feature/module_name_param
feature/module_name_param
1m 19s
Add Posit Support to PyRTL Run Python tests #148: Pull request #473 synchronize by arvindajaybharadwaj
1m 19s pes-innovation-lab:posits
pes-innovation-lab:posits
1m 19s
Fix code style issues identified by newer versions of ruff. Also: Run Python tests #147: Commit 8c706f6 pushed by fdxmw
1m 9s development
development
1m 9s
Add Posit Support to PyRTL Run Python tests #146: Pull request #473 opened by arvindajaybharadwaj
1m 13s pes-innovation-lab:posits
pes-innovation-lab:posits
1m 13s
Throw an exception if the user tries to render a trace without stepping the simulation Run Python tests #145: Pull request #472 opened by gaborszita
1m 23s gaborszita:sim-trace-error-no-step
gaborszita:sim-trace-error-no-step
1m 23s
Add readability aliases for Gate.op_param. These aliases assign nam… Run Python tests #144: Commit 137ff35 pushed by fdxmw
1m 25s development
development
1m 25s
Add documentation and examples for Const.val, `Register.reset_value… Run Python tests #143: Commit 0a57cd4 pushed by fdxmw
1m 14s development
development
1m 14s
Fix a typo in CHANGELOG.md's release notes for 0.12. Run Python tests #142: Commit ef456b6 pushed by fdxmw
1m 10s development
development
1m 10s
Run Python tests Run Python tests #141: by fdxmw
1m 12s 0.12
0.12
1m 12s
Update CHANGELOG.md for 0.12 release Run Python tests #140: Commit 5ad9ed6 pushed by fdxmw
1m 18s development
development
1m 18s
Update output_to_verilog to inline temporary wires, using `GateGrap… Run Python tests #139: Commit 98d2b5c pushed by fdxmw
1m 14s development
development
1m 14s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #138: Pull request #471 synchronize by fdxmw
1m 17s fdxmw:verilog
fdxmw:verilog
1m 17s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #137: Pull request #471 synchronize by fdxmw
1m 13s fdxmw:verilog
fdxmw:verilog
1m 13s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #136: Pull request #471 synchronize by fdxmw
1m 13s fdxmw:verilog
fdxmw:verilog
1m 13s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #135: Pull request #471 synchronize by fdxmw
1m 12s fdxmw:verilog
fdxmw:verilog
1m 12s
Update output_to_verilog to inline temporary wires, using GateGraph: Run Python tests #134: Pull request #471 synchronize by fdxmw
1m 11s fdxmw:verilog
fdxmw:verilog
1m 11s