I add ",verilog" at the end of the setting. But below block not rendered to the real verilog code, it shows as the below image. ```embed-verilog PATH: "https://raw.githubusercontent.com/veritas-verilog/full_adder/master/full_adder.v" LINES: "1-18" ```  
I add ",verilog" at the end of the setting.
But below block not rendered to the real verilog code, it shows as the below image.