diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index de81c0fb81c85..837697f6f0bc7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -319,7 +319,6 @@ config ARCH_CHIP_NRF52 #select ARM_HAVE_MPU_UNIFIED select ARCH_HAVE_SPI_BITORDER select ARCH_HAVE_FPU - select ARCH_HAVE_PWM_MULTICHAN select ARCH_HAVE_SERIAL_TERMIOS select ARCH_DMA_NO_FLASH_TRANSFER ---help--- @@ -328,7 +327,6 @@ config ARCH_CHIP_NRF52 config ARCH_CHIP_NRF53 bool "Nordic nRF53" select ARCH_CORTEXM33 - select ARCH_HAVE_PWM_MULTICHAN select ARCH_DMA_NO_FLASH_TRANSFER depends on EXPERIMENTAL ---help--- @@ -337,7 +335,6 @@ config ARCH_CHIP_NRF53 config ARCH_CHIP_NRF91 bool "Nordic nRF91" select ARCH_CORTEXM33 - select ARCH_HAVE_PWM_MULTICHAN select ARCH_HAVE_TRUSTZONE select ARCH_HAVE_TICKLESS select ARCH_DMA_NO_FLASH_TRANSFER @@ -373,7 +370,6 @@ config ARCH_CHIP_RP2040 select ARCH_HAVE_MULTICPU select ARCH_HAVE_I2CRESET select ARM_HAVE_WFE_SEV - select ARCH_HAVE_PWM_MULTICHAN select ARCH_BOARD_COMMON select ARCH_HAVE_CUSTOM_TESTSET ---help--- @@ -389,7 +385,6 @@ config ARCH_CHIP_RP23XX select ARM_HAVE_DSP select ARCH_HAVE_FPU select ARCH_HAVE_CUSTOM_TESTSET - select ARCH_HAVE_PWM_MULTICHAN select ARCH_BOARD_COMMON ---help--- Raspberry Pi RP23XX architectures (ARM dual Cortex-M33 or RISC-V). diff --git a/arch/arm/src/at32/Kconfig b/arch/arm/src/at32/Kconfig index de2c0fe52802c..6d43630fef065 100644 --- a/arch/arm/src/at32/Kconfig +++ b/arch/arm/src/at32/Kconfig @@ -3651,7 +3651,6 @@ config AT32_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n depends on AT32_PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. diff --git a/arch/arm/src/at32/at32_pwm.c b/arch/arm/src/at32/at32_pwm.c index 919e4fa525e78..3867f59c220c3 100644 --- a/arch/arm/src/at32/at32_pwm.c +++ b/arch/arm/src/at32/at32_pwm.c @@ -2168,11 +2168,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(channel == priv->channels[0].channel); - DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); -#endif - /* Get the reload values */ reload = pwm_arr_get(dev); @@ -3219,13 +3214,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, pwminfo("TIM%u channel: %u frequency: %" PRIx32 " duty: %08" PRIx32 " count: %" PRIx32 "\n", priv->timid, priv->channels[0].channel, info->frequency, - info->duty, info->count); + info->channels[0].duty, info->channels[0].count); DEBUGASSERT(info->frequency > 0); /* Channel specific setup */ - duty = info->duty; + duty = info->channels[0].duty; channel = priv->channels[0].channel; /* Disable all interrupts and DMA requests, clear all pending status */ @@ -3254,7 +3249,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * assured us that the count value is within range). */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Save the remaining count and the number of counts that will have * elapsed on the first interrupt. @@ -3265,7 +3260,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * value. */ - priv->prev = pwm_pulsecount(info->count); + priv->prev = pwm_pulsecount(info->channels[0].count); pwm_rcr_update(dev, priv->prev - 1); /* Generate an update event to reload the prescaler. This should @@ -3278,8 +3273,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * update event. */ - priv->count = info->count; - priv->curr = pwm_pulsecount(info->count - priv->prev); + priv->count = info->channels[0].count; + priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev); pwm_rcr_update(dev, priv->curr - 1); } @@ -3308,12 +3303,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, goto errout; } - /* Setup update interrupt. If info->count is > 0, then we can be - * assured that pwm_pulsecount_start() has already verified: (1) that this - * is an advanced timer, and that (2) the repetition count is within range. + /* Setup update interrupt. If info->channels[0].count is > 0, then we can + * be assured that pwm_pulsecount_start() has already verified: (1) that + * this is an advanced timer, and that (2) the repetition count is within + * range. */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Clear all pending interrupts and enable the update interrupt. */ @@ -3467,16 +3463,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, uint8_t channel = 0; ub16_t duty = 0; int ret = OK; -#ifdef CONFIG_PWM_MULTICHAN int i = 0; int j = 0; -#endif -#ifdef CONFIG_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) -#endif { -#ifdef CONFIG_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -3509,10 +3500,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, ret = -EINVAL; goto errout; } -#else - duty = info->duty; - channel = priv->channels[0].channel; -#endif /* Update duty cycle */ @@ -3521,9 +3508,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, { goto errout; } -#ifdef CONFIG_PWM_MULTICHAN } -#endif } errout: @@ -3554,19 +3539,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); -#if defined(CONFIG_PWM_MULTICHAN) pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); -#else - pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", - priv->timid, priv->channels[0].channel, - info->frequency, info->duty); -#endif DEBUGASSERT(info->frequency > 0); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100)); -#endif /* TODO: what if we have pwm running and we want disable some channels ? */ @@ -4172,14 +4148,14 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev, /* Generate an indefinite number of pulses */ - if (info->count == 0) + if (info->channels[0].count == 0) { return pwm_start(dev, info); } /* Check if a pulsecount has been selected */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Only the advanced timers (TIM1,8 can support the pulse counting) * REVISIT: verify if TIMTYPE_COUNTUP16_N works with it @@ -4188,7 +4164,7 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev, if (priv->timtype != TIMTYPE_ADVANCED) { pwmerr("ERROR: TIM%u cannot support pulse count: %" PRIx32 "\n", - priv->timid, info->count); + priv->timid, info->channels[0].count); return -EPERM; } } @@ -4213,7 +4189,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, if (info->frequency == priv->frequency) { -#ifdef CONFIG_PWM_MULTICHAN int i; for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) @@ -4233,9 +4208,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); } } -#else - ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty); -#endif /* CONFIG_PWM_MULTICHAN */ } else { diff --git a/arch/arm/src/at32/at32_pwm.h b/arch/arm/src/at32/at32_pwm.h index 2493aa2c0852b..e092de36cb84c 100644 --- a/arch/arm/src/at32/at32_pwm.h +++ b/arch/arm/src/at32/at32_pwm.h @@ -358,7 +358,7 @@ PWM_TIM20_CHANNEL3 + PWM_TIM20_CHANNEL4 + \ PWM_TIM20_CHANNEL5 + PWM_TIM20_CHANNEL6) -#else /* !CONFIG_PWM_MULTICHAN */ +#else /* !CONFIG_AT32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: diff --git a/arch/arm/src/cxd56xx/cxd56_pwm.c b/arch/arm/src/cxd56xx/cxd56_pwm.c index ff4b0a05b92cb..05d8bf92bd377 100644 --- a/arch/arm/src/cxd56xx/cxd56_pwm.c +++ b/arch/arm/src/cxd56xx/cxd56_pwm.c @@ -394,13 +394,13 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, uint32_t phase; int ret; - if (info->duty <= 0) + if (info->channels[0].duty <= 0) { /* Output low level if duty cycle is almost 0% */ PWM_REG(priv->ch)->EN = 0x0; } - else if (info->duty >= 65536) + else if (info->channels[0].duty >= 65536) { /* Output high level if duty cycle is almost 100% */ @@ -409,7 +409,8 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, } else { - ret = convert_freq2period(info->frequency, info->duty, ¶m, &phase); + ret = convert_freq2period(info->frequency, info->channels[0].duty, + ¶m, &phase); if (ret < 0) { return -EINVAL; diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c index 3ab728b9f62af..41ddea21f74df 100644 --- a/arch/arm/src/efm32/efm32_pwm.c +++ b/arch/arm/src/efm32/efm32_pwm.c @@ -360,13 +360,14 @@ static int pwm_timer(struct efm32_pwmtimer_s *priv, #ifdef CONFIG_PWM_PULSECOUNT pwminfo("TIMER%d channel: %d frequency: %d duty: %08x count: %d\n", priv->timid, priv->channel, info->frequency, - info->duty, info->count); + info->channels[0].duty, info->channels[0].count); #else pwminfo("TIMER%d channel: %d frequency: %d duty: %08x\n", - priv->timid, priv->channel, info->frequency, info->duty); + priv->timid, priv->channel, info->frequency, + info->channels[0].duty); #endif - DEBUGASSERT(info->frequency > 0 && info->duty >= 0 && - info->duty < uitoub16(100)); + DEBUGASSERT(info->frequency > 0 && info->channels[0].duty >= 0 && + info->channels[0].duty < uitoub16(100)); efm32_timer_reset(priv->base); @@ -403,7 +404,8 @@ static int pwm_timer(struct efm32_pwmtimer_s *priv, pwm_putreg(priv, EFM32_TIMER_ROUTE_OFFSET, regval); - regval = (info->duty * pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16; + regval = (info->channels[0].duty * + pwm_getreg(priv, EFM32_TIMER_TOP_OFFSET)) >> 16; pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCV_OFFSET, regval); /* pwm_putreg(priv, cc_offet + EFM32_TIMER_CC_CCVB_OFFSET, regval); */ diff --git a/arch/arm/src/ht32f491x3/Kconfig b/arch/arm/src/ht32f491x3/Kconfig index edc081eff6cf7..bf039932f4b8b 100644 --- a/arch/arm/src/ht32f491x3/Kconfig +++ b/arch/arm/src/ht32f491x3/Kconfig @@ -63,7 +63,7 @@ config HT32F491X3_TMR1 config HT32F491X3_TMR1_PWM bool "TMR1 PWM output" default n - depends on HT32F491X3_TMR1 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR1 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR1. @@ -85,7 +85,7 @@ config HT32F491X3_TMR2 config HT32F491X3_TMR2_PWM bool "TMR2 PWM output" default n - depends on HT32F491X3_TMR2 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR2 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR2. @@ -107,7 +107,7 @@ config HT32F491X3_TMR3 config HT32F491X3_TMR3_PWM bool "TMR3 PWM output" default n - depends on HT32F491X3_TMR3 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR3 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR3. @@ -129,7 +129,7 @@ config HT32F491X3_TMR4 config HT32F491X3_TMR4_PWM bool "TMR4 PWM output" default n - depends on HT32F491X3_TMR4 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR4 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR4. @@ -165,7 +165,7 @@ config HT32F491X3_TMR9 config HT32F491X3_TMR9_PWM bool "TMR9 PWM output" default n - depends on HT32F491X3_TMR9 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR9 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR9. @@ -187,7 +187,7 @@ config HT32F491X3_TMR10 config HT32F491X3_TMR10_PWM bool "TMR10 PWM output" default n - depends on HT32F491X3_TMR10 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR10 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR10. @@ -208,7 +208,7 @@ config HT32F491X3_TMR11 config HT32F491X3_TMR11_PWM bool "TMR11 PWM output" default n - depends on HT32F491X3_TMR11 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR11 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR11. @@ -229,7 +229,7 @@ config HT32F491X3_TMR12 config HT32F491X3_TMR12_PWM bool "TMR12 PWM output" default n - depends on HT32F491X3_TMR12 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR12 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR12. @@ -251,7 +251,7 @@ config HT32F491X3_TMR13 config HT32F491X3_TMR13_PWM bool "TMR13 PWM output" default n - depends on HT32F491X3_TMR13 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR13 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR13. @@ -272,7 +272,7 @@ config HT32F491X3_TMR14 config HT32F491X3_TMR14_PWM bool "TMR14 PWM output" default n - depends on HT32F491X3_TMR14 && PWM && !PWM_MULTICHAN + depends on HT32F491X3_TMR14 && PWM && PWM_NCHANNELS = 1 ---help--- Enable lower-half PWM support on TMR14. diff --git a/arch/arm/src/ht32f491x3/ht32f491x3_pwm.c b/arch/arm/src/ht32f491x3/ht32f491x3_pwm.c index f87a0638174f6..cb6585e8801f2 100644 --- a/arch/arm/src/ht32f491x3/ht32f491x3_pwm.c +++ b/arch/arm/src/ht32f491x3/ht32f491x3_pwm.c @@ -73,13 +73,13 @@ struct ht32f491x3_pwmcfg_s struct ht32f491x3_pwmtimer_s { - const struct pwm_ops_s *ops; + const struct pwm_ops_s *ops; FAR const struct ht32f491x3_pwmcfg_s *cfg; - uint32_t gpio_clken; - uintptr_t gpio_base; - uint8_t channel; - uint8_t pin; - uint8_t af; + uint32_t gpio_clken; + uintptr_t gpio_base; + uint8_t channel; + uint8_t pin; + uint8_t af; }; /**************************************************************************** @@ -345,7 +345,8 @@ static int pwm_timer(FAR struct ht32f491x3_pwmtimer_s *priv, } reload -= 1u; - pulse = (uint32_t)(((uint64_t)reload * info->duty + 0x8000ull) >> 16); + pulse = (uint32_t)(((uint64_t)reload * + info->channels[0].duty + 0x8000ull) >> 16); if (pulse > reload) { pulse = reload; diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index 22396545ef8fb..1190dce0b1843 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -298,7 +298,6 @@ config IMXRT_FLEXCAN2_FD config IMXRT_FLEXPWM bool default n - select ARCH_HAVE_PWM_MULTICHAN config IMXRT_LPI2C bool diff --git a/arch/arm/src/imxrt/imxrt_flexpwm.c b/arch/arm/src/imxrt/imxrt_flexpwm.c index 09f9164260ae7..3cc983c1ad58f 100644 --- a/arch/arm/src/imxrt/imxrt_flexpwm.c +++ b/arch/arm/src/imxrt/imxrt_flexpwm.c @@ -808,11 +808,7 @@ static int pwm_change_freq(struct pwm_lowerhalf_s *dev, uint8_t channel) { struct imxrt_flexpwm_s *priv = (struct imxrt_flexpwm_s *)dev; -#ifdef CONFIG_PWM_MULTICHAN uint8_t shift = (info->channels[channel].channel - 1) >> 1; -#else - uint8_t shift = priv->modules[0].module - 1; -#endif uint16_t regval; uint16_t olddiv = getreg16(priv->base + IMXRT_FLEXPWM_SM0VAL1_OFFSET + MODULE_OFFSET * shift); @@ -1219,7 +1215,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, { for (int i = 0; i < PWM_NCHANNELS; i++) { -#ifdef CONFIG_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -1233,9 +1228,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, { ret = pwm_change_freq(dev, info, i); } -#else - ret = pwm_change_freq(dev, info, i); -#endif } /* Save current frequency */ @@ -1246,7 +1238,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, } } -#ifdef CONFIG_PWM_MULTICHAN for (int i = 0; ret == OK && i < PWM_NCHANNELS; i++) { /* Break the loop if all following channels are not configured */ @@ -1268,15 +1259,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, ldok_map |= 1 << ((info->channels[i].channel - 1) >> 1); } } -#else - /* Enable PWM output just for first channel */ - - ret = pwm_set_output(dev, priv->modules[0].module, info->duty); - - /* Remember the channel number in bitmap */ - - ldok_map = 1 << (priv->modules[0].module - 1); -#endif /* CONFIG_PWM_MULTICHAN */ /* Set Load Okay bits */ @@ -1312,7 +1294,6 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) uint8_t shift; uint16_t regval; -#ifdef CONFIG_PWM_MULTICHAN for (int i = 0; i < priv->modules_num; i++) { /* Skip settings if channel is not configured */ @@ -1330,16 +1311,6 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) regval = OUTEN_PWMB_EN(0 << shift); putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); } -#else - shift = priv->modules[0].module - 1; - - regval = OUTEN_PWMA_EN(0 << shift); - putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); - - regval = OUTEN_PWMB_EN(0 << shift); - putreg16(regval, priv->base + IMXRT_FLEXPWM_OUTEN_OFFSET); - -#endif /* CONFIG_PWM_MULTICHAN */ return OK; } diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c index b023a8617f312..9285afab9e9fc 100644 --- a/arch/arm/src/kinetis/kinetis_pwm.c +++ b/arch/arm/src/kinetis/kinetis_pwm.c @@ -365,10 +365,11 @@ static int pwm_timer(struct kinetis_pwmtimer_s *priv, DEBUGASSERT(priv != NULL && info != NULL); pwminfo("FTM%d channel: %d frequency: %" PRId32 " duty: %08" PRIx32 "\n", - priv->tpmid, priv->channel, info->frequency, info->duty); + priv->tpmid, priv->channel, info->frequency, + info->channels[0].duty); - DEBUGASSERT(info->frequency > 0 && info->duty > 0 && - info->duty < uitoub16(100)); + DEBUGASSERT(info->frequency > 0 && info->channels[0].duty > 0 && + info->channels[0].duty < uitoub16(100)); /* Calculate optimal values for the timer prescaler and for the timer * modulo register. If' frequency' is the desired frequency, then @@ -432,7 +433,7 @@ static int pwm_timer(struct kinetis_pwmtimer_s *priv, * duty cycle = cv / modulo (fractional value) */ - cv = b16toi(info->duty * modulo + b16HALF); + cv = b16toi(info->channels[0].duty * modulo + b16HALF); pwminfo("FTM%d PCLK: %" PRId32 " frequency: %" PRIx32 " FTMCLK: %" PRIx32 " prescaler: %d modulo: %" PRId32 " c0v: %" PRId32 "\n", diff --git a/arch/arm/src/kl/kl_pwm.c b/arch/arm/src/kl/kl_pwm.c index 0c8e2ef0cca22..2659edf5a4433 100644 --- a/arch/arm/src/kl/kl_pwm.c +++ b/arch/arm/src/kl/kl_pwm.c @@ -331,10 +331,11 @@ static int pwm_timer(struct kl_pwmtimer_s *priv, DEBUGASSERT(priv != NULL && info != NULL); pwminfo("TPM%d channel: %d frequency: %" PRId32 " duty: %08" PRIx32 "\n", - priv->tpmid, priv->channel, info->frequency, info->duty); + priv->tpmid, priv->channel, info->frequency, + info->channels[0].duty); - DEBUGASSERT(info->frequency > 0 && info->duty > 0 && - info->duty < uitoub16(100)); + DEBUGASSERT(info->frequency > 0 && info->channels[0].duty > 0 && + info->channels[0].duty < uitoub16(100)); /* Calculate optimal values for the timer prescaler and for the timer * modulo register. If' frequency' is the desired frequency, then @@ -398,7 +399,7 @@ static int pwm_timer(struct kl_pwmtimer_s *priv, * duty cycle = cv / modulo (fractional value) */ - cv = b16toi(info->duty * modulo + b16HALF); + cv = b16toi(info->channels[0].duty * modulo + b16HALF); pwminfo("TPM%d PCLK: %" PRId32 " frequency: %" PRId32 " TPMCLK: %" PRId32 " prescaler: %d modulo: %" PRId32 " c0v: %" PRId32 "\n", diff --git a/arch/arm/src/lpc17xx_40xx/Kconfig b/arch/arm/src/lpc17xx_40xx/Kconfig index 38b305fbffe5f..d26d3d87356bf 100644 --- a/arch/arm/src/lpc17xx_40xx/Kconfig +++ b/arch/arm/src/lpc17xx_40xx/Kconfig @@ -348,7 +348,6 @@ config LPC17_40_PWM0 config LPC17_40_PWM1 bool "PWM1" - select ARCH_HAVE_PWM_MULTICHAN default n config LPC17_40_PWM1_PIN diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_mcpwm.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_mcpwm.c index 0746a51b8a091..22ed4f55e9570 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_mcpwm.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_mcpwm.c @@ -268,8 +268,13 @@ static int mcpwm_timer(struct lpc17_40_mcpwmtimer_s *priv, flags = enter_critical_section(); - putreg32(info->frequency, LPC17_40_MCPWM_LIM0); /* Set PWMMR0 = number of counts */ - putreg32(info->duty, LPC17_40_MCPWM_MAT0); /* Set PWM cycle */ + /* Set PWMMR0 = number of counts */ + + putreg32(info->frequency, LPC17_40_MCPWM_LIM0); + + /* Set PWM cycle */ + + putreg32(info->channels[0].duty, LPC17_40_MCPWM_MAT0); leave_critical_section(flags); mcpwm_dumpregs(priv, "After starting"); diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c index ffd8fa0676f5f..fc1e9d1bd7b9d 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c @@ -296,7 +296,6 @@ static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv, pwm_getreg(priv, LPC17_40_PWM_PC_OFFSET)); pwminfo(" MCR: %04x\n", pwm_getreg(priv, LPC17_40_PWM_MCR_OFFSET)); -#ifdef CONFIG_PWM_MULTICHAN pwminfo(" 0: %08x 1: %08x 2: %08x 3: %08x\n", pwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET), pwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET), @@ -306,7 +305,6 @@ static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv, pwm_getreg(priv, LPC17_40_PWM_MR4_OFFSET), pwm_getreg(priv, LPC17_40_PWM_MR5_OFFSET), pwm_getreg(priv, LPC17_40_PWM_MR6_OFFSET)); -#endif } #endif @@ -341,9 +339,6 @@ static int pwm_timer(struct lpc17_40_pwmtimer_s *priv, putreg32(mr0_freq, LPC17_40_PWM1_MR0); /* Set PWMMR0 = number of counts */ -#ifndef CONFIG_PWM_MULTICHAN - putreg32(info->duty, LPC17_40_PWM1_MR1); /* Set PWM cycle */ -#else for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) { switch (priv->channels[i].channel) @@ -398,7 +393,6 @@ static int pwm_timer(struct lpc17_40_pwmtimer_s *priv, } } } -#endif #ifdef CONFIG_LPC17_40_PWM1_CHANNEL1 pcrval |= PWMENA1; diff --git a/arch/arm/src/nrf52/nrf52_pwm.c b/arch/arm/src/nrf52/nrf52_pwm.c index b229c9e335a01..537dd161cb94f 100644 --- a/arch/arm/src/nrf52/nrf52_pwm.c +++ b/arch/arm/src/nrf52/nrf52_pwm.c @@ -68,9 +68,6 @@ struct nrf52_pwm_s uint32_t ch1_pin; /* Channel 2 pin */ uint32_t ch2_pin; /* Channel 3 pin */ uint32_t ch3_pin; /* Channel 4 pin */ -#ifndef CONFIG_PWM_MULTICHAN - uint8_t channel; /* Assigned channel */ -#endif /* Sequence 0 */ @@ -148,9 +145,6 @@ struct nrf52_pwm_s g_nrf52_pwm0 = #ifdef CONFIG_NRF52_PWM0_CH3 .ch3_pin = NRF52_PWM0_CH3_PIN, #endif -#ifndef CONFIG_PWM_MULTICHAN - .channel = CONFIG_NRF52_PWM0_CHANNEL -#endif }; #endif @@ -173,9 +167,6 @@ struct nrf52_pwm_s g_nrf52_pwm1 = #ifdef CONFIG_NRF52_PWM1_CH3 .ch3_pin = NRF52_PWM1_CH3_PIN, #endif -#ifndef CONFIG_PWM_MULTICHAN - .channel = CONFIG_NRF52_PWM1_CHANNEL -#endif }; #endif @@ -198,9 +189,6 @@ struct nrf52_pwm_s g_nrf52_pwm2 = #ifdef CONFIG_NRF52_PWM2_CH3 .ch3_pin = NRF52_PWM2_CH3_PIN, #endif -#ifndef CONFIG_PWM_MULTICHAN - .channel = CONFIG_NRF52_PWM2_CHANNEL -#endif }; #endif @@ -223,9 +211,6 @@ struct nrf52_pwm_s g_nrf52_pwm3 = #ifdef CONFIG_NRF52_PWM3_CH3 .ch3_pin = NRF52_PWM3_CH3_PIN, #endif -#ifndef CONFIG_PWM_MULTICHAN - .channel = CONFIG_NRF52_PWM3_CHANNEL -#endif }; #endif @@ -568,9 +553,7 @@ static int nrf52_pwm_start(struct pwm_lowerhalf_s *dev, { struct nrf52_pwm_s *priv = (struct nrf52_pwm_s *)dev; int ret = OK; -#ifdef CONFIG_PWM_MULTICHAN - int i = 0; -#endif + int i; DEBUGASSERT(dev); @@ -588,29 +571,24 @@ static int nrf52_pwm_start(struct pwm_lowerhalf_s *dev, } } -#ifdef CONFIG_PWM_MULTICHAN - for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) - { - /* Break the loop if all following channels are not configured */ + for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) + { + /* Break the loop if all following channels are not configured */ - if (info->channels[i].channel == -1) - { - break; - } + if (info->channels[i].channel == -1) + { + break; + } - /* Set output if channel configured */ + /* Set output if channel configured */ - if (info->channels[i].channel != 0) - { - ret = nrf52_pwm_duty(priv, - (info->channels[i].channel - 1), - info->channels[i].duty); - } + if (info->channels[i].channel != 0) + { + ret = nrf52_pwm_duty(priv, + (info->channels[i].channel - 1), + info->channels[i].duty); } - -#else - ret = nrf52_pwm_duty(priv, priv->channel, info->duty); -#endif /* CONFIG_PWM_MULTICHAN */ + } /* Start sequence 0 */ diff --git a/arch/arm/src/nrf53/nrf53_pwm.c b/arch/arm/src/nrf53/nrf53_pwm.c index b57f4a965c1cf..ba17aca3ba730 100644 --- a/arch/arm/src/nrf53/nrf53_pwm.c +++ b/arch/arm/src/nrf53/nrf53_pwm.c @@ -68,9 +68,6 @@ struct nrf53_pwm_s uint32_t ch1_pin; /* Channel 2 pin */ uint32_t ch2_pin; /* Channel 3 pin */ uint32_t ch3_pin; /* Channel 4 pin */ -#ifndef CONFIG_PWM_MULTICHAN - uint8_t channel; /* Assigned channel */ -#endif /* Sequence 0 */ @@ -148,9 +145,6 @@ struct nrf53_pwm_s g_nrf53_pwm0 = #ifdef CONFIG_NRF53_PWM0_CH3 .ch3_pin = NRF53_PWM0_CH3_PIN, #endif -#ifndef CONFIG_PWM_MULTICHAN - .channel = CONFIG_NRF53_PWM0_CHANNEL -#endif }; #endif @@ -173,9 +167,6 @@ struct nrf53_pwm_s g_nrf53_pwm1 = #ifdef CONFIG_NRF53_PWM1_CH3 .ch3_pin = NRF53_PWM1_CH3_PIN, #endif -#ifndef CONFIG_PWM_MULTICHAN - .channel = CONFIG_NRF53_PWM1_CHANNEL -#endif }; #endif @@ -198,9 +189,6 @@ struct nrf53_pwm_s g_nrf53_pwm2 = #ifdef CONFIG_NRF53_PWM2_CH3 .ch3_pin = NRF53_PWM2_CH3_PIN, #endif -#ifndef CONFIG_PWM_MULTICHAN - .channel = CONFIG_NRF53_PWM2_CHANNEL -#endif }; #endif @@ -543,9 +531,7 @@ static int nrf53_pwm_start(struct pwm_lowerhalf_s *dev, { struct nrf53_pwm_s *priv = (struct nrf53_pwm_s *)dev; int ret = OK; -#ifdef CONFIG_PWM_MULTICHAN int i = 0; -#endif DEBUGASSERT(dev); @@ -563,29 +549,24 @@ static int nrf53_pwm_start(struct pwm_lowerhalf_s *dev, } } -#ifdef CONFIG_PWM_MULTICHAN - for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) - { - /* Break the loop if all following channels are not configured */ + for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) + { + /* Break the loop if all following channels are not configured */ - if (info->channels[i].channel == -1) - { - break; - } + if (info->channels[i].channel == -1) + { + break; + } - /* Set output if channel configured */ + /* Set output if channel configured */ - if (info->channels[i].channel != 0) - { - ret = nrf53_pwm_duty(priv, - (info->channels[i].channel - 1), - info->channels[i].duty); - } + if (info->channels[i].channel != 0) + { + ret = nrf53_pwm_duty(priv, + (info->channels[i].channel - 1), + info->channels[i].duty); } - -#else - ret = nrf53_pwm_duty(priv, priv->channel, info->duty); -#endif /* CONFIG_PWM_MULTICHAN */ + } /* Start sequence 0 */ diff --git a/arch/arm/src/ra4/ra_pwm.c b/arch/arm/src/ra4/ra_pwm.c index b8f61e0a8b9b6..dc08e09441757 100644 --- a/arch/arm/src/ra4/ra_pwm.c +++ b/arch/arm/src/ra4/ra_pwm.c @@ -556,13 +556,14 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, } /* Calculate the duty cycle register value. - * info->duty is a 16-bit value (0..65535). To avoid 64-bit math we - * can split the 32-bit period into high and low 16-bit parts + * info->channels[0].duty is a 16-bit value (0..65535). + * To avoid 64-bit math we can split the 32-bit period into high + * and low 16-bit parts */ hi = period >> 16; lo = period & 0xffff; - duty16 = (uint32_t)info->duty; + duty16 = (uint32_t)info->channels[0].duty; duty = hi * duty16; @@ -578,7 +579,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, /* Save the frequency and duty cycle settings */ priv->frequency = info->frequency; - priv->duty = info->duty; + priv->duty = info->channels[0].duty; /* Stop the timer */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_pwm.c b/arch/arm/src/s32k1xx/s32k1xx_pwm.c index ff5e034165af2..b62e69be74e46 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pwm.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pwm.c @@ -360,10 +360,11 @@ static int pwm_timer(struct s32k1xx_pwmtimer_s *priv, DEBUGASSERT(priv != NULL && info != NULL); pwminfo("FTM%d channel: %d frequency: %" PRId32 " duty: %08" PRIx32 "\n", - priv->tpmid, priv->channel, info->frequency, info->duty); + priv->tpmid, priv->channel, info->frequency, + info->channels[0].duty); - DEBUGASSERT(info->frequency > 0 && info->duty > 0 && - info->duty < uitoub16(100)); + DEBUGASSERT(info->frequency > 0 && info->channels[0].duty > 0 && + info->channels[0].duty < uitoub16(100)); /* Calculate optimal values for the timer prescaler and for the timer * modulo register. If' frequency' is the desired frequency, then @@ -427,7 +428,7 @@ static int pwm_timer(struct s32k1xx_pwmtimer_s *priv, * duty cycle = cv / modulo (fractional value) */ - cv = b16toi(info->duty * modulo + b16HALF); + cv = b16toi(info->channels[0].duty * modulo + b16HALF); pwminfo("FTM%d PCLK: %" PRId32 " frequency: %" PRId32 " FTMCLK: %" PRId32 " prescaler: %d modulo: %" PRId32 "c0v: %" PRId32 "\n", diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index 3fdf244d7d2d2..f3f23a62fc6b0 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -1022,7 +1022,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, * to the CTDY (vs. the CTDYUPD) register. */ - regval = b16toi(info->duty * cprd + b16HALF); + regval = b16toi(info->channels[0].duty * cprd + b16HALF); if (regval > cprd) { /* Rounding up could cause the duty value to exceed CPRD (?) */ diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 3a3c6f6500d24..067ad3fb160d7 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -387,7 +387,6 @@ config SAMV7_HAVE_MEDIALB config SAMV7_PWM bool default n - select ARCH_HAVE_PWM_MULTICHAN select ARCH_HAVE_PWM_OVERWRITE select ARCH_HAVE_PWM_DEADTIME @@ -742,7 +741,6 @@ if SAMV7_PWM0 config SAMV7_PWM0_SYNC bool "PWM0 synchronous channels" - depends on PWM_MULTICHAN default n ---help--- This option makes the synchronization between channels possible. @@ -1097,7 +1095,6 @@ if SAMV7_PWM1 config SAMV7_PWM1_SYNC bool "PWM1 synchronous channels" - depends on PWM_MULTICHAN default n ---help--- This option makes the synchronization between channels possible. diff --git a/arch/arm/src/samv7/sam_pwm.c b/arch/arm/src/samv7/sam_pwm.c index e350c734348dd..3c00fad5a5245 100644 --- a/arch/arm/src/samv7/sam_pwm.c +++ b/arch/arm/src/samv7/sam_pwm.c @@ -963,7 +963,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { struct sam_pwm_s *priv = (struct sam_pwm_s *)dev; -#ifdef CONFIG_PWM_MULTICHAN uint32_t regval; for (int i = 0; i < PWM_NCHANNELS; i++) @@ -1036,18 +1035,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, pwm_putreg(priv, SAMV7_PWM_ENA, CHID_SEL(1)); pwm_putreg(priv, SAMV7_PWM_SCUC, regval); } -#else - /* Set the frequency and enable PWM output just for first channel */ - - pwm_set_freq(dev, priv->channels[0].channel, info->frequency); -#ifdef CONFIG_PWM_DEADTIME - pwm_set_deadtime(dev, priv->channels[0].channel, - info->dead_time_a, info->dead_time_b); -#endif - pwm_set_polarity(dev, priv->channels[0].channel, - info->cpol, info->dcpol); - pwm_set_output(dev, priv->channels[0].channel, info->duty); -#endif pwm_set_comparison(dev); @@ -1078,7 +1065,6 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) struct sam_pwm_s *priv = (struct sam_pwm_s *)dev; uint32_t regval; -#ifdef CONFIG_PWM_MULTICHAN for (int i = 0; i < priv->channels_num; i++) { regval = CHID_SEL(1 << priv->channels[i].channel); @@ -1091,10 +1077,6 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) regval &= ~(CHID_SEL(1 << 0) | CHID_SEL(1 << 1) | CHID_SEL(1 << 2) | CHID_SEL(1 << 3)); pwm_putreg(priv, SAMV7_PWM_SCM, regval); -#else - regval = CHID_SEL(1 << priv->channels[0].channel); - pwm_putreg(priv, SAMV7_PWM_DIS, regval); -#endif /* CONFIG_PWM_MULTICHAN */ return OK; } diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 6f1c879e8305a..97dcf898a3fe4 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -6034,7 +6034,6 @@ config STM32_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n depends on STM32_PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index b94348176f52d..fd1b45f1647a2 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -2321,11 +2321,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(channel == priv->channels[0].channel); - DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); -#endif - /* Get the reload values */ reload = pwm_arr_get(dev); @@ -3372,13 +3367,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, pwminfo("TIM%u channel: %u frequency: %" PRIx32 " duty: %08" PRIx32 " count: %" PRIx32 "\n", priv->timid, priv->channels[0].channel, info->frequency, - info->duty, info->count); + info->channels[0].duty, info->channels[0].count); DEBUGASSERT(info->frequency > 0); /* Channel specific setup */ - duty = info->duty; + duty = info->channels[0].duty; channel = priv->channels[0].channel; /* Disable all interrupts and DMA requests, clear all pending status */ @@ -3407,7 +3402,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * assured us that the count value is within range). */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Save the remaining count and the number of counts that will have * elapsed on the first interrupt. @@ -3418,7 +3413,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * value. */ - priv->prev = pwm_pulsecount(info->count); + priv->prev = pwm_pulsecount(info->channels[0].count); pwm_rcr_update(dev, priv->prev - 1); /* Generate an update event to reload the prescaler. This should @@ -3431,8 +3426,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * update event. */ - priv->count = info->count; - priv->curr = pwm_pulsecount(info->count - priv->prev); + priv->count = info->channels[0].count; + priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev); pwm_rcr_update(dev, priv->curr - 1); } @@ -3461,12 +3456,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, goto errout; } - /* Setup update interrupt. If info->count is > 0, then we can be - * assured that pwm_pulsecount_start() has already verified: (1) that this - * is an advanced timer, and that (2) the repetition count is within range. + /* Setup update interrupt. If info->channels[0].count is > 0, then we can + * be assured that pwm_pulsecount_start() has already verified: (1) that + * this is an advanced timer, and that (2) the repetition count is within + * range. */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Clear all pending interrupts and enable the update interrupt. */ @@ -3620,16 +3616,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, uint8_t channel = 0; ub16_t duty = 0; int ret = OK; -#ifdef CONFIG_PWM_MULTICHAN int i = 0; int j = 0; -#endif -#ifdef CONFIG_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) -#endif { -#ifdef CONFIG_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -3662,10 +3653,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, ret = -EINVAL; goto errout; } -#else - duty = info->duty; - channel = priv->channels[0].channel; -#endif /* Update duty cycle */ @@ -3674,9 +3661,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, { goto errout; } -#ifdef CONFIG_PWM_MULTICHAN } -#endif } errout: @@ -3707,19 +3692,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); -#if defined(CONFIG_PWM_MULTICHAN) pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); -#else - pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", - priv->timid, priv->channels[0].channel, - info->frequency, info->duty); -#endif DEBUGASSERT(info->frequency > 0); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100)); -#endif /* TODO: what if we have pwm running and we want disable some channels ? */ @@ -4336,14 +4312,14 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev, /* Generate an indefinite number of pulses */ - if (info->count == 0) + if (info->channels[0].count == 0) { return pwm_start(dev, info); } /* Check if a pulsecount has been selected */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Only the advanced timers (TIM1,8 can support the pulse counting) * REVISIT: verify if TIMTYPE_COUNTUP16_N works with it @@ -4352,7 +4328,7 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev, if (priv->timtype != TIMTYPE_ADVANCED) { pwmerr("ERROR: TIM%u cannot support pulse count: %" PRIx32 "\n", - priv->timid, info->count); + priv->timid, info->channels[0].count); return -EPERM; } } @@ -4377,7 +4353,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, if (info->frequency == priv->frequency) { -#ifdef CONFIG_PWM_MULTICHAN int i; for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) @@ -4397,9 +4372,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); } } -#else - ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty); -#endif /* CONFIG_PWM_MULTICHAN */ } else { diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/stm32/stm32_pwm.h index 2a0f43500fe13..f2f7191bcf077 100644 --- a/arch/arm/src/stm32/stm32_pwm.h +++ b/arch/arm/src/stm32/stm32_pwm.h @@ -356,7 +356,7 @@ #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index a8080419ec9b2..ad53ee4d492c6 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -3126,7 +3126,6 @@ config STM32F0L0G0_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n depends on STM32F0L0G0_PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/stm32f0l0g0/stm32_pwm.c index 70da111baef58..2aff3c8e1f92e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.c @@ -852,9 +852,7 @@ static int stm32pwm_output_configure(struct stm32_pwmtimer_s *priv, static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, const struct pwm_info_s *info) { -#ifdef CONFIG_PWM_MULTICHAN int i; -#endif /* Calculated values */ @@ -884,24 +882,17 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, ccmr2 = stm32pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET); #endif -#if defined(CONFIG_PWM_MULTICHAN) - pwminfo("TIM%u frequency: %" PRIu32 "\n", - priv->timid, info->frequency); -#elif defined(CONFIG_PWM_PULSECOUNT) +#ifdef CONFIG_PWM_PULSECOUNT pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 " count: %u\n", priv->timid, priv->channels[0].channel, info->frequency, - info->duty, info->count); + info->channels[0].duty, info->channels[0].count); #else - pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", - priv->timid, priv->channels[0].channel, info->frequency, - info->duty); + pwminfo("TIM%u frequency: %" PRIu32 "\n", + priv->timid, info->frequency); #endif DEBUGASSERT(info->frequency > 0); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100)); -#endif /* Disable all interrupts and DMA requests, clear all pending status */ @@ -1080,7 +1071,7 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, */ #ifdef CONFIG_PWM_PULSECOUNT - if (info->count > 0) + if (info->channels[0].count > 0) { /* Save the remaining count and the number of counts that will have * elapsed on the first interrupt. @@ -1091,7 +1082,7 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, * value. */ - priv->prev = stm32pwm_pulsecount(info->count); + priv->prev = stm32pwm_pulsecount(info->channels[0].count); stm32pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->prev - 1); /* Generate an update event to reload the prescaler. This should @@ -1104,8 +1095,9 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, * update event. */ - priv->count = info->count; - priv->curr = stm32pwm_pulsecount(info->count - priv->prev); + priv->count = info->channels[0].count; + priv->curr = stm32pwm_pulsecount(info->channels[0].count + - priv->prev); stm32pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, priv->curr - 1); } @@ -1138,20 +1130,15 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, ocmode2 = 0; #endif -#ifdef CONFIG_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) -#endif { ub16_t duty; uint32_t chanmode; bool ocmbit = false; uint8_t channel; -#ifdef CONFIG_PWM_MULTICHAN int j; -#endif enum stm32_chanmode_e mode; -#ifdef CONFIG_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -1185,11 +1172,6 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, pwmerr("ERROR: No such channel: %u\n", channel); return -EINVAL; } -#else - duty = info->duty; - channel = priv->channels[0].channel; - mode = priv->channels[0].mode; -#endif /* Duty cycle: * @@ -1399,13 +1381,14 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, cr1 |= GTIM_CR1_ARPE; stm32pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); - /* Setup update interrupt. If info->count is > 0, then we can be - * assured that stm32pwm_start() has already verified: (1) that this is an - * advanced timer, and that (2) the repetition count is within range. + /* Setup update interrupt. If info->channels[0].count is > 0, then we can + * be assured that stm32pwm_start() has already verified: (1) that this + * is an advanced timer, and that (2) the repetition count is within + * range. */ #ifdef CONFIG_PWM_PULSECOUNT - if (info->count > 0) + if (info->channels[0].count > 0) { /* Clear all pending interrupts and enable the update interrupt. */ @@ -1468,11 +1451,6 @@ static int stm32pwm_update_duty(struct stm32_pwmtimer_s *priv, pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(channel == priv->channels[0].channel); - DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); -#endif - /* Get the reload values */ reload = stm32pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); @@ -1913,14 +1891,14 @@ static int stm32pwm_start(struct pwm_lowerhalf_s *dev, /* Check if a pulsecount has been selected */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Only the advanced timers (TIM1,8 can support the pulse counting) */ if (priv->timtype != TIMTYPE_ADVANCED) { pwmerr("ERROR: TIM%u cannot support pulse count: %u\n", - priv->timid, info->count); + priv->timid, info->channels[0].count); return -EPERM; } } @@ -1945,7 +1923,6 @@ static int stm32pwm_start(struct pwm_lowerhalf_s *dev, if (info->frequency == priv->frequency) { -#ifdef CONFIG_PWM_MULTICHAN int i; for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) @@ -1965,10 +1942,6 @@ static int stm32pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); } } -#else - ret = stm32pwm_update_duty(priv, priv->channels[0].channel, - info->duty); -#endif } else #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.h b/arch/arm/src/stm32f0l0g0/stm32_pwm.h index 58ff9e78fdc46..a603069ad130f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.h +++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.h @@ -105,8 +105,6 @@ defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ defined(CONFIG_STM32F0L0G0_TIM17_PWM) -#ifdef CONFIG_PWM_MULTICHAN - #ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1 # ifdef CONFIG_STM32F0L0G0_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT @@ -337,157 +335,6 @@ MAX(PWM_TIM16_NCHANNELS, \ PWM_TIM17_NCHANNELS)))))) -#else /* !CONFIG_PWM_MULTICHAN */ - -/* For each timer that is enabled for PWM usage, we need the following - * additional configuration settings: - * - * CONFIG_STM32F0L0G0_TIMx_CHANNEL - Specifies the timer output channel - * {1,..,4} PWM_TIMx_CHn - One of the values defined in - * chip/stm32*_pinmap.h. In the case where there are multiple pin - * selections, the correct setting must be provided in the arch/board/board.h - * file. - * - * NOTE: The STM32 timers are each capable of generating different signals on - * each of the four channels with different duty cycles. That capability is - * not supported by this driver: Only one output channel per timer. - */ - -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM1_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM1_CH1MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT -# define PWM_TIM1_CH1NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM1_CH2MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT -# define PWM_TIM1_CH2NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM1_CH3MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT -# define PWM_TIM1_CH3NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM1_CH4MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM1_CHANNEL" -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM2_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM2_CH1MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM2_CH2MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM2_CH3MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM2_CH4MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM2_CHANNEL" -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM3_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM3_CH1MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM3_CH2MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM3_CH3MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM3_CH4MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM3_CHANNEL" -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM14_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM14_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM14_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM14_CH1MODE CONFIG_STM32F0L0G0_TIM14_CHMODE -# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT -# define PWM_TIM14_CH1NCFG 0 -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM14_CHANNEL" -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM15_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM15_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM15_CH1MODE CONFIG_STM32F0L0G0_TIM15_CHMODE -# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT -# define PWM_TIM15_CH1NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM15_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM15_CH2MODE CONFIG_STM32F0L0G0_TIM15_CHMODE -# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM15_CHANNEL" -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM16_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM16_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM16_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM16_CH1MODE CONFIG_STM32F0L0G0_TIM16_CHMODE -# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT -# define PWM_TIM16_CH1NCFG 0 -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM16_CHANNEL" -# endif -#endif - -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM17_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM17_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM17_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM17_CH1MODE CONFIG_STM32F0L0G0_TIM17_CHMODE -# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT -# define PWM_TIM17_CH1NCFG 0 -# else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM17_CHANNEL" -# endif -#endif - -#define PWM_NCHANNELS 1 - -#endif - /* Complementary outputs support */ #if defined(CONFIG_STM32F0L0G0_TIM1_CH1NOUT) || defined(CONFIG_STM32F0L0G0_TIM1_CH2NOUT) || \ diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 650da62e9b84c..67581eecad46a 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -4658,7 +4658,6 @@ config STM32F7_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n depends on STM32F7_PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index d10551d86ae4c..41725c7dfec29 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -1926,11 +1926,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(channel == priv->channels[0].channel); - DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); -#endif - /* Get the reload values */ reload = pwm_arr_get(dev); @@ -2948,13 +2943,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, pwminfo("TIM%u channel: %u frequency: %" PRIx32 " duty: %08" PRIx32 " count: %" PRIx32 "\n", priv->timid, priv->channels[0].channel, info->frequency, - info->duty, info->count); + info->channels[0].duty, info->channels[0].count); DEBUGASSERT(info->frequency > 0); /* Channel specific setup */ - duty = info->duty; + duty = info->channels[0].duty; channel = priv->channels[0].channel; /* Disable all interrupts and DMA requests, clear all pending status */ @@ -2983,7 +2978,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * assured us that the count value is within range). */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Save the remaining count and the number of counts that will have * elapsed on the first interrupt. @@ -2994,7 +2989,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * value. */ - priv->prev = pwm_pulsecount(info->count); + priv->prev = pwm_pulsecount(info->channels[0].count); pwm_rcr_update(dev, priv->prev - 1); /* Generate an update event to reload the prescaler. This should @@ -3007,8 +3002,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * update event. */ - priv->count = info->count; - priv->curr = pwm_pulsecount(info->count - priv->prev); + priv->count = info->channels[0].count; + priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev); pwm_rcr_update(dev, priv->curr - 1); } @@ -3037,12 +3032,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, goto errout; } - /* Setup update interrupt. If info->count is > 0, then we can be - * assured that pwm_pulsecount_start() has already verified: (1) that this - * is an advanced timer, and that (2) the repetition count is within range. + /* Setup update interrupt. If info->channels[0].count is > 0, then we can + * be assured that pwm_pulsecount_start() has already verified: (1) that + * this is an advanced timer, and that (2) the repetition count is within + * range. */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Clear all pending interrupts and enable the update interrupt. */ @@ -3194,16 +3190,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, uint8_t channel = 0; ub16_t duty = 0; int ret = OK; -#ifdef CONFIG_PWM_MULTICHAN int i = 0; int j = 0; -#endif -#ifdef CONFIG_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) -#endif { -#ifdef CONFIG_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -3236,10 +3227,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, ret = -EINVAL; goto errout; } -#else - duty = info->duty; - channel = priv->channels[0].channel; -#endif /* Update duty cycle */ @@ -3248,9 +3235,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, { goto errout; } -#ifdef CONFIG_PWM_MULTICHAN } -#endif } errout: @@ -3281,19 +3266,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); -#if defined(CONFIG_PWM_MULTICHAN) pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); -#else - pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", - priv->timid, priv->channels[0].channel, - info->frequency, info->duty); -#endif DEBUGASSERT(info->frequency > 0); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100)); -#endif /* TODO: what if we have pwm running and we want disable some channels ? */ @@ -3882,21 +3858,21 @@ static int pwm_start_pulsecount(struct pwm_lowerhalf_s *dev, /* Generate an indefinite number of pulses */ - if (info->count == 0) + if (info->channels[0].count == 0) { return pwm_start(dev, info); } /* Check if a pulsecount has been selected */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Only the advanced timers (TIM1,8 can support the pulse counting) */ if (priv->timtype != TIMTYPE_ADVANCED) { pwmerr("ERROR: TIM%u cannot support pulse count: %" PRIx32 "\n", - priv->timid, info->count); + priv->timid, info->channels[0].count); return -EPERM; } } @@ -3921,7 +3897,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, if (info->frequency == priv->frequency) { -#ifdef CONFIG_PWM_MULTICHAN int i; for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) @@ -3941,9 +3916,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); } } -#else - ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty); -#endif /* CONFIG_PWM_MULTICHAN */ } else { diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 461a81969e973..06a7671301ab8 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -321,7 +321,7 @@ #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#else /* !CONFIG_PWM_MULTICHAN */ +#else /* !CONFIG_STM32F7_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index a7c0eaeba0c5e..96a140e409e0f 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -3373,7 +3373,6 @@ config STM32H5_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n depends on STM32H5_PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. diff --git a/arch/arm/src/stm32h5/stm32_pwm.c b/arch/arm/src/stm32h5/stm32_pwm.c index e86d9043814a3..26f8f92629400 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.c +++ b/arch/arm/src/stm32h5/stm32_pwm.c @@ -1991,11 +1991,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(channel == priv->channels[0].channel); - DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); -#endif - /* Get the reload values */ reload = pwm_arr_get(dev); @@ -3043,13 +3038,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n", priv->timid, priv->channels[0].channel, info->frequency, - info->duty, info->count); + info->channels[0].duty, info->channels[0].count); DEBUGASSERT(info->frequency > 0); /* Channel specific setup */ - duty = info->duty; + duty = info->channels[0].duty; channel = priv->channels[0].channel; mode = priv->channels[0].mode; @@ -3079,7 +3074,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * assured us that the count value is within range). */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Save the remaining count and the number of counts that will have * elapsed on the first interrupt. @@ -3090,7 +3085,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * value. */ - priv->prev = pwm_pulsecount(info->count); + priv->prev = pwm_pulsecount(info->channels[0].count); pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1); /* Generate an update event to reload the prescaler. This should @@ -3103,8 +3098,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * update event. */ - priv->count = info->count; - priv->curr = pwm_pulsecount(info->count - priv->prev); + priv->count = info->channels[0].count; + priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev); pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -3133,12 +3128,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, goto errout; } - /* Setup update interrupt. If info->count is > 0, then we can be - * assured that pwm_pulsecount_start() has already verified: (1) that this - * is an advanced timer, and that (2) the repetition count is within range. + /* Setup update interrupt. If info->channels[0].count is > 0, then we can + * be assured that pwm_pulsecount_start() has already verified: (1) that + * this is an advanced timer, and that (2) the repetition count is within + * range. */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Clear all pending interrupts and enable the update interrupt. */ @@ -3292,16 +3288,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, uint8_t channel = 0; ub16_t duty = 0; int ret = OK; -#ifdef CONFIG_PWM_MULTICHAN int i = 0; int j = 0; -#endif -#ifdef CONFIG_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) -#endif { -#ifdef CONFIG_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -3334,10 +3325,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, ret = -EINVAL; goto errout; } -#else - duty = info->duty; - channel = priv->channels[0].channel; -#endif /* Update duty cycle */ @@ -3346,9 +3333,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, { goto errout; } -#ifdef CONFIG_PWM_MULTICHAN } -#endif } errout: @@ -3379,19 +3364,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); -#if defined(CONFIG_PWM_MULTICHAN) pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); -#else - pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", - priv->timid, priv->channels[0].channel, - info->frequency, info->duty); -#endif DEBUGASSERT(info->frequency > 0); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100)); -#endif /* TODO: what if we have pwm running and we want disable some channels ? */ @@ -3976,7 +3952,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, /* Check if a pulsecount has been selected */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Only the advanced timers (TIM1,8 can support the pulse counting) * REVISIT: verify if TIMTYPE_COUNTUP16_N works with it @@ -3985,7 +3961,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, if (priv->timtype != TIMTYPE_ADVANCED) { pwmerr("ERROR: TIM%u cannot support pulse count: %u\n", - priv->timid, info->count); + priv->timid, info->channels[0].count); return -EPERM; } } @@ -4009,7 +3985,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, if (info->frequency == priv->frequency) { -#ifdef CONFIG_PWM_MULTICHAN int i; for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) @@ -4029,9 +4004,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); } } -#else - ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty); -#endif /* CONFIG_PWM_MULTICHAN */ } else { diff --git a/arch/arm/src/stm32h5/stm32_pwm.h b/arch/arm/src/stm32h5/stm32_pwm.h index 94ccee9e2163c..149de56fec9cd 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.h +++ b/arch/arm/src/stm32h5/stm32_pwm.h @@ -321,7 +321,7 @@ #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_PWM_MULTICHAN */ +#else /* !CONFIG_STM32H5_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 77000df43b8b8..3810e8f2c1df1 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -4312,7 +4312,6 @@ config STM32H7_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n depends on STM32H7_PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index 40354522c0348..10bd501b18997 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -1995,11 +1995,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(channel == priv->channels[0].channel); - DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); -#endif - /* Get the reload values */ reload = pwm_arr_get(dev); @@ -3047,13 +3042,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n", priv->timid, priv->channels[0].channel, info->frequency, - info->duty, info->count); + info->channels[0].duty, info->channels[0].count); DEBUGASSERT(info->frequency > 0); /* Channel specific setup */ - duty = info->duty; + duty = info->channels[0].duty; channel = priv->channels[0].channel; mode = priv->channels[0].mode; @@ -3083,7 +3078,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * assured us that the count value is within range). */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Save the remaining count and the number of counts that will have * elapsed on the first interrupt. @@ -3094,7 +3089,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * value. */ - priv->prev = pwm_pulsecount(info->count); + priv->prev = pwm_pulsecount(info->channels[0].count); pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1); /* Generate an update event to reload the prescaler. This should @@ -3107,8 +3102,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * update event. */ - priv->count = info->count; - priv->curr = pwm_pulsecount(info->count - priv->prev); + priv->count = info->channels[0].count; + priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev); pwm_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -3137,12 +3132,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, goto errout; } - /* Setup update interrupt. If info->count is > 0, then we can be - * assured that pwm_pulsecount_start() has already verified: (1) that this - * is an advanced timer, and that (2) the repetition count is within range. + /* Setup update interrupt. If info->channels[0].count is > 0, then we can + * be assured that pwm_pulsecount_start() has already verified: (1) that + * this is an advanced timer, and that (2) the repetition count is within + * range. */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Clear all pending interrupts and enable the update interrupt. */ @@ -3296,16 +3292,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, uint8_t channel = 0; ub16_t duty = 0; int ret = OK; -#ifdef CONFIG_PWM_MULTICHAN int i = 0; int j = 0; -#endif -#ifdef CONFIG_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) -#endif { -#ifdef CONFIG_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -3338,10 +3329,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, ret = -EINVAL; goto errout; } -#else - duty = info->duty; - channel = priv->channels[0].channel; -#endif /* Update duty cycle */ @@ -3350,9 +3337,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, { goto errout; } -#ifdef CONFIG_PWM_MULTICHAN } -#endif } errout: @@ -3383,19 +3368,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); -#if defined(CONFIG_PWM_MULTICHAN) pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); -#else - pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", - priv->timid, priv->channels[0].channel, - info->frequency, info->duty); -#endif DEBUGASSERT(info->frequency > 0); -#ifndef CONFIG_PWM_MULTICHAN - DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100)); -#endif /* TODO: what if we have pwm running and we want disable some channels ? */ @@ -3980,7 +3956,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, /* Check if a pulsecount has been selected */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Only the advanced timers (TIM1,8 can support the pulse counting) * REVISIT: verify if TIMTYPE_COUNTUP16_N works with it @@ -3989,7 +3965,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, if (priv->timtype != TIMTYPE_ADVANCED) { pwmerr("ERROR: TIM%u cannot support pulse count: %u\n", - priv->timid, info->count); + priv->timid, info->channels[0].count); return -EPERM; } } @@ -4013,7 +3989,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, if (info->frequency == priv->frequency) { -#ifdef CONFIG_PWM_MULTICHAN int i; for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) @@ -4033,9 +4008,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); } } -#else - ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty); -#endif /* CONFIG_PWM_MULTICHAN */ } else { diff --git a/arch/arm/src/stm32h7/stm32_pwm.h b/arch/arm/src/stm32h7/stm32_pwm.h index 51018b7c790c4..bc6002af3bf19 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.h +++ b/arch/arm/src/stm32h7/stm32_pwm.h @@ -321,7 +321,7 @@ #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_PWM_MULTICHAN */ +#else /* !CONFIG_STM32H7_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index d1bb2326eef01..0731829dd6c71 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -3709,7 +3709,6 @@ config STM32L4_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n depends on STM32L4_PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 3c2825602e4f3..37a4ec2b6a569 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -1806,11 +1806,6 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, pwminfo("TIM%u channel: %u duty: %08" PRIx32 "\n", priv->timid, channel, duty); -#ifndef CONFIG_STM32L4_PWM_MULTICHAN - DEBUGASSERT(channel == priv->channels[0].channel); - DEBUGASSERT(duty >= 0 && duty < uitoub16(100)); -#endif - /* Get the reload values */ reload = pwm_arr_get(dev); @@ -2945,13 +2940,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n", priv->timid, priv->channels[0].channel, info->frequency, - info->duty, info->count); + info->channels[0].duty, info->channels[0].count); DEBUGASSERT(info->frequency > 0); /* Channel specific setup */ - duty = info->duty; + duty = info->channels[0].duty; channel = priv->channels[0].channel; /* Disable all interrupts and DMA requests, clear all pending status */ @@ -2980,7 +2975,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * assured us that the count value is within range). */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Save the remaining count and the number of counts that will have * elapsed on the first interrupt. @@ -2991,7 +2986,7 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * value. */ - priv->prev = pwm_pulsecount(info->count); + priv->prev = pwm_pulsecount(info->channels[0].count); pwm_putreg(priv, STM32L4_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1); /* Generate an update event to reload the prescaler. This should @@ -3004,8 +2999,8 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, * update event. */ - priv->count = info->count; - priv->curr = pwm_pulsecount(info->count - priv->prev); + priv->count = info->channels[0].count; + priv->curr = pwm_pulsecount(info->channels[0].count - priv->prev); pwm_putreg(priv, STM32L4_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -3034,12 +3029,13 @@ static int pwm_pulsecount_timer(struct pwm_lowerhalf_s *dev, goto errout; } - /* Setup update interrupt. If info->count is > 0, then we can be - * assured that pwm_pulsecount_start() has already verified: (1) that this - * is an advanced timer, and that (2) the repetition count is within range. + /* Setup update interrupt. If info->channels[0].count is > 0, then we can + * be assured that pwm_pulsecount_start() has already verified: (1) that + * this is an advanced timer, and that (2) the repetition count is within + * range. */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Clear all pending interrupts and enable the update interrupt. */ @@ -3078,16 +3074,11 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, uint8_t channel = 0; ub16_t duty = 0; int ret = OK; -#ifdef CONFIG_STM32L4_PWM_MULTICHAN int i = 0; int j = 0; -#endif -#ifdef CONFIG_STM32L4_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) -#endif { -#ifdef CONFIG_STM32L4_PWM_MULTICHAN /* Break the loop if all following channels are not configured */ if (info->channels[i].channel == -1) @@ -3120,10 +3111,6 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, ret = -EINVAL; goto errout; } -#else - duty = info->duty; - channel = priv->channels[0].channel; -#endif /* Update duty cycle */ @@ -3132,9 +3119,7 @@ static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, { goto errout; } -#ifdef CONFIG_STM32L4_PWM_MULTICHAN } -#endif } errout: @@ -3165,19 +3150,10 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); -#if defined(CONFIG_STM32L4_PWM_MULTICHAN) pwminfo("TIM%u frequency: %" PRIu32 "\n", priv->timid, info->frequency); -#else - pwminfo("TIM%u channel: %u frequency: %" PRIu32 " duty: %08" PRIx32 "\n", - priv->timid, priv->channels[0].channel, - info->frequency, info->duty); -#endif DEBUGASSERT(info->frequency > 0); -#ifndef CONFIG_STM32L4_PWM_MULTICHAN - DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100)); -#endif /* TODO: what if we have pwm running and we want disable some channels ? */ @@ -3272,19 +3248,10 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, DEBUGASSERT(priv != NULL && info != NULL); -#if defined(CONFIG_STM32L4_PWM_MULTICHAN) pwminfo("LPTIM%u frequency: %u\n", priv->timid, info->frequency); -#else - pwminfo("LPTIM%u channel: %u frequency: %u duty: %08x\n", - priv->timid, priv->channels[0].channel, - info->frequency, info->duty); -#endif DEBUGASSERT(info->frequency > 0); -#ifndef CONFIG_STM32L4_PWM_MULTICHAN - DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100)); -#endif /* Enable again, ARR and CMP need to be written while enabled */ @@ -3298,11 +3265,7 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, goto errout; } -#ifdef CONFIG_STM32L4_PWM_MULTICHAN ub16_t duty = info->channels[0].duty; -#else - ub16_t duty = info->duty; -#endif /* Update duty cycle */ @@ -3883,14 +3846,14 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, /* Check if a pulsecount has been selected */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Only the advanced timers (TIM1,8 can support the pulse counting) */ if (priv->timtype != TIMTYPE_ADVANCED) { pwmerr("ERROR: TIM%u cannot support pulse count: %u\n", - priv->timid, info->count); + priv->timid, info->channels[0].count); return -EPERM; } } @@ -3915,7 +3878,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, if (info->frequency == priv->frequency) { -#ifdef CONFIG_STM32L4_PWM_MULTICHAN int i; for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) @@ -3935,9 +3897,6 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); } } -#else - ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty); -#endif /* CONFIG_STM32L4_PWM_MULTICHAN */ } else { diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index 937c3165750cd..0c970b7f89cec 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -1700,7 +1700,6 @@ config STM32L5_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n depends on STM32L5_TIM1_PWM || STM32L5_TIM2_PWM || STM32L5_TIM3_PWM || STM32L5_TIM4_PWM || STM32L5_TIM5_PWM || STM32L5_TIM8_PWM || STM32L5_TIM15_PWM || STM32L5_TIM16_PWM || STM32L5_TIM17_PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 6f7992fe695ec..c9d61b3219f42 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -1998,7 +1998,6 @@ config STM32U5_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n depends on STM32U5_PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output channels per timer. diff --git a/arch/arm/src/tiva/common/tiva_pwm.c b/arch/arm/src/tiva/common/tiva_pwm.c index 487504dd80bc0..59612c58eda77 100644 --- a/arch/arm/src/tiva/common/tiva_pwm.c +++ b/arch/arm/src/tiva/common/tiva_pwm.c @@ -568,8 +568,8 @@ static int tiva_pwm_start(struct pwm_lowerhalf_s *dev, * Count should be add 1 for the first time */ - chan->count = info->count; - chan->cur_count = info->count; + chan->count = info->channels[0].count; + chan->cur_count = info->channels[0].count; if (!chan->inited) { @@ -580,7 +580,7 @@ static int tiva_pwm_start(struct pwm_lowerhalf_s *dev, /* Count 0 means to generate indefinite number of pulses */ - if (info->count == 0) + if (info->channels[0].count == 0) { pwm_expired(chan->handle); @@ -636,7 +636,7 @@ static int tiva_pwm_start(struct pwm_lowerhalf_s *dev, static inline int tiva_pwm_timer(struct tiva_pwm_chan_s *chan, const struct pwm_info_s *info) { - uint16_t duty = info->duty; + uint16_t duty = info->channels[0].duty; uint32_t frequency = info->frequency; pwminfo("> frequency = %d\n", frequency); diff --git a/arch/arm/src/tlsr82/tlsr82_pwm.c b/arch/arm/src/tlsr82/tlsr82_pwm.c index 7507a30fded4d..f4d8f9fcb07a7 100644 --- a/arch/arm/src/tlsr82/tlsr82_pwm.c +++ b/arch/arm/src/tlsr82/tlsr82_pwm.c @@ -308,12 +308,12 @@ static int pwm_config(struct tlsr82_pwmtimer_s *priv, pwminfo("PWM%d invert: %d frequency: %lu duty: %08lx\n", (int)priv->id, (int)priv->invert, info->frequency, - info->duty); + info->channels[0].duty); - if (info->frequency == 0 || info->duty >= uitoub16(100)) + if (info->frequency == 0 || info->channels[0].duty >= uitoub16(100)) { pwrerr("pwm info is invalid, fre: %lu duty: %08lx\n", - info->frequency, info->duty); + info->frequency, info->channels[0].duty); return -EINVAL; } @@ -331,10 +331,11 @@ static int pwm_config(struct tlsr82_pwmtimer_s *priv, max = (uint16_t)((g_pwmclk / info->frequency)); - cmp = (uint16_t)(((uint64_t)max * (uint64_t)info->duty) >> 16); + cmp = (uint16_t)(((uint64_t)max * (uint64_t)info->channels[0].duty) >> 16); pwminfo("PWM%d PCLK: %lu freq: %lu duty: %lu max: %u cmp: %u\n", - priv->id, g_pwmclk, info->frequency, info->duty, max, cmp); + priv->id, g_pwmclk, info->frequency, info->channels[0].duty, + max, cmp); priv->max = max; priv->cmp = cmp; @@ -616,25 +617,25 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, /* Check if a pulsecount has been selected */ - if (info->count > 0) + if (info->channels[0].count > 0) { /* Only the PWM0 support the pulse counting */ if (priv->id != 0) { pwmerr("ERROR: PWM%d cannot support pulse count: %lu\n", - priv->id, info->count); + priv->id, info->channels[0].count); return -EPERM; } - if (info->count > PWM_MAX_COUNT) + if (info->channels[0].count > PWM_MAX_COUNT) { pwmerr("ERROR: PWM0 count out of range, count: %lu, max: %d", - info->count, PWM_MAX_COUNT); + info->channels[0].count, PWM_MAX_COUNT); return -EINVAL; } - priv->count = info->count; + priv->count = info->channels[0].count; } /* Save the handle */ diff --git a/arch/arm/src/xmc4/xmc4_pwm.c b/arch/arm/src/xmc4/xmc4_pwm.c index d419d7008070d..527c0d0d42523 100644 --- a/arch/arm/src/xmc4/xmc4_pwm.c +++ b/arch/arm/src/xmc4/xmc4_pwm.c @@ -851,7 +851,7 @@ static int pwm_compute_config(struct xmc4_pwm_s *priv, uint32_t crs = 0; uint32_t f_pwm = info->frequency; - float duty_cycle = (1.0 - b16tof(info->duty)); + float duty_cycle = (1.0 - b16tof(info->channels[0].duty)); do { @@ -919,7 +919,7 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info) pwm_set_period_match(priv, prs); pwm_set_compare_match(priv, crs); - pwm_set_passive_level(priv, info->cpol); + pwm_set_passive_level(priv, info->channels[0].cpol); pwm_shadow_transfert(priv); } else @@ -933,7 +933,7 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info) pwm_set_compare_match(priv, crs); pwm_set_period_match(priv, prs); - pwm_set_passive_level(priv, info->cpol); + pwm_set_passive_level(priv, info->channels[0].cpol); pwm_shadow_transfert(priv); pwm_enable_slice_clock(priv); @@ -948,7 +948,7 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info) pwm_set_compare_match(priv, crs); pwm_set_period_match(priv, prs); - pwm_set_passive_level(priv, info->cpol); + pwm_set_passive_level(priv, info->channels[0].cpol); pwm_shadow_transfert(priv); pwm_enable_slice_clock(priv); @@ -956,17 +956,17 @@ static int pwm_timer(struct xmc4_pwm_s *priv, const struct pwm_info_s *info) } priv->frequency = info->frequency; - priv->duty = info->duty; + priv->duty = info->channels[0].duty; } else { /* Frequency doesn't change, update shadow transfer */ pwm_set_compare_match(priv, crs); - pwm_set_passive_level(priv, info->cpol); + pwm_set_passive_level(priv, info->channels[0].cpol); pwm_shadow_transfert(priv); - priv->duty = info->duty; + priv->duty = info->channels[0].duty; } return OK; diff --git a/arch/arm64/src/imx9/Kconfig b/arch/arm64/src/imx9/Kconfig index 415748b957e33..370ff134a5c3a 100644 --- a/arch/arm64/src/imx9/Kconfig +++ b/arch/arm64/src/imx9/Kconfig @@ -17,7 +17,6 @@ config ARCH_CHIP_IMX93 select ARMV8A_HAVE_GICv3 select ARCH_CORTEX_A55 if !IMX9_BOOTLOADER select ARCH_CORTEX_A53 if IMX9_BOOTLOADER - select ARCH_HAVE_PWM_MULTICHAN select ARCH_HAVE_RESET ---help--- EL3/OCRAM is a bad combination for atomic instructions, they don't work. @@ -67,7 +66,6 @@ endmenu # DMA Allocator Configuration config IMX9_FLEXIO_PWM bool - select PWM_MULTICHAN default n config IMX9_HAVE_ATF_FIRMWARE @@ -445,7 +443,6 @@ config IMX9_FLEXIO2_DSHOT_TX_TIMER config IMX9_TPM_PWM bool - select PWM_MULTICHAN default n config IMX9_TPM1_PWM diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index e7446507a96bd..a721da161dbee 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -261,7 +261,6 @@ config ARCH_CHIP_MPFS select ARCH_HAVE_ELF_EXECUTABLE select ARCH_HAVE_RESET select ARCH_HAVE_SPI_CS_CONTROL - select ARCH_HAVE_PWM_MULTICHAN select ARCH_HAVE_S_MODE select ARCH_RV_CPUID_MAP select ARCH_HAVE_PERF_EVENTS @@ -447,7 +446,6 @@ config ARCH_CHIP_RP23XX_RV select ARCH_RV_ISA_M select ARCH_RV_ISA_A select ARCH_RV_ISA_C - select ARCH_HAVE_PWM_MULTICHAN select ARCH_HAVE_RESET select ARCH_HAVE_MULTICPU select ARCH_HAVE_I2CRESET diff --git a/arch/risc-v/src/bl602/Kconfig b/arch/risc-v/src/bl602/Kconfig index d720ffd193562..39bc4c65b250e 100644 --- a/arch/risc-v/src/bl602/Kconfig +++ b/arch/risc-v/src/bl602/Kconfig @@ -18,7 +18,6 @@ config BL602_HAVE_UART0 select ARCH_HAVE_UART0 select UART0_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select ARCH_HAVE_PWM_MULTICHAN config BL602_UART0 bool diff --git a/arch/risc-v/src/bl602/bl602_pwm_lowerhalf.c b/arch/risc-v/src/bl602/bl602_pwm_lowerhalf.c index 722d371b083b6..5d2931aa208be 100644 --- a/arch/risc-v/src/bl602/bl602_pwm_lowerhalf.c +++ b/arch/risc-v/src/bl602/bl602_pwm_lowerhalf.c @@ -387,7 +387,7 @@ static int bl602_pwm_start(struct pwm_lowerhalf_s *dev, } #else bl602_pwm_freq(priv, 0, info->frequency); - bl602_pwm_duty(priv, 0, info->duty); + bl602_pwm_duty(priv, 0, info->channels[0].duty); pwm_channel_enable(0); #endif diff --git a/arch/risc-v/src/common/espressif/Kconfig b/arch/risc-v/src/common/espressif/Kconfig index 3c16ea9c4a2b6..89ecc9b85e950 100644 --- a/arch/risc-v/src/common/espressif/Kconfig +++ b/arch/risc-v/src/common/espressif/Kconfig @@ -1657,7 +1657,6 @@ config ESPRESSIF_LEDC bool "LEDC (PWM)" default n select PWM - select ARCH_HAVE_PWM_MULTICHAN config ESPRESSIF_SHA_ACCELERATOR bool "SHA Accelerator" @@ -3663,8 +3662,8 @@ if ESPRESSIF_LEDC_TIMER0 config ESPRESSIF_LEDC_TIMER0_CHANNELS int "Number of Timer 0 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + default 2 if PWM_NCHANNELS > 1 + default 1 if PWM_NCHANNELS = 1 range 0 6 config ESPRESSIF_LEDC_TIMER0_RESOLUTION @@ -3687,8 +3686,8 @@ if ESPRESSIF_LEDC_TIMER1 config ESPRESSIF_LEDC_TIMER1_CHANNELS int "Number of Timer 1 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + default 2 if PWM_NCHANNELS > 1 + default 1 if PWM_NCHANNELS = 1 range 0 6 config ESPRESSIF_LEDC_TIMER1_RESOLUTION @@ -3711,8 +3710,8 @@ if ESPRESSIF_LEDC_TIMER2 config ESPRESSIF_LEDC_TIMER2_CHANNELS int "Number of Timer 2 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + default 2 if PWM_NCHANNELS > 1 + default 1 if PWM_NCHANNELS = 1 range 0 6 config ESPRESSIF_LEDC_TIMER2_RESOLUTION @@ -3735,8 +3734,8 @@ if ESPRESSIF_LEDC_TIMER3 config ESPRESSIF_LEDC_TIMER3_CHANNELS int "Number of Timer 3 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + default 2 if PWM_NCHANNELS > 1 + default 1 if PWM_NCHANNELS = 1 range 0 6 config ESPRESSIF_LEDC_TIMER3_RESOLUTION @@ -3767,7 +3766,7 @@ config ESPRESSIF_LEDC_CHANNEL3_PIN int "Channel 3 pin" default 5 -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config ESPRESSIF_LEDC_CHANNEL4_PIN int "Channel 4 pin" @@ -3777,7 +3776,7 @@ config ESPRESSIF_LEDC_CHANNEL5_PIN int "Channel 5 pin" default 7 -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endmenu # LEDC configuration diff --git a/arch/risc-v/src/esp32c3-legacy/Kconfig b/arch/risc-v/src/esp32c3-legacy/Kconfig index 9401335db51f8..1fa55cc1fbbf4 100644 --- a/arch/risc-v/src/esp32c3-legacy/Kconfig +++ b/arch/risc-v/src/esp32c3-legacy/Kconfig @@ -185,7 +185,6 @@ config ESP32C3_LEDC bool "LEDC (PWM)" default n select PWM - select ARCH_HAVE_PWM_MULTICHAN config ESP32C3_GPIO_IRQ bool "GPIO pin interrupts" diff --git a/arch/risc-v/src/litex/litex_pwm.c b/arch/risc-v/src/litex/litex_pwm.c index acc9a119c59aa..01460c8ab8815 100644 --- a/arch/risc-v/src/litex/litex_pwm.c +++ b/arch/risc-v/src/litex/litex_pwm.c @@ -44,10 +44,11 @@ ****************************************************************************/ #ifdef CONFIG_PWM_PULSECOUNT -#error PWM puslecount not supported for Litex. +# error PWM pulsecount not supported for Litex. #endif -#ifdef CONFIG_PWM_MULTICHAN -#error PWM multichannel not supported for Litex. + +#if CONFIG_PWM_NCHANNELS > 1 +# error PWM multiple channels not supported for Litex. #endif /* Control register offsets from peripheral base address */ @@ -219,7 +220,7 @@ static int litex_pwm_start(struct pwm_lowerhalf_s *dev, const uint32_t min_in_duty = 1; update_frequency = priv->frequency != info->frequency; - update_duty = update_frequency | (priv->duty != info->duty); + update_duty = update_frequency | (priv->duty != info->channels[0].duty); DEBUGASSERT(dev); DEBUGASSERT(priv->base); @@ -260,8 +261,9 @@ static int litex_pwm_start(struct pwm_lowerhalf_s *dev, */ period = getreg32(priv->base + PWM_PERIOD_REG_OFFSET); - duty = period * (info->duty / (float)(max_in_duty - min_in_duty)); - priv->duty = info->duty; + duty = period * (info->channels[0].duty / (float)(max_in_duty - + min_in_duty)); + priv->duty = info->channels[0].duty; putreg32(duty, priv->base + PWM_WIDTH_REG_OFFSET); pwminfo("Update PWM duty to %lu\n", duty); diff --git a/arch/risc-v/src/mpfs/Kconfig b/arch/risc-v/src/mpfs/Kconfig index c070fa1666170..dc93fd7ce6336 100644 --- a/arch/risc-v/src/mpfs/Kconfig +++ b/arch/risc-v/src/mpfs/Kconfig @@ -609,7 +609,6 @@ config MPFS_HAVE_COREPWM config MPFS_COREPWM0 bool "CorePWM0 FPGA IP block configured" default n - select PWM_MULTICHAN depends on MPFS_HAVE_COREPWM config MPFS_COREPWM0_BASE @@ -632,7 +631,6 @@ config MPFS_COREPWM0_NCHANNELS config MPFS_COREPWM1 bool "CorePWM1 FPGA IP block configured" default n - select PWM_MULTICHAN depends on MPFS_HAVE_COREPWM config MPFS_COREPWM1_BASE diff --git a/arch/xtensa/src/common/espressif/Kconfig b/arch/xtensa/src/common/espressif/Kconfig index 16acce2297bd3..527b288567289 100644 --- a/arch/xtensa/src/common/espressif/Kconfig +++ b/arch/xtensa/src/common/espressif/Kconfig @@ -195,7 +195,6 @@ config ESPRESSIF_LEDC default n depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 select PWM - select ARCH_HAVE_PWM_MULTICHAN config ESPRESSIF_SHA_ACCELERATOR bool "SHA Accelerator" @@ -340,8 +339,8 @@ if ESPRESSIF_LEDC_TIMER0 config ESPRESSIF_LEDC_TIMER0_CHANNELS int "Number of Timer 0 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + default 2 if PWM_NCHANNELS > 1 + default 1 if PWM_NCHANNELS = 1 range 0 6 config ESPRESSIF_LEDC_TIMER0_RESOLUTION @@ -363,8 +362,8 @@ if ESPRESSIF_LEDC_TIMER1 config ESPRESSIF_LEDC_TIMER1_CHANNELS int "Number of Timer 1 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + default 2 if PWM_NCHANNELS > 1 + default 1 if PWM_NCHANNELS = 1 range 0 6 config ESPRESSIF_LEDC_TIMER1_RESOLUTION @@ -386,8 +385,8 @@ if ESPRESSIF_LEDC_TIMER2 config ESPRESSIF_LEDC_TIMER2_CHANNELS int "Number of Timer 2 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + default 2 if PWM_NCHANNELS > 1 + default 1 if PWM_NCHANNELS = 1 range 0 6 config ESPRESSIF_LEDC_TIMER2_RESOLUTION @@ -409,8 +408,8 @@ if ESPRESSIF_LEDC_TIMER3 config ESPRESSIF_LEDC_TIMER3_CHANNELS int "Number of Timer 3 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + default 2 if PWM_NCHANNELS > 1 + default 1 if PWM_NCHANNELS = 1 range 0 6 config ESPRESSIF_LEDC_TIMER3_RESOLUTION @@ -450,7 +449,7 @@ config ESPRESSIF_LEDC_CHANNEL3_PIN range 0 48 if ARCH_CHIP_ESP32S3 range 0 46 if ARCH_CHIP_ESP32S2 -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config ESPRESSIF_LEDC_CHANNEL4_PIN int "Channel 4 pin" @@ -476,7 +475,7 @@ config ESPRESSIF_LEDC_CHANNEL7_PIN range 0 48 if ARCH_CHIP_ESP32S3 range 0 46 if ARCH_CHIP_ESP32S2 -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # !ESP32_LEDC && !ESP32S2_LEDC && !ESP32S3_LEDC diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 6c5416adec40b..3836f0ac6bb2c 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -293,7 +293,6 @@ config ESP32_LEDC bool "LEDC (PWM)" default n select PWM - select ARCH_HAVE_PWM_MULTICHAN ---help--- Enable support to PWM on ESP32 using LEDC peripheral. diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig index 06cb50a61bc16..054de6066c827 100644 --- a/arch/xtensa/src/esp32s2/Kconfig +++ b/arch/xtensa/src/esp32s2/Kconfig @@ -544,7 +544,6 @@ config ESP32S2_LEDC bool "LEDC (PWM)" default n select PWM - select ARCH_HAVE_PWM_MULTICHAN select ESPRESSIF_LEDC ---help--- Enable support to PWM on ESP32S2 using LEDC peripheral. diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig index e5947d0f02fde..af1c9e69c8784 100644 --- a/arch/xtensa/src/esp32s3/Kconfig +++ b/arch/xtensa/src/esp32s3/Kconfig @@ -817,7 +817,6 @@ config ESP32S3_LEDC bool "LEDC (PWM)" default n select PWM - select ARCH_HAVE_PWM_MULTICHAN select ESPRESSIF_LEDC ---help--- Enable support to PWM on ESP32S3 using LEDC peripheral. diff --git a/boards/arm/imxrt/teensy-4.x/configs/pwm-4.1/defconfig b/boards/arm/imxrt/teensy-4.x/configs/pwm-4.1/defconfig index 706e3d3087b8a..ef402bffd3b06 100644 --- a/boards/arm/imxrt/teensy-4.x/configs/pwm-4.1/defconfig +++ b/boards/arm/imxrt/teensy-4.x/configs/pwm-4.1/defconfig @@ -40,7 +40,6 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=2 CONFIG_RAM_SIZE=1048576 CONFIG_RAM_START=0x20200000 diff --git a/boards/arm/nrf52/nrf52840-dk/configs/jumbo/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/jumbo/defconfig index 84d1d0f3255c1..5f6d3ea9b425a 100644 --- a/boards/arm/nrf52/nrf52840-dk/configs/jumbo/defconfig +++ b/boards/arm/nrf52/nrf52840-dk/configs/jumbo/defconfig @@ -60,7 +60,6 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=4 CONFIG_RAM_SIZE=65535 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/nrf53/nrf5340-dk/configs/pwm_cpuapp/defconfig b/boards/arm/nrf53/nrf5340-dk/configs/pwm_cpuapp/defconfig index 0a05c8e40a7cd..99755a1798764 100644 --- a/boards/arm/nrf53/nrf5340-dk/configs/pwm_cpuapp/defconfig +++ b/boards/arm/nrf53/nrf5340-dk/configs/pwm_cpuapp/defconfig @@ -40,7 +40,6 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=4 CONFIG_RAM_SIZE=524288 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/nrf53/thingy53/configs/rgbled_cpuapp/defconfig b/boards/arm/nrf53/thingy53/configs/rgbled_cpuapp/defconfig index 3367124cab73e..08c3447e411cc 100644 --- a/boards/arm/nrf53/thingy53/configs/rgbled_cpuapp/defconfig +++ b/boards/arm/nrf53/thingy53/configs/rgbled_cpuapp/defconfig @@ -53,7 +53,6 @@ CONFIG_NSH_READLINE=y CONFIG_NSH_USBCONSOLE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=3 CONFIG_RAMLOG=y CONFIG_RAM_SIZE=524288 diff --git a/boards/arm/nrf53/thingy53/include/board.h b/boards/arm/nrf53/thingy53/include/board.h index 409556001c677..078020de51ef8 100644 --- a/boards/arm/nrf53/thingy53/include/board.h +++ b/boards/arm/nrf53/thingy53/include/board.h @@ -137,14 +137,8 @@ * BLUE - P1.07 */ -#ifdef CONFIG_PWM_MULTICHAN # define NRF53_PWM0_CH0_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(8)) # define NRF53_PWM0_CH1_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(6)) # define NRF53_PWM0_CH2_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(7)) -#else -# define NRF53_PWM0_CH0_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(8)) -# define NRF53_PWM1_CH0_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(6)) -# define NRF53_PWM2_CH0_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT1 | GPIO_PIN(7)) -#endif #endif /* __BOARDS_ARM_NRF53_THINGY53_INCLUDE_BOARD_H */ diff --git a/boards/arm/nrf53/thingy53/src/nrf53_rgbled.c b/boards/arm/nrf53/thingy53/src/nrf53_rgbled.c index d96a031dbcefe..2c0e5ac1e7240 100644 --- a/boards/arm/nrf53/thingy53/src/nrf53_rgbled.c +++ b/boards/arm/nrf53/thingy53/src/nrf53_rgbled.c @@ -41,8 +41,6 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_PWM_MULTICHAN - /* PWM0 channels 0, 1 and 2 used */ # if !defined(CONFIG_NRF53_PWM0_CH0) || !defined(CONFIG_NRF53_PWM0_CH1) || \ @@ -50,16 +48,6 @@ # error Invalid configuration for RGBLED driver # endif -#else - -/* PWM0 channel 0, PWM1 channel 0 and PWM2 channel 0 used */ - -# if !defined(CONFIG_NRF53_PWM0_CH0) || !defined(CONFIG_NRF53_PWM1_CH0) || \ - !defined(CONFIG_NRF53_PWM2_CH0) -# error Invalid configuration for RGBLED driver -# endif -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -96,10 +84,6 @@ int nrf53_rgbled_initialize(void) /* Define frequency and duty cycle */ -#ifndef CONFIG_PWM_MULTICHAN - info.frequency = 100; - info.duty = 0; -#else ledg = ledr; ledb = ledr; @@ -107,50 +91,15 @@ int nrf53_rgbled_initialize(void) info.channels[0].duty = 0; info.channels[1].duty = 0; info.channels[2].duty = 0; -#endif /* Initialize LED R */ ledr->ops->setup(ledr); ledr->ops->start(ledr, &info); -#ifndef CONFIG_PWM_MULTICHAN - /* Call nrf53_pwminitialize() to get an instance of the PWM interface */ - - ledg = nrf53_pwminitialize(1); - if (!ledg) - { - lederr("ERROR: Failed to get the NRF53 PWM lower half to LEDG\n"); - return -ENODEV; - } - - /* Initialize LED G */ - - ledg->ops->setup(ledg); - ledg->ops->start(ledg, &info); - - /* Call nrf53_pwminitialize() to get an instance of the PWM interface */ - - ledb = nrf53_pwminitialize(2); - if (!ledb) - { - lederr("ERROR: Failed to get the NRF53 PWM lower half to LEDB\n"); - return -ENODEV; - } - - /* Initialize LED B */ - - ledb->ops->setup(ledb); - ledb->ops->start(ledb, &info); -#endif - /* Register the RGB LED diver at "/dev/rgbled0" */ -#ifdef CONFIG_PWM_MULTICHAN ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, 1, 2, 3); -#else - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb); -#endif if (ret < 0) { lederr("ERROR: rgbled_register failed: %d\n", ret); diff --git a/boards/arm/rp2040/common/Kconfig b/boards/arm/rp2040/common/Kconfig index 81b6ee497fa4e..cce9cc12dbef5 100644 --- a/boards/arm/rp2040/common/Kconfig +++ b/boards/arm/rp2040/common/Kconfig @@ -271,7 +271,7 @@ config RP2040_PWM0A_GPIO either 0 or 16, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP2040_PWM0B_GPIO int "GPIO pin for PWM0 channel 2 (1, 17 or -1:no assign)" @@ -282,7 +282,7 @@ config RP2040_PWM0B_GPIO either 1 or 17, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP2040_PWM0 @@ -299,7 +299,7 @@ config RP2040_PWM1A_GPIO either 2 or 18, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP2040_PWM1B_GPIO int "GPIO pin for PWM1 channel 2 (3, 19 or -1:no assign)" @@ -310,7 +310,7 @@ config RP2040_PWM1B_GPIO either 3 or 19, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP2040_PWM1 @@ -327,7 +327,7 @@ config RP2040_PWM2A_GPIO either 4 or 20, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP2040_PWM2B_GPIO int "GPIO pin for PWM2 channel 2 (5, 21 or -1:no assign)" @@ -338,7 +338,7 @@ config RP2040_PWM2B_GPIO either 5 or 21, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP2040_PWM2 @@ -355,7 +355,7 @@ config RP2040_PWM3A_GPIO either 6 or 22, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP2040_PWM3B_GPIO int "GPIO pin for PWM3 channel 2 (7, 23 or -1:no assign)" @@ -366,7 +366,7 @@ config RP2040_PWM3B_GPIO either 7 or 23, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP2040_PWM3 @@ -383,7 +383,7 @@ config RP2040_PWM4A_GPIO either 8 or 24, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP2040_PWM4B_GPIO int "GPIO pin for PWM4 channel 2 (9, 25 or -1:no assign)" @@ -394,7 +394,7 @@ config RP2040_PWM4B_GPIO either 9 or 25, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP2040_PWM4 @@ -411,7 +411,7 @@ config RP2040_PWM5A_GPIO either 10 or 26, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP2040_PWM5B_GPIO int "GPIO pin for PWM5 channel 2 (11, 27 or -1:no assign)" @@ -422,7 +422,7 @@ config RP2040_PWM5B_GPIO either 11 or 27, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP2040_PWM5 @@ -439,7 +439,7 @@ config RP2040_PWM6A_GPIO either 12 or 28, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP2040_PWM6B_GPIO int "GPIO pin for PWM6 channel 2 (13, 29 or -1:no assign)" @@ -450,7 +450,7 @@ config RP2040_PWM6B_GPIO either 13 or 29, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP2040_PWM6 @@ -467,7 +467,7 @@ config RP2040_PWM7A_GPIO either 14, any other value disables the output. Refer to board documentation to see if pin 14 is available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP2040_PWM7B_GPIO int "GPIO pin for PWM7 channel 2 (15 or -1:no assign)" @@ -478,7 +478,7 @@ config RP2040_PWM7B_GPIO either 15, any other value disables the output. Refer to board documentation to see if pin 15 is available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP2040_PWM7 diff --git a/boards/arm/rp23xx/common/Kconfig b/boards/arm/rp23xx/common/Kconfig index 9c42ae12b232d..aceef7ee7a0e6 100644 --- a/boards/arm/rp23xx/common/Kconfig +++ b/boards/arm/rp23xx/common/Kconfig @@ -272,7 +272,7 @@ config RP23XX_PWM0A_GPIO either 0 or 16, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_PWM0B_GPIO int "GPIO pin for PWM0 channel 2 (1, 17 or -1:no assign)" @@ -283,7 +283,7 @@ config RP23XX_PWM0B_GPIO either 1 or 17, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_PWM0 @@ -300,7 +300,7 @@ config RP23XX_PWM1A_GPIO either 2 or 18, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_PWM1B_GPIO int "GPIO pin for PWM1 channel 2 (3, 19 or -1:no assign)" @@ -311,7 +311,7 @@ config RP23XX_PWM1B_GPIO either 3 or 19, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_PWM1 @@ -328,7 +328,7 @@ config RP23XX_PWM2A_GPIO either 4 or 20, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_PWM2B_GPIO int "GPIO pin for PWM2 channel 2 (5, 21 or -1:no assign)" @@ -339,7 +339,7 @@ config RP23XX_PWM2B_GPIO either 5 or 21, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_PWM2 @@ -356,7 +356,7 @@ config RP23XX_PWM3A_GPIO either 6 or 22, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_PWM3B_GPIO int "GPIO pin for PWM3 channel 2 (7, 23 or -1:no assign)" @@ -367,7 +367,7 @@ config RP23XX_PWM3B_GPIO either 7 or 23, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_PWM3 @@ -384,7 +384,7 @@ config RP23XX_PWM4A_GPIO either 8 or 24, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_PWM4B_GPIO int "GPIO pin for PWM4 channel 2 (9, 25 or -1:no assign)" @@ -395,7 +395,7 @@ config RP23XX_PWM4B_GPIO either 9 or 25, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_PWM4 @@ -412,7 +412,7 @@ config RP23XX_PWM5A_GPIO either 10 or 26, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_PWM5B_GPIO int "GPIO pin for PWM5 channel 2 (11, 27 or -1:no assign)" @@ -423,7 +423,7 @@ config RP23XX_PWM5B_GPIO either 11 or 27, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_PWM5 @@ -440,7 +440,7 @@ config RP23XX_PWM6A_GPIO either 12 or 28, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_PWM6B_GPIO int "GPIO pin for PWM6 channel 2 (13, 29 or -1:no assign)" @@ -451,7 +451,7 @@ config RP23XX_PWM6B_GPIO either 13 or 29, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_PWM6 @@ -468,7 +468,7 @@ config RP23XX_PWM7A_GPIO either 14, any other value disables the output. Refer to board documentation to see if pin 14 is available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_PWM7B_GPIO int "GPIO pin for PWM7 channel 2 (15 or -1:no assign)" @@ -479,7 +479,7 @@ config RP23XX_PWM7B_GPIO either 15, any other value disables the output. Refer to board documentation to see if pin 15 is available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_PWM7 diff --git a/boards/arm/samv7/same70-xplained/configs/pwm/defconfig b/boards/arm/samv7/same70-xplained/configs/pwm/defconfig index 8f16621e1ba6a..abb1051b7aa81 100644 --- a/boards/arm/samv7/same70-xplained/configs/pwm/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/pwm/defconfig @@ -56,7 +56,6 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=3 CONFIG_RAM_SIZE=393216 CONFIG_RAM_START=0x20400000 diff --git a/boards/arm/samv7/same70-xplained/configs/pysim/defconfig b/boards/arm/samv7/same70-xplained/configs/pysim/defconfig index 9da1ba1c280b1..83516fa2eda7d 100644 --- a/boards/arm/samv7/same70-xplained/configs/pysim/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/pysim/defconfig @@ -101,7 +101,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_PTHREAD_STACK_MIN=1024 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=3 CONFIG_RAM_SIZE=393216 CONFIG_RAM_START=0x20400000 diff --git a/boards/arm/stm32/common/src/stm32_tone.c b/boards/arm/stm32/common/src/stm32_tone.c index 65abd425d6fd2..58bbcd22242ad 100644 --- a/boards/arm/stm32/common/src/stm32_tone.c +++ b/boards/arm/stm32/common/src/stm32_tone.c @@ -44,6 +44,10 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef BOARD_TONE_PWM_CHANNEL +# define BOARD_TONE_PWM_CHANNEL 1 +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -117,7 +121,7 @@ int board_tone_initialize(int devno) /* Register the Audio Tone driver at "/dev/tone0" */ snprintf(devpath, sizeof(devpath), "/dev/tone%d", devno); - ret = tone_register(devpath, tone, oneshot); + ret = tone_register(devpath, tone, BOARD_TONE_PWM_CHANNEL, oneshot); if (ret < 0) { auderr("ERROR: tone_register failed: %d\n", ret); diff --git a/boards/arm/stm32/common/src/stm32_xen1210.c b/boards/arm/stm32/common/src/stm32_xen1210.c index 085650e177708..1dcb2a2787ee6 100644 --- a/boards/arm/stm32/common/src/stm32_xen1210.c +++ b/boards/arm/stm32/common/src/stm32_xen1210.c @@ -225,8 +225,8 @@ static int xen1210_pwm_setup(void) /* Define frequency and duty cycle: 2MHz @ 50% */ - info.frequency = 2000000; /* 2MHz */ - info.duty = 32768; /* This value means 50% */ + info.frequency = 2000000; /* 2MHz */ + info.channels[0].duty = 32768; /* This value means 50% */ /* Initialize PWM */ diff --git a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig index ae10fd15e4c48..7c449ee522c3e 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig @@ -24,7 +24,6 @@ CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=2 CONFIG_RAM_SIZE=65536 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig index 8225f55014795..8f56b95cda311 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig @@ -25,7 +25,6 @@ CONFIG_LINE_MAX=80 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=4 CONFIG_RAM_SIZE=22528 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig index 42a7c2d4868c8..3c35b9f82b28d 100644 --- a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig +++ b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig @@ -64,7 +64,6 @@ CONFIG_NSH_READLINE=y CONFIG_PIPES=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32/photon/configs/rgbled/defconfig b/boards/arm/stm32/photon/configs/rgbled/defconfig index ca84d052dd346..d1096c8a84d31 100644 --- a/boards/arm/stm32/photon/configs/rgbled/defconfig +++ b/boards/arm/stm32/photon/configs/rgbled/defconfig @@ -37,7 +37,6 @@ CONFIG_PHOTON_IWDG=y CONFIG_PHOTON_WDG_THREAD=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=4 CONFIG_RAMLOG=y CONFIG_RAMLOG_BUFSIZE=8192 diff --git a/boards/arm/stm32/photon/src/stm32_rgbled.c b/boards/arm/stm32/photon/src/stm32_rgbled.c index 96c9c9a6082a7..c43f21b604ba1 100644 --- a/boards/arm/stm32/photon/src/stm32_rgbled.c +++ b/boards/arm/stm32/photon/src/stm32_rgbled.c @@ -57,10 +57,6 @@ # undef HAVE_RGBLED #endif -#ifndef CONFIG_PWM_MULTICHAN -# undef HAVE_RGBLED -#endif - #ifndef CONFIG_STM32_TIM2_PWM # undef HAVE_RGBLED #endif @@ -139,13 +135,9 @@ int stm32_rgbled_setup(void) /* Register the RGB LED diver at "/dev/rgbled0" */ -#ifdef CONFIG_PWM_MULTICHAN ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, RGBLED_BPWMCHANNEL); -#else - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb); -#endif if (ret < 0) { lederr("ERROR: rgbled_register failed: %d\n", ret); diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig index 393c1bbdddec9..cba32112192c0 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig @@ -32,6 +32,7 @@ CONFIG_LINE_MAX=80 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=3 CONFIG_RAM_SIZE=20480 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y diff --git a/boards/arm/stm32/stm32f103-minimum/include/board.h b/boards/arm/stm32/stm32f103-minimum/include/board.h index 45dd778262dc2..36ed8ae7f6979 100644 --- a/boards/arm/stm32/stm32f103-minimum/include/board.h +++ b/boards/arm/stm32/stm32f103-minimum/include/board.h @@ -186,6 +186,7 @@ /* Tone Driver **************************************************************/ #define BOARD_TONE_PWM_TIM 2 /* PWM timer for tone generation */ +#define BOARD_TONE_PWM_CHANNEL 2 /* PWM channel for tone generation */ #define BOARD_TONE_ONESHOT_TIM 3 /* Oneshot timer for note timings */ #define BOARD_TONE_ONESHOT_TIM_RES 10 /* Oneshot timer resolution (us) */ diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c index 1fa74def3ca79..3ba2dc47d783c 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c +++ b/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c @@ -126,7 +126,7 @@ int stm32_rgbled_setup(void) /* Define frequency and duty cycle */ info.frequency = 100; - info.duty = 0; + info.channels[0].duty = 0; /* Initialize LED R */ @@ -163,7 +163,9 @@ int stm32_rgbled_setup(void) /* Register the RGB LED diver at "/dev/rgbled0" */ - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb); + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, + RGBLED_BPWMCHANNEL); if (ret < 0) { lederr("ERROR: rgbled_register failed: %d\n", ret); diff --git a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig index 3afa110be2c4a..c5ebec8a82b82 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig @@ -32,6 +32,7 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=3 CONFIG_RAM_SIZE=131072 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c index e17d403c01c58..faaa9e4871b94 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c +++ b/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c @@ -126,7 +126,7 @@ int stm32_rgbled_setup(void) /* Define frequency and duty cycle */ info.frequency = 100; - info.duty = 0; + info.channels[0].duty = 0; /* Initialize LED R */ @@ -163,7 +163,9 @@ int stm32_rgbled_setup(void) /* Register the RGB LED diver at "/dev/rgbled0" */ - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb); + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + RGBLED_RPWMCHANNEL, RGBLED_GPWMCHANNEL, + RGBLED_BPWMCHANNEL); if (ret < 0) { lederr("ERROR: rgbled_register failed: %d\n", ret); diff --git a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig index 12ba2b303a997..48ded7700ac78 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig @@ -31,6 +31,7 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=3 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c b/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c index b71f840ccca46..983d11293bcab 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c @@ -114,7 +114,7 @@ int stm32_rgbled_setup(void) /* Define frequency and duty cycle */ info.frequency = 100; - info.duty = 0; + info.channels[0].duty = 0; /* Initialize LED R */ @@ -151,7 +151,9 @@ int stm32_rgbled_setup(void) /* Register the RGB LED diver at "/dev/rgbled0" */ - ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb); + ret = rgbled_register("/dev/rgbled0", ledr, ledg, ledb, + 1, CONFIG_STM32_TIM2_CHANNEL, + CONFIG_STM32_TIM3_CHANNEL); if (ret < 0) { lederr("ERROR: rgbled_register failed: %d\n", ret); diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig index 9e16858e87d4e..2fc1ae312753c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig @@ -50,7 +50,6 @@ CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 CONFIG_PTHREAD_MUTEX_UNSAFE=y CONFIG_PTHREAD_STACK_DEFAULT=1536 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_RAM_SIZE=20480 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig index ecc5faf6678e5..0112b71b52d77 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig @@ -75,7 +75,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_PTHREAD_STACK_MIN=1024 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=2 CONFIG_RAM_SIZE=245760 CONFIG_RAM_START=0x20010000 diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig index dfc6915718a0c..291c438c26cd2 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig @@ -74,7 +74,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_PTHREAD_STACK_MIN=1024 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=2 CONFIG_RAM_SIZE=245760 CONFIG_RAM_START=0x20010000 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h index a4cc20958f1fb..8ce1c6eee650e 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h @@ -104,6 +104,7 @@ /* PWM */ #define BUZZER_PWMTIMER 4 +#define BUZZER_PWMCHANNEL 2 /* OneShot Timer */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_tone.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_tone.c index 341117fcaca2f..655c9d8040c03 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_tone.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_tone.c @@ -155,7 +155,7 @@ int board_tone_initialize(int devno) /* Register the Audio Tone driver at "/dev/tone0" */ snprintf(devpath, 12, "/dev/tone%d", devno); - ret = tone_register(devpath, tone, oneshot); + ret = tone_register(devpath, tone, BUZZER_PWMCHANNEL, oneshot); if (ret < 0) { auderr("ERROR: tone_register failed: %d\n", ret); diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig index a501dab8470aa..36c6b375d46e0 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig @@ -35,7 +35,6 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=4 CONFIG_RAM_SIZE=245760 CONFIG_RAM_START=0x20010000 diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig index 9b95d63b8be4e..1148378b85553 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig @@ -72,7 +72,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_PTHREAD_STACK_MIN=1024 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_RAM_SIZE=245760 CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig index ee71e6b201906..5876e49c1e4e4 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig @@ -72,7 +72,6 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_PTHREAD_STACK_DEFAULT=2048 CONFIG_PTHREAD_STACK_MIN=1024 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_RAM_SIZE=245760 CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y diff --git a/boards/risc-v/bl602/bl602evb/configs/timer/defconfig b/boards/risc-v/bl602/bl602evb/configs/timer/defconfig index 507ca1af8c2aa..64f2e3cd9442d 100644 --- a/boards/risc-v/bl602/bl602evb/configs/timer/defconfig +++ b/boards/risc-v/bl602/bl602evb/configs/timer/defconfig @@ -59,7 +59,6 @@ CONFIG_NSH_STRERROR=y CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=8192 CONFIG_PTHREAD_STACK_DEFAULT=8192 CONFIG_PWM=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=2 CONFIG_RAM_SIZE=134217728 CONFIG_RAM_START=0xc0800000 diff --git a/boards/risc-v/rp23xx-rv/common/Kconfig b/boards/risc-v/rp23xx-rv/common/Kconfig index 707c2aefd5cc0..bcf3d7d9f7337 100644 --- a/boards/risc-v/rp23xx-rv/common/Kconfig +++ b/boards/risc-v/rp23xx-rv/common/Kconfig @@ -272,7 +272,7 @@ config RP23XX_RV_PWM0A_GPIO either 0 or 16, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_RV_PWM0B_GPIO int "GPIO pin for PWM0 channel 2 (1, 17 or -1:no assign)" @@ -283,7 +283,7 @@ config RP23XX_RV_PWM0B_GPIO either 1 or 17, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_RV_PWM0 @@ -300,7 +300,7 @@ config RP23XX_RV_PWM1A_GPIO either 2 or 18, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_RV_PWM1B_GPIO int "GPIO pin for PWM1 channel 2 (3, 19 or -1:no assign)" @@ -311,7 +311,7 @@ config RP23XX_RV_PWM1B_GPIO either 3 or 19, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_RV_PWM1 @@ -328,7 +328,7 @@ config RP23XX_RV_PWM2A_GPIO either 4 or 20, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_RV_PWM2B_GPIO int "GPIO pin for PWM2 channel 2 (5, 21 or -1:no assign)" @@ -339,7 +339,7 @@ config RP23XX_RV_PWM2B_GPIO either 5 or 21, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_RV_PWM2 @@ -356,7 +356,7 @@ config RP23XX_RV_PWM3A_GPIO either 6 or 22, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_RV_PWM3B_GPIO int "GPIO pin for PWM3 channel 2 (7, 23 or -1:no assign)" @@ -367,7 +367,7 @@ config RP23XX_RV_PWM3B_GPIO either 7 or 23, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_RV_PWM3 @@ -384,7 +384,7 @@ config RP23XX_RV_PWM4A_GPIO either 8 or 24, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_RV_PWM4B_GPIO int "GPIO pin for PWM4 channel 2 (9, 25 or -1:no assign)" @@ -395,7 +395,7 @@ config RP23XX_RV_PWM4B_GPIO either 9 or 25, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_RV_PWM4 @@ -412,7 +412,7 @@ config RP23XX_RV_PWM5A_GPIO either 10 or 26, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_RV_PWM5B_GPIO int "GPIO pin for PWM5 channel 2 (11, 27 or -1:no assign)" @@ -423,7 +423,7 @@ config RP23XX_RV_PWM5B_GPIO either 11 or 27, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_RV_PWM5 @@ -440,7 +440,7 @@ config RP23XX_RV_PWM6A_GPIO either 12 or 28, any other value disables the output. Refer to board documentation to see which pins are available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_RV_PWM6B_GPIO int "GPIO pin for PWM6 channel 2 (13, 29 or -1:no assign)" @@ -451,7 +451,7 @@ config RP23XX_RV_PWM6B_GPIO either 13 or 29, any other value disables the output. Refer to board documentation to see which pins are available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_RV_PWM6 @@ -468,7 +468,7 @@ config RP23XX_RV_PWM7A_GPIO either 14, any other value disables the output. Refer to board documentation to see if pin 14 is available. -if PWM_MULTICHAN && PWM_NCHANNELS > 1 +if PWM_NCHANNELS > 1 config RP23XX_RV_PWM7B_GPIO int "GPIO pin for PWM7 channel 2 (15 or -1:no assign)" @@ -479,7 +479,7 @@ config RP23XX_RV_PWM7B_GPIO either 15, any other value disables the output. Refer to board documentation to see if pin 15 is available. -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 +endif # PWM_NCHANNELS > 1 endif # RP23XX_RV_PWM7 diff --git a/boards/xtensa/esp32/common/src/esp32_rgbled.c b/boards/xtensa/esp32/common/src/esp32_rgbled.c index 31815a17345a4..b83e7c9ff5389 100644 --- a/boards/xtensa/esp32/common/src/esp32_rgbled.c +++ b/boards/xtensa/esp32/common/src/esp32_rgbled.c @@ -51,7 +51,7 @@ defined(CONFIG_ESP32_LEDC) && \ defined(CONFIG_ESP32_LEDC_TIM0) && \ (CONFIG_ESP32_LEDC_TIM0_CHANNELS >= 3) && \ - defined(CONFIG_PWM_MULTICHAN) && (CONFIG_PWM_NCHANNELS >= 3) + (CONFIG_PWM_NCHANNELS >= 3) /**************************************************************************** * Public Functions diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/configs/ble/defconfig b/boards/xtensa/esp32/esp32-sparrow-kit/configs/ble/defconfig index 2dec45c4af1c7..9091e0f2d015b 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/configs/ble/defconfig +++ b/boards/xtensa/esp32/esp32-sparrow-kit/configs/ble/defconfig @@ -86,7 +86,6 @@ CONFIG_NSH_READLINE=y CONFIG_PREALLOC_MQ_IRQ_MSGS=512 CONFIG_PREALLOC_MQ_MSGS=512 CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=3 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/configs/mqttc/defconfig b/boards/xtensa/esp32/esp32-sparrow-kit/configs/mqttc/defconfig index 8d0e40b3d652a..555c7e59a1619 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/configs/mqttc/defconfig +++ b/boards/xtensa/esp32/esp32-sparrow-kit/configs/mqttc/defconfig @@ -106,7 +106,6 @@ CONFIG_NSH_MMCSDSPIPORTNO=2 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_MUTEX_TYPES=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=3 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig index ea7c1a67a4d12..89ff9dfc89e6a 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig @@ -83,7 +83,6 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_MMCSDSPIPORTNO=2 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=3 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-sparrow-kit/configs/wifi/defconfig index 6a1963b4813d0..c2a75f2b3fc98 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-sparrow-kit/configs/wifi/defconfig @@ -110,7 +110,6 @@ CONFIG_NSH_READLINE=y CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048 CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_MUTEX_TYPES=y -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=3 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig index 6b3360e509500..f5976166afb4a 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig @@ -44,7 +44,6 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 -CONFIG_PWM_MULTICHAN=y CONFIG_PWM_NCHANNELS=2 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c index b005a51a8d73a..052daf7be5fc4 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c @@ -106,7 +106,7 @@ int board_lcd_initialize(void) /* Turn on LCD backlight (10% brightness) */ pwm.frequency = SZPI_LCD_PWM_FREQ; - pwm.duty = SZPI_LCD_PWM_DUTY; + pwm.channels[0].duty = SZPI_LCD_PWM_DUTY; ret = file_open(&g_pwm_file, SZPI_LCD_PWM_PATH, O_RDONLY); if (ret < 0) diff --git a/drivers/audio/tone.c b/drivers/audio/tone.c index 5488047c712aa..3504d012f11a4 100644 --- a/drivers/audio/tone.c +++ b/drivers/audio/tone.c @@ -83,9 +83,7 @@ struct tone_upperhalf_s { uint8_t crefs; /* The number of times the device has been * opened */ -#ifdef CONFIG_PWM_MULTICHAN uint8_t channel; /* Output channel that drives the tone. */ -#endif volatile bool started; /* True: pulsed output is being generated */ mutex_t lock; /* Supports mutual exclusion */ struct pwm_info_s tone; /* Pulsed output for Audio Tone */ @@ -290,12 +288,8 @@ static void start_note(FAR struct tone_upperhalf_s *upper, uint8_t note) FAR struct pwm_lowerhalf_s *tone = upper->devtone; upper->tone.frequency = g_notes_freq[note - 1]; -#ifdef CONFIG_PWM_MULTICHAN upper->tone.channels[0].channel = upper->channel; upper->tone.channels[0].duty = b16HALF; -#else - upper->tone.duty = b16HALF; -#endif /* REVISIT: Should check the return value */ @@ -310,12 +304,8 @@ static void stop_note(FAR struct tone_upperhalf_s *upper) { FAR struct pwm_lowerhalf_s *tone = upper->devtone; -#ifdef CONFIG_PWM_MULTICHAN upper->tone.channels[0].channel = upper->channel; upper->tone.channels[0].duty = 0; -#else - upper->tone.duty = 0; -#endif /* REVISIT: Should check the return value */ @@ -929,9 +919,7 @@ static ssize_t tone_write(FAR struct file *filep, FAR const char *buffer, ****************************************************************************/ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone, -#ifdef CONFIG_PWM_MULTICHAN int channel, -#endif FAR struct oneshot_lowerhalf_s *oneshot) { FAR struct tone_upperhalf_s *upper; @@ -954,9 +942,7 @@ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone, nxmutex_init(&upper->lock); upper->devtone = tone; upper->oneshot = oneshot; -#ifdef CONFIG_PWM_MULTICHAN upper->channel = (uint8_t)channel; -#endif upper->oneshot->callback = oneshot_callback; upper->oneshot->arg = upper; diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index def6776d887e1..5f0a1088d86ce 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -74,6 +74,7 @@ config LEDS_MAX7219 config RGBLED bool "RGB LED Driver Support" default n + depends on PWM_NCHANNELS >= 3 ---help--- This selection enables building of the "upper-half" RGB LED driver. See include/nuttx/rgbled.h for further PWM driver information. diff --git a/drivers/leds/rgbled.c b/drivers/leds/rgbled.c index 8a438e057d43a..f04638b8dcb37 100644 --- a/drivers/leds/rgbled.c +++ b/drivers/leds/rgbled.c @@ -62,11 +62,9 @@ struct rgbled_upperhalf_s FAR struct pwm_lowerhalf_s *devledr; FAR struct pwm_lowerhalf_s *devledg; FAR struct pwm_lowerhalf_s *devledb; -#ifdef CONFIG_PWM_MULTICHAN int chanr; /* Red PWM channel */ int chang; /* Green PWM channel */ int chanb; /* Blue PWM channel */ -#endif }; /**************************************************************************** @@ -280,9 +278,7 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer, unsigned int green; unsigned int blue; char color[3]; -#ifdef CONFIG_PWM_MULTICHAN int i; -#endif /* We need to receive a string #RRGGBB = 7 bytes */ @@ -359,7 +355,6 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer, blue ^= 0xffff; #endif -#ifdef CONFIG_PWM_MULTICHAN memset(&pwm, 0, sizeof(struct pwm_info_s)); pwm.frequency = CONFIG_RGBLED_PWM_FREQ; @@ -433,18 +428,6 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer, ledb->ops->start(ledb, &pwm); } -#else - pwm.frequency = CONFIG_RGBLED_PWM_FREQ; - - pwm.duty = red; - ledr->ops->start(ledr, &pwm); - - pwm.duty = green; - ledg->ops->start(ledg, &pwm); - - pwm.duty = blue; - ledb->ops->start(ledb, &pwm); -#endif return buflen; } @@ -471,8 +454,7 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer, * drivers for the red, green, and blue LEDs, respectively. These * instances will be bound to the RGB LED driver and must persists as * long as that driver persists. - * chanr, chang, chanb -Red/Green/Blue PWM channels (only if - * CONFIG_PWM_MULTICHAN is defined) + * chanr, chang, chanb -Red/Green/Blue PWM channels * * Returned Value: * Zero on success; a negated errno value on failure. @@ -482,9 +464,7 @@ static ssize_t rgbled_write(FAR struct file *filep, FAR const char *buffer, int rgbled_register(FAR const char *path, FAR struct pwm_lowerhalf_s *ledr, FAR struct pwm_lowerhalf_s *ledg, FAR struct pwm_lowerhalf_s *ledb -#ifdef CONFIG_PWM_MULTICHAN , int chanr, int chang, int chanb -#endif ) { FAR struct rgbled_upperhalf_s *upper; @@ -509,11 +489,9 @@ int rgbled_register(FAR const char *path, FAR struct pwm_lowerhalf_s *ledr, upper->devledg = ledg; upper->devledb = ledb; -#ifdef CONFIG_PWM_MULTICHAN upper->chanr = chanr; upper->chang = chang; upper->chanb = chanb; -#endif /* Register the PWM device */ diff --git a/drivers/timers/Kconfig b/drivers/timers/Kconfig index c98101103ebbf..b34721657af50 100644 --- a/drivers/timers/Kconfig +++ b/drivers/timers/Kconfig @@ -17,10 +17,6 @@ config ARCH_HAVE_PWM_DEADTIME bool default n -config ARCH_HAVE_PWM_MULTICHAN - bool - default n - config PWM bool "PWM Driver Support" default n @@ -64,16 +60,6 @@ config PWM_DEADTIME For detailed description about deadtime functionality please refer to architecture manuals and datasheets. -config PWM_MULTICHAN - bool "PWM Multiple Output Channel Support" - default n - depends on ARCH_HAVE_PWM_MULTICHAN - depends on !PWM_PULSECOUNT - ---help--- - Enables support for multiple output channels per timer. - -if PWM_MULTICHAN - config PWM_NCHANNELS int "Number of Output Channels Per Timer" default 1 @@ -82,7 +68,6 @@ config PWM_NCHANNELS Specifies the number of output channels per timer. Each timer may support fewer output channels than this value. -endif # PWM_MULTICHAN endif # PWM config CAPTURE diff --git a/drivers/timers/pwm.c b/drivers/timers/pwm.c index 4dd62fe28f2f1..cd583de509e1d 100644 --- a/drivers/timers/pwm.c +++ b/drivers/timers/pwm.c @@ -116,24 +116,18 @@ static const struct file_operations g_pwmops = static void pwm_dump(FAR const char *msg, FAR const struct pwm_info_s *info, bool started) { -#ifdef CONFIG_PWM_MULTICHAN int i; -#endif pwminfo("%s: frequency: %" PRId32 "\n", msg, info->frequency); -#ifdef CONFIG_PWM_MULTICHAN for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) { pwminfo(" channel: %d duty: %08" PRIx32 "\n", info->channels[i].channel, info->channels[i].duty); } -#else - pwminfo(" duty: %08" PRIx32 "\n", info->duty); -#endif #ifdef CONFIG_PWM_PULSECOUNT - pwminfo(" count: %" PRIx32 "\n", info->count); + pwminfo(" count: %" PRIx32 "\n", info->channels[0].count); #endif pwminfo(" started: %d\n", started); @@ -324,7 +318,7 @@ static int pwm_start(FAR struct pwm_upperhalf_s *upper, unsigned int oflags) * We do these things before starting the PWM to avoid race conditions. */ - upper->waiting = (upper->info.count > 0) && + upper->waiting = (upper->info.channels[0].count > 0) && ((oflags & O_NONBLOCK) == 0); upper->started = true; diff --git a/include/nuttx/audio/tone.h b/include/nuttx/audio/tone.h index bf41c39d51fe3..e5ec71cce353f 100644 --- a/include/nuttx/audio/tone.h +++ b/include/nuttx/audio/tone.h @@ -76,9 +76,7 @@ extern "C" ****************************************************************************/ int tone_register(FAR const char *path, FAR struct pwm_lowerhalf_s *tone, -#ifdef CONFIG_PWM_MULTICHAN int channel, -#endif FAR struct oneshot_lowerhalf_s *oneshot); #undef EXTERN diff --git a/include/nuttx/leds/rgbled.h b/include/nuttx/leds/rgbled.h index 849429fedd411..1a3621724cb0b 100644 --- a/include/nuttx/leds/rgbled.h +++ b/include/nuttx/leds/rgbled.h @@ -67,8 +67,7 @@ extern "C" * drivers for the red, green, and blue LEDs, respectively. These * instances will be bound to the RGB LED driver and must persists as * long as that driver persists. - * chanr, chang, chanb -Red/Green/Blue PWM channels (only if - * CONFIG_PWM_MULTICHAN is defined) + * chanr, chang, chanb - Red/Green/Blue PWM channels. * * Returned Value: * Zero on success; a negated errno value on failure. @@ -77,10 +76,8 @@ extern "C" int rgbled_register(FAR const char *path, FAR struct pwm_lowerhalf_s *ledr, FAR struct pwm_lowerhalf_s *ledg, - FAR struct pwm_lowerhalf_s *ledb -#ifdef CONFIG_PWM_MULTICHAN - , int chanr, int chang, int chanb -#endif + FAR struct pwm_lowerhalf_s *ledb, + int chanr, int chang, int chanb ); #undef EXTERN diff --git a/include/nuttx/timers/pwm.h b/include/nuttx/timers/pwm.h index f59df5e3edb6b..d0c2a2f9efa45 100644 --- a/include/nuttx/timers/pwm.h +++ b/include/nuttx/timers/pwm.h @@ -52,6 +52,10 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef CONFIG_PWM_NCHANNELS +# define CONFIG_PWM_NCHANNELS 1 +#endif + /* Configuration ************************************************************/ /* CONFIG_PWM - Enables because PWM driver support @@ -59,9 +63,6 @@ * number of pulses. This might be used, for example to support a stepper * motor. If the hardware will support a fixed pulse count, then this * configuration should be set to enable the capability. - * CONFIG_PWM_MULTICHAN - Enables support for multiple output channels per - * timer. If selected, then CONFIG_PWM_NCHANNELS must be provided to - * indicated the maximum number of supported PWM output channels. * CONFIG_DEBUG_PWM_INFO - This will generate output that can be use to * debug the PWM driver. */ @@ -159,7 +160,6 @@ * structure describes the output state on one channel. */ -#ifdef CONFIG_PWM_MULTICHAN struct pwm_chan_s { ub16_t duty; @@ -174,8 +174,12 @@ struct pwm_chan_s uint8_t cpol; uint8_t dcpol; int8_t channel; -}; + +#ifdef CONFIG_PWM_PULSECOUNT + uint32_t count; /* The number of pulse to generate. 0 means to + * generate an indefinite number of pulses */ #endif +}; /* This structure describes the characteristics of the pulsed output */ @@ -183,27 +187,10 @@ struct pwm_info_s { uint32_t frequency; /* Frequency of the pulse train */ -#ifdef CONFIG_PWM_MULTICHAN - /* Per-channel output state */ + /* Per-channel output state */ struct pwm_chan_s channels[CONFIG_PWM_NCHANNELS]; -#else - ub16_t duty; /* Duty of the pulse train, "1"-to-"0" duration. - * Maximum: 65535/65536 (0x0000ffff) - * Minimum: 1/65536 (0x00000001) */ -#ifdef CONFIG_PWM_DEADTIME - ub16_t dead_time_a; /* Dead time value for main output */ - ub16_t dead_time_b; /* Dead time value for complementary output */ -#endif -# ifdef CONFIG_PWM_PULSECOUNT - uint32_t count; /* The number of pulse to generate. 0 means to - * generate an indefinite number of pulses */ -# endif - uint8_t cpol; /* Channel polarity */ - uint8_t dcpol; /* Disabled channel polarity */ -#endif /* CONFIG_PWM_MULTICHAN */ - FAR void *arg; /* User provided argument to be used in the * lower half */ };