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riscv32: Update riscv32_progbuf_mem_read to use both x10 & x11
1 parent fbac7d8 commit ade8a0a

1 file changed

Lines changed: 15 additions & 20 deletions

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src/target/riscv32.c

Lines changed: 15 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -580,15 +580,18 @@ static void riscv32_progbuf_mem_read(
580580
const uint8_t access_width = riscv_mem_access_width(hart, src, len);
581581
const uint8_t access_length = 1U << access_width;
582582

583-
/* RV32I opcodes: load word/half/byte from address A0 into A0 (clobber) */
584-
static const uint32_t progbuf_read32[1] = {
585-
0x00052503U, // lw a0, 0(a0)
583+
/* RV32I opcodes: load word/half/byte from address A0 into A1 (clobber), postincrement A0 */
584+
static const uint32_t progbuf_read32[2] = {
585+
0x00052583U, // lw a1, 0(a0)
586+
0x00450513U, // addi a0, a0, 4
586587
};
587-
static const uint32_t progbuf_read16[1] = {
588-
0x00051503U, // lh a0, 0(a0)
588+
static const uint32_t progbuf_read16[2] = {
589+
0x00051583U, // lh a1, 0(a0)
590+
0x00450513U, // addi a0, a0, 4
589591
};
590-
static const uint32_t progbuf_read8[1] = {
591-
0x00050503U, // lb a0, 0(a0)
592+
static const uint32_t progbuf_read8[2] = {
593+
0x00050583U, // lb a1, 0(a0)
594+
0x00450513U, // addi a0, a0, 4
592595
};
593596
const uint32_t *progbuf_read = progbuf_read32;
594597
switch (access_width) {
@@ -604,14 +607,6 @@ static void riscv32_progbuf_mem_read(
604607
default:
605608
return;
606609
}
607-
#if 0
608-
/* assume ptr is in A0, load word/half/byte to A1 (clobber), postincrement A0 */
609-
static const uint32_t progbuf_read32_autoexec[2] = {
610-
0x00052583U, // lw a1, 0(a0)
611-
0x00450513U, // addi a0, a0, 4
612-
}
613-
DEBUG_TARGET("%s: 0x%08x+%lu width %u\n", __func__, src, len, access_width);
614-
#endif
615610
/* Fill the program buffer */
616611
if (!riscv_dm_write(hart->dbg_module, RV_DM_PROGBUF_BASE, progbuf_read[0]))
617612
return;
@@ -622,9 +617,9 @@ static void riscv32_progbuf_mem_read(
622617
}
623618

624619
uint32_t a0_save = 0;
625-
//uint32_t a1_save = 0;
620+
uint32_t a1_save = 0;
626621
riscv_csr_read(hart, RV_GPR_A0, &a0_save);
627-
//riscv_csr_read(hart, RV_GPR_A0 + 11, &a1_save);
622+
riscv_csr_read(hart, RV_GPR_A0 + 1, &a1_save);
628623

629624
uint8_t *const data = (uint8_t *)dest;
630625
for (size_t offset = 0; offset < len; offset += access_length) {
@@ -640,9 +635,9 @@ static void riscv32_progbuf_mem_read(
640635
if (!result)
641636
return;
642637
#if 1
643-
/* Copy the read value from GPR A0 to DATA0 */
638+
/* Copy the read value from GPR A1 to DATA0 */
644639
const uint32_t abstract_command2 =
645-
RV_DM_ABST_CMD_ACCESS_REG | RV_ABST_READ | RV_REG_XFER | RV_REG_ACCESS_32_BIT | RV_GPR_A0;
640+
RV_DM_ABST_CMD_ACCESS_REG | RV_ABST_READ | RV_REG_XFER | RV_REG_ACCESS_32_BIT | (RV_GPR_A0 + 1);
646641
result = riscv_dm_write(hart->dbg_module, RV_DM_ABST_COMMAND, abstract_command2);
647642
result &= riscv_command_wait_complete(hart);
648643
if (!result)
@@ -659,7 +654,7 @@ static void riscv32_progbuf_mem_read(
659654
}
660655

661656
riscv_csr_write(hart, RV_GPR_A0, &a0_save);
662-
//riscv_csr_write(hart, RV_GPR_A0 + 1, &a1_save);
657+
riscv_csr_write(hart, RV_GPR_A0 + 1, &a1_save);
663658
}
664659

665660
static void riscv32_progbuf_mem_write(

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