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Merge pull request #20 from choco-technologies/copilot/add-weak-prototypes-for-interrupts
Add weak interrupt handler prototypes for RTOS-essential ISRs
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README.md

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@@ -56,6 +56,12 @@ Software timers for periodic or one-shot callbacks:
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- `dmosi_timer_stop()` - Stop a timer
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- `dmosi_timer_reset()` - Reset a timer
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### 7. **Interrupt Handler API**
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Weak (no-op) prototypes for RTOS-essential interrupt handlers with architecture-independent dmosi names. RTOS-specific implementations override these to hook into the relevant hardware interrupts:
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- `dmosi_context_switch_handler()` — RTOS context switch (ARM Cortex-M: `PendSV_Handler`; RISC-V: software interrupt ISR)
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- `dmosi_syscall_handler()` — RTOS system/supervisor call (ARM Cortex-M: `SVC_Handler`; RISC-V: ecall / machine-mode trap handler)
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- `dmosi_tick_handler()` — RTOS periodic time tick (ARM Cortex-M: `SysTick_Handler`; RISC-V: machine timer interrupt handler)
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## Usage
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### Basic Integration

include/dmosi.h

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@@ -677,4 +677,68 @@ DMOD_BUILTIN_API( dmosi, 1.0, uint32_t, _timer_get_period, (dmosi_timer_t t
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/** @} */ // end of DMOSI_TIMER_API
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//==============================================================================
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// Interrupt Handler API
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//==============================================================================
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/**
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* @defgroup DMOSI_IRQ_API Interrupt Handler API
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* @brief Weak prototypes for RTOS-essential interrupt handlers
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*
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* These handlers represent the three interrupt roles that every RTOS requires
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* for correct operation. Each RTOS and each hardware architecture names these
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* interrupts differently; the dmosi names below are architecture-independent
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* and describe the functional role of the handler.
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*
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* An RTOS port provides strong implementations that forward to the
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* architecture-specific ISR names, for example:
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*
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* | dmosi handler | ARM Cortex-M | RISC-V |
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* |-----------------------------|----------------------|-------------------------|
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* | dmosi_context_switch_handler | PendSV_Handler | software interrupt ISR |
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* | dmosi_syscall_handler | SVC_Handler | ecall / machine-mode ISR|
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* | dmosi_tick_handler | SysTick_Handler | timer interrupt ISR |
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* @{
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*/
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/**
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* @brief RTOS context-switch handler
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*
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* Invoked by the RTOS to perform a context switch between tasks/threads.
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* Override this weak (no-op) implementation with the RTOS-specific
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* context-switch routine.
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*
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* Architecture mapping examples:
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* - ARM Cortex-M: @c PendSV_Handler
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* - RISC-V: software interrupt handler
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*/
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DMOD_BUILTIN_API( dmosi, 1.0, void, _context_switch_handler, (void) );
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/**
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* @brief RTOS system-call (supervisor-call) handler
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*
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* Invoked when user code requests privileged OS services via a trap/call
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* instruction. Override this weak (no-op) implementation with the
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* RTOS-specific system-call entry routine.
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*
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* Architecture mapping examples:
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* - ARM Cortex-M: @c SVC_Handler
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* - RISC-V: ecall / machine-mode trap handler
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*/
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DMOD_BUILTIN_API( dmosi, 1.0, void, _syscall_handler, (void) );
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/**
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* @brief RTOS periodic tick handler
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*
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* Invoked by the hardware timer that drives the RTOS time base. Used for
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* task scheduling, timeouts, and delay management. Override this weak (no-op)
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* implementation with the RTOS-specific tick routine.
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*
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* Architecture mapping examples:
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* - ARM Cortex-M: @c SysTick_Handler
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* - RISC-V: machine timer interrupt handler
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*/
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DMOD_BUILTIN_API( dmosi, 1.0, void, _tick_handler, (void) );
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/** @} */ // end of DMOSI_IRQ_API
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#endif // DMOSI_H

src/dmosi.c

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return 0;
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}
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//==============================================================================
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// Interrupt Handler API
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//==============================================================================
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DMOD_INPUT_WEAK_API_DECLARATION( dmosi, 1.0, void, _context_switch_handler, (void) )
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{
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}
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DMOD_INPUT_WEAK_API_DECLARATION( dmosi, 1.0, void, _syscall_handler, (void) )
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{
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}
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DMOD_INPUT_WEAK_API_DECLARATION( dmosi, 1.0, void, _tick_handler, (void) )
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{
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}
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//==============================================================================
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// DMOD Mutex API Implementation
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//==============================================================================

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