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Timur Kristófgregkh
Timur Kristóf
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gregkh
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drm/amd/display: Fix DCE 6.0 and 6.4 PLL programming.
[ Upstream commit 35222b5 ] Apparently, both DCE 6.0 and 6.4 have 3 PLLs, but PLL0 can only be used for DP. Make sure to initialize the correct amount of PLLs in DC for these DCE versions and use PLL0 only for DP. Also, on DCE 6.0 and 6.4, the PLL0 needs to be powered on at initialization as opposed to DCE 6.1 and 7.x which use a different clock source for DFS. The following functions were used as reference from the old radeon driver implementation of DCE 6.x: - radeon_atom_pick_pll - atombios_crtc_set_disp_eng_pll Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rosen Penev <rosenp@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1 parent fd1b69d commit 85229e1

2 files changed

Lines changed: 25 additions & 14 deletions

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‎drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -245,6 +245,11 @@ int dce_set_clock(
245245
pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10;
246246
pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
247247

248+
/* DCE 6.0, DCE 6.4: engine clock is the same as PLL0 */
249+
if (clk_mgr_base->ctx->dce_version == DCE_VERSION_6_0 ||
250+
clk_mgr_base->ctx->dce_version == DCE_VERSION_6_4)
251+
pxl_clk_params.pll_id = CLOCK_SOURCE_ID_PLL0;
252+
248253
if (clk_mgr_dce->dfs_bypass_active)
249254
pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true;
250255

‎drivers/gpu/drm/amd/display/dc/dce60/dce60_resource.c‎

Lines changed: 20 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -373,7 +373,7 @@ static const struct resource_caps res_cap = {
373373
.num_timing_generator = 6,
374374
.num_audio = 6,
375375
.num_stream_encoder = 6,
376-
.num_pll = 2,
376+
.num_pll = 3,
377377
.num_ddc = 6,
378378
};
379379

@@ -389,7 +389,7 @@ static const struct resource_caps res_cap_64 = {
389389
.num_timing_generator = 2,
390390
.num_audio = 2,
391391
.num_stream_encoder = 2,
392-
.num_pll = 2,
392+
.num_pll = 3,
393393
.num_ddc = 2,
394394
};
395395

@@ -982,21 +982,24 @@ static bool dce60_construct(
982982

983983
if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
984984
pool->base.dp_clock_source =
985-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
985+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
986986

987+
/* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
987988
pool->base.clock_sources[0] =
988-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
989+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
989990
pool->base.clock_sources[1] =
990-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
991+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
991992
pool->base.clk_src_count = 2;
992993

993994
} else {
994995
pool->base.dp_clock_source =
995-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
996+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
996997

997998
pool->base.clock_sources[0] =
998-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
999-
pool->base.clk_src_count = 1;
999+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1000+
pool->base.clock_sources[1] =
1001+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1002+
pool->base.clk_src_count = 2;
10001003
}
10011004

10021005
if (pool->base.dp_clock_source == NULL) {
@@ -1374,21 +1377,24 @@ static bool dce64_construct(
13741377

13751378
if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
13761379
pool->base.dp_clock_source =
1377-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1380+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
13781381

1382+
/* DCE 6.0 and 6.4: PLL0 can only be used with DP. Don't initialize it here. */
13791383
pool->base.clock_sources[0] =
1380-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1384+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
13811385
pool->base.clock_sources[1] =
1382-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1386+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
13831387
pool->base.clk_src_count = 2;
13841388

13851389
} else {
13861390
pool->base.dp_clock_source =
1387-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1391+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
13881392

13891393
pool->base.clock_sources[0] =
1390-
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1391-
pool->base.clk_src_count = 1;
1394+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1395+
pool->base.clock_sources[1] =
1396+
dce60_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1397+
pool->base.clk_src_count = 2;
13921398
}
13931399

13941400
if (pool->base.dp_clock_source == NULL) {

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